Quill, Shift-Enter and <br> tags

Everything in this post relates to Quill v1.3.7. I don’t do web tech for a living, and my knowledge on Quill is merely based upon reading its sources. Besides, I eventually picked another editor for my own use.

Introduction

These are my somewhat wandering and inconsistent notes as I solved the issue of Shift-Enter for Quill, on my own behalf. I ended up with the solution outlined in the last section of this post. So the vast majority of this post describes things I didn’t use in the end, however I left them as they say a few things on how to program with Quill.

Only when I had finished my own <br> inserting blot (which is what this post is about, actually), I found this rather equivalent one. Well, it’s probably better than mine, as it apparently supports <br> in pasted input. But what makes that solution interesting is how similar it is to mine (great minds think alike?), and yet it’s different in some aspects.

Note to self: There are unapplied commits in my own git repo with the options I didn’t go for eventually.

To <br> or not to <br>

Quill’s lack of support for the Shift-Enter generation of a <br> tag seems to irritate a few people out there, so the immediate question is what it’s actually needed for.

It’s worth to point out that the <br> is a bit of an anomaly in the world of HTML and DOM, since the commonly used tags for finishing horizontal packing of elements and move down vertically, are tags that enclose a chunk of HTML code, e.g. <p> and </p>, <div> and </div> etc. Hence the normal way to control vertical spacing is to enclose a vertical segment of the document, and put all the elements as the children of the DOM node that the tag generates.

Actually, there’s also <hr>, but it’s likewise messy in this sense. Maybe there are another few, but the point is that these would surely not have been included in the standard, had it been written today.

Analyzing a DOM containing <br>, it’s evident that it’s implemented as a zero by zero pixels element at the end of the line it appears in, and apparently it has this magic thing that it forces a new line.

As for Quill, it’s quite understandable that the idea of a <br> is rejected, since it breaks Quill’s model saying that vertical spacing is represented only by Block blots, and everything that comes until the next Block blot is the former blot’s children in the Parchment tree. This has been softened up a bit with the introduction of the Container blot, but <br> has still no place there.

So the question is: Is there any good reason to use <br> in documents? I’d say no. But then, when do I personally use Shift-Enter? I can think about two scenarios:

  • For creating text with narrower vertical spacing, for example in footnotes under a table. Since a regular Enter creates a paragraph, it’s typically vertically spaced from the previous one. <br> is usually closer.
  • For starting a new line within a list (i.e. within a <li> + </li> pair). Regular Enter starts a new bullet, Shift-Enter starts a new line within the current bullet.

None of these require the <br> tag, though. Shift-Enter could create a <p> or <div> tag with a class that has a smaller vertical spacing, and inside a list, it could create a <p> tag instead of a creating a new bullet.

Another important scenario is when pasting a several lines of text. Should the newlines translate into paragraphs or <br>’s? It depends on the scenario, more than anything.

How browsers respond to Shift-Enter

Most non-Quill editors use the contenteditable attribute to let the browser’s internal rich text editor do the heavy lifting.

Both Firefox and Chrome create a <div> + </div> pair when pressing Enter. With Shift-Enter, both generate a <br> tag, as expected. However if the cursor is positioned at the end of a paragraph or some other vertical enclosure, two <br> tags are created. The text that is typed immediately after pressing Shift-Enter is inserted between the two <br> tags on Firefox, and instead of the second <br> tag in Chrome.

The reason two <br> tags are inserted is that otherwise the cursor doesn’t go down to the following line. Don’t ask me why exactly, but apparently if a vertical container ends with a <br>, the cursor can’t be placed after it.

My implementation for <br>

So this is my JavaScript snippet for implementing the insertion of <br> on typing Shift-Enter. Actually, it pushes two <br> elements in the same scenarios just discussed. This means that pointless, useless but nevertheless harmless <br> might be hidden in the edited document forever (or until deleted by moving the cursor just before the new line, and pressing “Delete” on the keyboard, removing the invisible <br>).

It’s a plain JavaScript add-on, working with Quill v1.3.7. Well, working most of the time. In a plain paragraph it works, inside lists it works, but inside a code clause it may not work. And when pasting something that contains <br>, well, it’s not even in the loop.

The idea behind this code is to mimic the behavior of inserting an Image, as implemented in Quill’s Image class. If it works with an <img> it should work with a <br>.

(function() {
  var Parchment = Quill.import('parchment');
  var Delta = Quill.import('delta');

  class ShiftEnterBlot extends Parchment.Embed {} // Actually EmbedBlot
  ShiftEnterBlot.blotName = 'ShiftEnter';
  ShiftEnterBlot.tagName = 'br';

  Quill.register(ShiftEnterBlot);

  quill.keyboard.bindings[13].unshift({
    key: 13,
    shiftKey: true,
    handler: function(range) {
	quill.updateContents(new Delta()
			     .retain(range.index)
			     .delete(range.length)
			     .insert({ "ShiftEnter": true }),
			     'user');

	if (!quill.getLeaf(range.index + 1)[0].next) {
	  quill.updateContents(new Delta()
			       .retain(range.index + 1)
			       .delete(0)
			       .insert({ "ShiftEnter": true }),
			       'user');
	}

	quill.setSelection(range.index + 1, Quill.sources.SILENT);
	return false; // Don't call other candidate handlers
      }});
 })();

And now to a walkthrough of this code. Maybe it’s the only part of this post that is actually worth something.

The ShiftEnter blot

First, the Parchment and Delta modules are imported. Then the ShiftEnterBlot is defined as an extension of Parchment.Embed, which is actually Parchment’s EmbedBlot class. The naming is confusing.

I had previously failed with importing ‘blots/embed’ (apparently FormulaBlot) as well as ‘blots/block/embed’ (BlockEmbed).

How did I figure out that EmbedBlot is available as Parchment.Embed? It can be deduced from Quill’s sources, but I went for some reverse engineering of the JavaScript packaging.

So the trick was to search quill.js for lines saying exports.default, and nail down the one with

exports.default = EmbedBlot;

That line finishes the code for that export, and just below it there was a comment saying

/***/ }),
/* 49 */
/***/

so that’s the code for the next segment. Hence the index for EmbedBlot is 48. Somewhere else in quill.js, there’s a line saying

var embed_1 = __webpack_require__(48);

and then there’s

var Parchment = {
    Scope: Registry.Scope,
    create: Registry.create,
    Leaf: leaf_1.default,
[ ... ]
    Embed: embed_1.default,
    Scroll: scroll_1.default,
[ ... ]
    },
};
exports.default = Parchment;

So there we have it that EmbedBlot is exported as Parchment.Embed.

With this at hand, the new blot class is registered:

  ShiftEnterBlot.blotName = 'ShiftEnter';
  ShiftEnterBlot.tagName = 'br';

  Quill.register(ShiftEnterBlot);

It’s given a name and a tag. The name appears in the Delta, and the tag in the DOM. There’s always one blot for one DOM element and vice versa.

Keyboard handler registration

The part it the snippet above is this:

  quill.keyboard.bindings[13].unshift({
    key: 13,
    shiftKey: true,
    handler: function(range) {

This is where the function that is given next is set to become the first function to be processed when Shift-Enter is pressed. My first attempt was to use quill.keyboard.addBinding(), but since the handlers are processed in the order they were registered. Since Quill’s default handlers are added at initialization, the only way to prevent them is to add them in the configuration. In other words, the binding should appear where the Quill object is created, under modules: { keyboard: { bindings: .. } } }.

Or with the hack shown above.

Shoving in a <br> or two

So the handler goes on with

	quill.updateContents(new Delta()
			     .retain(range.index)
			     .delete(range.length)
			     .insert({ "ShiftEnter": true }),
			     'user');

This is where my implementation and the other one go different ways: I’m creating a Delta object, requesting to add a ShiftEnter blot. The other implementation uses insertEmbed() instead. Which I failed colossally with: I got a <br> inserted indeed, but the DOM became populated with leftovers from a Cursor blot. In short, it messed up. I suspect that it worked on the other implementation, because it sets the value to “\n” and length() accordingly. But I’m not sure.

This way or another, pushing a Delta is based upon the formal API, and is hence safer, I guess.

As for the second, optional <br>, the code goes on with:

	if (!quill.getLeaf(range.index + 1)[0].next) {
	  quill.updateContents(new Delta()
			       .retain(range.index + 1)
			       .delete(0)
			       .insert({ "ShiftEnter": true }),
			       'user');
	}

The getLeaf() call gets the ShiftEnterBlot object of the newly inserted <br>, and checks if its the last sibling in the subtree. If so, the <br> is the last element in the DOM’s subtree, since the trees are equally shaped. And if this is indeed the case, a second blot is pushed in. The other implementation does something similar, but instead of looking at the blot’s @next property, it compares the parents of the current blot with the one at index+1.

And then finally, the cursor is moved and the handler returns with false to indicate that the keystroke’s processing is completed (i.e. the other handlers, if present, aren’t reached):

	quill.setSelection(range.index + 1, Quill.sources.SILENT);
	return false; // Don't call other candidate handlers

Some notes on the other implementation

The other implementation has other differences from mine. The most important one is that it extend the Break blot, which in turn extends Parchment.Embed. I went for Parchment.Embed directly. This probably explains the part in the other implementation that goes

    insertInto(parent, ref) {
      Embed.prototype.insertInto.call(this, parent, ref);
    }}

This seems to skip Break class’ insertInto() method, by going directly to Embed’s method. So it would probably have been better to extend Parchment.Embed like I did.

Another thing about that other implementation is that it adds a matcher for <br> tags as follows:

function lineBreakMatcher() {
  var Delta = Quill.import("delta");
  var newDelta = new Delta();
  newDelta.insert({ break: "" });
  return newDelta;
}

However oddly enough, this generates <br> elements in the DOM without any reference to their related blot (i.e. without a __blot property), which causes exceptions in Quill’s on core code as it traverses the DOM. So I’m not sure what happened here.

A completely different approach

As mentioned above, I ended up adopting the method explained below. However I wouldn’t recommend this on an editor for other people to use, because odds are that they will complain about weird behavior. It’s not weird when one understands how it works, so this is good for my own use.

Recall that the real reason I want Shift-Enter is for starting a new paragraph inside a list item. So how about inserting a pair of <p>-</p> tags on Ctrl-Enter, and declare that as Inline blot, so it can live under Block blots?

The problem with inline blots is that if there are two such one after the other (say, multiple small paragraphs inside a list bullet), they will be fused into one by optimization. But that can be solved. Consider this:

(function() {
  var Inline = Quill.import('blots/inline');
  var Parchment = Quill.import('parchment');

  class ShiftEnterBlot extends Inline {
    static create(value) {
      let node = super.create(value);
      node.__rand = value;
      return node;
    }

    static formats(domNode) {
      let blot = Parchment.find(domNode);

      if (blot && blot.parent && blot.parent.children &&
	  blot.parent.children.head !== blot)
	return domNode.__rand;
    }
  }

  ShiftEnterBlot.blotName = 'ShiftEnter';
  ShiftEnterBlot.tagName = 'p';
  ShiftEnterBlot.className = 'shift-enter-class';

  Inline.order.push(ShiftEnterBlot.blotName);

  Quill.register(ShiftEnterBlot);

  quill.keyboard.bindings[13].unshift({
    key: 13,
	shiftKey: true,
	handler: function(range) {
	quill.format('ShiftEnter', 'rand-' + Math.floor(1000000000 * Math.random()));

	return false; // Don't call other candidate handlers
      }});
 })();

So when Ctrl-Shift is called, a call to format() is made, to apply a bogus inline format named ShiftEnter on the current selection or position. It’s like applying bold or italics, but with the wrapper tag <p> instead. So it creates a new paragraph. Actually, something of the sort of

<p class="shift-enter-class">text</p>

so these <p> enclosures have a dedicated class. Useful for obtaining lines with smaller space, just like <br> usually gives. If desirable, of course.

In order to prevent the fusing of adjacent paragraphs of this sort, each is given a random number as its value. This value is kept in a hidden property of the resulting DOM object, __rand. What prevents these from fusing into one chunk is the formats() method, which returns this random number. By doing so, Quill treats each segment with different random number as non-fusable. By the same coin, formats() returns an undefined value (i.e. no return statement at all) if the ShiftEnter blot is the first one in the line: It’s not just pointless to start a <p> pair there, but necessary for e.g. list items: Since pressing Enter causes Quill to copy all formats to the next paragraph, or list item, this would have meant that the line begins a line after the bullet.

By virtue of Quill’s optimization and canonization, these <p> enclosures are never nested into each other.

This random number is invisible in innerHTML, since it’s a property of the DOM objects and not an attribute, however it’s visible (as it has to be) in the Delta representation.

The Inline.order.push() call makes sure that ShiftEnter isn’t cut into pieces by other Inline formats, as explained in a separate post of mine.

Even though Shift-Enter behaves as one would expect when it’s used to terminate a line, some unexpected things happen when used in the middle of a line, or when text is selected. In particular it may come unexpected that the correct way to push down existing text into a new line is to select it and then press Shift-Enter. It’s not weird if one understands that it’s some kind of inline text formatting, which is why I argued above that it’s good for me but not for anyone to use.

Quill internals: formatAt() in detail, and nesting of DOM tags

Everything in this post relates to Quill v1.3.7. I don’t do web tech for a living, and my knowledge on Quill is merely based upon reading its sources. Besides, I eventually picked another editor for my own use..

Introduction

This post is a collection of findings I made while trying to figure out the following: Consider this simple HTML code

None enabled, <em><strong>bold and italic, </strong>only italic.</em>

which is visually formatted as follows:

None enabled, bold and italic, only italic.

Note that there’s a part starting with bold and italic, and then the bold is taken off, leaving italic only. Oddly enough, when pasting the formatted line above into Quill, the resulting innerHTML is

<p>None enabled, <strong><em>bold and italic, </em></strong><em>only italic.</em></p>

Because Quill chose to put the <strong> tag first and the <em> afterwards, it was forced to insert an </em> to allow for inserting </strong>, and then re-enable italic with <em>.

This is suboptimal, however harmless with these tags, but recall that <a> tags for links are also implemented as Inline blot extensions, so what happens if the text of a link is partly bold? Could Quill create two separate links, one for the part in bold, and one for the part that isn’t, because of the same issue shown above with nested tags? The short answer is of course no, and I’ll just explain how Quill is designed to ensure this won’t happen.

But this is an opportunity to point out, that if a link spans several Block blots (for example, several paragraphs), Quill will create a different <a>-</a> tag pair inside each paragraph. Just try it out: Select several paragraphs in the editor, and assign that text a link, and then look at the exported HTML or the DOM with the browser’s DOM viewer.

Frankly speaking, I’m not sure if it’s legal to have a link spanning across paragraphs (something like <a href=”/”> <p> This </p> <p> That </p> </a>) but it’s an uncommon use case, so who cares.

What’s important is that changing the formatting inside a small text segment won’t turn it into two links, and that doesn’t happen. The magic behind this is explained next.

DOM tree ordering: The problem

First, let’s understand the problem. Suppose there’s a piece of text in the document saying Hello: Five characters, already italics. HTML-wise, it’s <em>Hello</em>. From a blot perspective, it’s an Italic (Inline) blot with one child, a Textblot, containing the “Hello” string.

Now I mark all five characters and press the bold button on the editor. This results in a call to formatAt() with the index and length of the selected text. Say, something like

quill.scroll.formatAt(105, 5, 'bold', 'true');

I should mention that formatAt() is an internal function, and it doesn’t update the Delta representation of the document. The recommended API call is format() and friends.

A call to formatAt() results in a whole lot of activity, but the punchline is the creation of a new Bold blot and the call to wrap() (defined in the ShadowBlot class), which puts a Bold blot at the position of the blot that it’s formatting, and makes the latter the child of the former. From an HTML point of view, the <strong>-</strong> wrap everything inbetween, hence the method’s name.

I was deliberately ambiguous regarding what exactly is being wrapped, because that’s the big question: The formatAt() call relates to positions in the document, but format blots themselves contribute zero length. Therefore, that range with length 5 could mean the text only, or the text wrapped with italic tags. In other words, the wrap() call could be applied to the Textblot directly or to the Italic blot, and both would satisfy the request.

To ensure consistent behavior, there’s this little snippet in Quill’s blots/inline.js:

// Lower index means deeper in the DOM tree, since not found (-1) is for embeds
Inline.order = [
  'cursor', 'inline',   // Must be lower
  'underline', 'strike', 'italic', 'bold', 'script',
  'link', 'code'        // Must be higher
];

So the @order array of the Inline class defines which formatting blot become the parent of which, which is the same as saying which DOM tag become the parent of which. Or which HTML tags wrap which.

As the comment says, the elements appearing later in this list get a higher place in the DOM hierarchy. As one would expect, “link” appears almost last, so other formatting tags are pushed between the <a>-</a> tag and not vice versa. So as one would expect, formatting inside link text never generates multiple links. Only a “code” blot can do that.

As for blot classes that aren’t listed, they get lowest down in the DOM (as if they were before “cursor”), and if two unknown blot classes compete, it’s as if they were listed in this array in alphabetical order.

The important takeaway is that if you’re writing a blot that extends Inline (even indirectly), you may want to add it to the list somewhere towards the end, if having it divided into segments is an issue (like with the Link blot).

This is done more or less like this — with emphasis on the part marked in red.

var Inline = Quill.import('blots/inline');

class MyBlot extends Inline {
  [ ... ]
}
MyBlot.blotName = 'myblot';
MyBlot.tagName = 'span';
MyBlot.className = 'myclass';

Inline.order.push(MyBlot.blotName);

It would of course have been nicer to have an official API for this rather than hacking an internal variable, but I can’t see a more robust way for this.

How ordering is implemented

If you just wanted the bottom line, there’s no point reading further in this post. What follows is the partial explanation to how I reached the conclusion above. For this section, I’ll stick with Quill’s blots/inline.js unless said otherwise.

First, this is the compare() utility function:

  static compare(self, other) {
    let selfIndex = Inline.order.indexOf(self);
    let otherIndex = Inline.order.indexOf(other);
    if (selfIndex >= 0 || otherIndex >= 0) {
      return selfIndex - otherIndex;
    } else if (self === other) {
      return 0;
    } else if (self < other) {
      return -1;
    } else {
      return 1;
    }
  }

It returns a negative number if its first argument’s name appears before the second in Inline.order and vice versa. That’s the main thing about it. Since indexOf() returns -1 if the string isn’t found, a name not found is considered as if it was before the first element in the array.

And now to Inline’s formatAt():

  formatAt(index, length, name, value) {
    if (Inline.compare(this.statics.blotName, name) < 0 && Parchment.query(name, Parchment.Scope.BLOT)) {
      let blot = this.isolate(index, length);
      if (value) {
        blot.wrap(name, value);
      }
    } else {
      super.formatAt(index, length, name, value);
    }
  }

Before getting into the details, I’ll explain this briefly: The call to compare() checks the position of the desired blot name (the format to add) vs. the name of the current blot (the one of the object that the method is called with). If the current blot appears before in Inline.order, it’s shred into pieces if necessary, and the piece that corresponds to desired segment (index, length) is pushed down as the child of a new blot that is created for the formatting.

An additional condition for this to happen is that the name of the formatting corresponds to a blot class (this is the Parchment.query() part).

Otherwise, the current blot remains intact, and formatAt() call is applied to all its children. This is the super.formatAt() part.

So now the details. It’s a long journey.

The super.formatAt() part is easier to explain. It falls on the method defined in the ContainerBlot class (see parchment/src/blot/abstract/container.ts):

  formatAt(index: number, length: number, name: string, value: any): void {
    this.children.forEachAt(index, length, function(child, offset, length) {
      child.formatAt(offset, length, name, value);
    });

forEachAt() (and similar methods) is implemented in parchment/src/collection/linked-list.ts. As its name implies, it calls a function on all blots within a range (index, length) with proper index and length for each call.

As for the shredding part with isolate() and wrap(): I’m going into these in detail below, but I’ll give the spoiler already:

  • isolate() returns a blot that consists of the segment given by index and length, relative to the blot it’s called on. If that blots needs to be chopped up into siblings (including chopping up the subtree), so be it.
  • wrap() creates a new blot based upon the name and value argument, and pushes the object on which it was called as the new blot’s child. Which is the equivalent of wrapping the HTML segment with the new blot’s tags.

The isolate() method

isolate() is defined in parchment/src/blot/abstract/shadow.ts:

  isolate(index: number, length: number): Blot {
    let target = this.split(index);
    target.split(length);
    return target;
  }

This method quite simply chops up the blot into pieces as necessary to obtain a blot that covers exactly the desired segment, as required by the index and length arguments.

To get an idea how this work, consider the split() method for plain text blots, as defined in parchment/src/blot/text.ts:

  split(index: number, force: boolean = false): Blot {
    if (!force) {
      if (index === 0) return this;
      if (index === this.length()) return this.next;
    }
    let after = Registry.create(this.domNode.splitText(index));
    this.parent.insertBefore(after, this.next);
    this.text = this.statics.value(this.domNode);
    return after;
  }

This method divides the blot into two at the index (relative to the blots beginning, of course) and returns the second (new) blot. And it does nothing in particular if the split point is between blots (index at the beginning or after segment).

This snippet concisely shows how a text node is split with the DOM API’s splitText, and how the new blot node is created and inserted, but that’s a different story.

When the blot for splitting is a Bold, Italic or some other Inline class, ContainerBlot’s split() method does the work instead (see parchment/src/blot/abstract/container.ts):

  split(index: number, force: boolean = false): Blot {
    if (!force) {
      if (index === 0) return this;
      if (index === this.length()) return this.next;
    }
    let after = <ContainerBlot>this.clone();
    this.parent.insertBefore(after, this.next);
    this.children.forEachAt(index, this.length(), function(child, offset, length) {
      child = child.split(offset, force);
      after.appendChild(child);
    });
    return after;
  }

So as one would expect, this method clones the blot in question, and then calls the split() method on all children that are in the range from the split point (i.e. @index) to the end of the what the blot covers. Effectively, this split() call changes only the first child in the list. The second command in the loop moves the child to the cloned blot object. So all in all, this clones the blot for which the method is called, and divides the child blots as appropriate, including splitting a child blot as necessary.

Due to the recursive nature of this method, child blots are split further down as necessary. As one would expect.

The wrap() method

So first a word about class hierarchy: FormatBlot extends ContainerBlot, which extends ShadowBlot.

The wrap() in FormatBlot (see parchment/src/blot/abstract/format.ts) reads:

  wrap(name: string | Parent, value?: any): Parent {
    let wrapper = super.wrap(name, value);
    if (wrapper instanceof FormatBlot && wrapper.statics.scope === this.statics.scope) {
      this.attributes.move(wrapper);
    }
    return wrapper;
  }

so there’s nothing interesting here: Aside from doing things with attributes, it just calls super.wrap(). None is defined in ContainerBlot, so that leaves us with ShadowBlot (parchment/src/blot/abstract/shadow.ts):

  wrap(name: string | Parent, value?: any): Parent {
    let wrapper = typeof name === 'string' ? <Parent>Registry.create(name, value) : name;
    if (this.parent != null) {
      this.parent.insertBefore(wrapper, this.next);
    }
    wrapper.appendChild(this);
    return wrapper;
  }

So pretty much as mentioned above: A new blot object is created with the name and value given, and inserted in place of the object for which the method was called (with insertBefore) and then the latter object becomes the child of the new blot object.

formatAt() for non-ContainerBlot descendants

This isn’t related related, but not all classes are derived from ContainerBlot, which catches formatAt() and applies it to all children. So what happens otherwise?

The generic formatAt() method (as well as several other manipulation methods) is defined in parchment/src/blot/abstract/shadow.ts:

  formatAt(index: number, length: number, name: string, value: any): void {
    let blot = this.isolate(index, length);
    if (Registry.query(name, Registry.Scope.BLOT) != null && value) {
      blot.wrap(name, value);
    } else if (Registry.query(name, Registry.Scope.ATTRIBUTE) != null) {
      let parent = <Parent & Formattable>Registry.create(this.statics.scope);
      blot.wrap(parent);
      parent.format(name, value);
    }
  }

So when the name corresponds to a blot class (as opposed to an attribute), formatAt() calls isolate() on the current object, and then calls wrap() on the object that isolate() returned. Just like the shredding option in Inline’s formatAt(). Actually, it was probably Inline’s formatAt() method that was copied from here, but never mind that.

And if you’re as far as this, it’s probably a good idea to start over to remind yourself what this post is about.

Pasting into a Quill editor: Making the text take formatting as usually expected

Everything in this post relates to Quill v1.3.7. I don’t do web tech for a living, and my knowledge on Quill is merely based upon reading its sources. Besides, I eventually picked another editor for my own use.

Introduction

One of the odd things with Quill is that pasting into the editor window retains the exact formatting, rather than mixing the formats. In other words, if you paste format-less text (from some plain text editor, for example) in the middle of text of italics, the pasted text will become an island of text without italics.

This behavior is counterintuitive, and goes against what the browser’s native editor does. It becomes even more annoying when pasting text in the middle of text that is a link, because links is a format in Quill. So the text before and after the pasted text retain the link, but the pasted text in the middle becomes without linking.

This behavior is nevertheless in line with how Quill considers the operation of pasting: The insertion of a Delta segment. And since the format in the Delta segment is that of the pasted text only, inserting it means that the surrounding formats are not in effect in the pasted segment. Logical in terms of Quill, completely odd in reality.

Luckily, it’s not difficult to fix this.

How Quill does pasting

Before jumping to the solution, I’d like to explain the mechanism for handling pasting briefly. Upon initilization, the Clipboard class (see modules/clipboard.js) creates a <div> element after the editor window, having the class ql-clipboard, which is invisible by virtue of CSS. The DOM object is stored as its own property @container.

It also binds the browsers “paste” event to its onPaste() method during its initialization, as follows:

  onPaste(e) {
    if (e.defaultPrevented || !this.quill.isEnabled()) return;
    let range = this.quill.getSelection();
    let delta = new Delta().retain(range.index);
    let scrollTop = this.quill.scrollingContainer.scrollTop;
    this.container.focus();
    this.quill.selection.update(Quill.sources.SILENT);
    setTimeout(() => {
      delta = delta.concat(this.convert()).delete(range.length);
      this.quill.updateContents(delta, Quill.sources.USER);
      // range.length contributes to delta.length()
      this.quill.setSelection(delta.length() - range.length, Quill.sources.SILENT);
      this.quill.scrollingContainer.scrollTop = scrollTop;
      this.quill.focus();
    }, 1);
  }

So when called, this method gives the dedicated clipboard element focus, causing the pasted material to go there. It then queues a callback for execution 1 ms after its invocation. The callback creates a delta representation of the pasted content by calling its own convert() method, which traverses the DOM of the @container, returning the Delta ops that would have generated it (the traverse() method handles this operation).

This Delta representation is concatenated with the “retain” operation to skip the part up to the pasted position, and a “delete” to remove the part that was selected when the pasting occurred. That results in a Delta representation on the fix to be made in order to implement the paste operation. With that result, the API function updateContents() is called in order to carry it out.

But since the pasting was redirected to inside a dedicated container, and not to where the cursor stood, the Delta representation surely can’t include the formatting that was in effect at the position it’s applied into. And with Delta as in Delta, if a formatting isn’t explicitly listed in the attributes, it’s off. Meaning, that if the Delta “insert” is applied where that formatting was previously on, and it doesn’t appear in the insert’s attributes, it should be turned off. So that’s how that annoying formatting island is created.

How updateContents() does formatting

updateContents() calls the Editor’s class’ applyDelta() (see core/editor.js), which loops on the Delta object’s op array elements. For each element, the Delta op’s diff function (see quill-delta/lib/op.js) is called to compare the attributes that go along with the “insert” op, with those that are in effect where the op is about to be applied. A local variable @attributes contains the result: Its keys are the keys of the attributes that are different (and hence need an update). If the attribute is present in the current context, and not in the op, the value of the key is null.

And then comes the punchline:

      Object.keys(attributes).forEach((name) => {
        this.scroll.formatAt(index, length, name, attributes[name]);
      });

so this is where the formatting of the relevant text segment is set up. Including nullifying the format attributes that are absent in the insert op.

The fix

Given the presentation of the problem, the fix is quite straightforward: Modify applyDelta() so it doesn’t make formatAt() calls that remove formats, if it runs on behalf of a paste operation. In that case, only make the calls that add formats.

So first, the Clipboard’s onPaste() class is modified to begin like this:

  onPaste(e) {
[ ... ]
    setTimeout(() => {
      delta = delta.concat(this.convert()).delete(range.length);
      if (delta.ops && delta.ops[0])
        delta.ops[0].joinformats = 1;
      this.quill.updateContents(delta, Quill.sources.USER);
[ ... ]
    }, 1);
  }

So an additional key is added to the first op in the Delta, in order to hint that it’s a result of a Paste. The first op is used rather than setting delta.joinformats, because the Delta is copy-created along the foodchain, so this property wouldn’t survive.

And then, in the Editor class, update applyDelta() so it starts with:

  applyDelta(delta) {
    let joinformats = delta.ops && delta.ops[0] && delta.ops[0].joinformats;
    let consumeNextNewline = false;
[ ... ]

and then the part mentioned above to

      Object.keys(attributes).forEach((name) => {
        if (attributes[name] || !joinformats)
          this.scroll.formatAt(index, length, name, attributes[name]);
      });

which prevents the removal of formats that aren’t in the Delta op’s attributes, if @joinformats is set. Naturally, this shouldn’t affect all Delta applications, or formats would remain forever.

But what about updating the Delta?

After I finished this little hack, I slapped my forehead with “OK, nice, you’ve just fixed the visual representation, but it’s worth nothing as the Delta isn’t updated”. In other words, the fix above got the blots and hence DOM correctly, but if the Delta isn’t synchronized with this, it will turn out wrong next time the document is loaded.

This would indeed have been a problem had the Delta been updated by somehow joining the existing Delta with the Delta to apply. Luckily, this is not the way it’s done. So as it turned out, I actually got it right.

That’s because applyDelta() ends with

return this.update(delta);

which effectively calls editor.update(). This method, when called without arguments, updates the editor’s stored Delta with:

this.delta = this.getDelta();

and getDelta(), surprisingly enough, rebuilds the Delta afresh from the content of the scroll:

  getDelta() {
    return this.scroll.lines().reduce((delta, line) => {
      return delta.concat(line.delta());
    }, new Delta());
  }

This isn’t as wasteful as it sounds, because some blot elements cache their Delta representation. But the bottom line is that because the Delta is deduced from the blot, that little fix above updates the Delta correctly as well. All well that ends well.

Quill, why not, and rich text editors in general: Getting started notes

Introduction

These are some notes I made while selecting a browser-based rich text editor for my own personal use. Internet and web tech is not my expertise, so I had to catch up some stuff, just to make educated decisions.

I’ll reiterate: I take notes as I work, so this explains why there are several posts about a tool I eventually opted out.

As the title implies, I chose Quill in the beginning, and gave it up after a month. As I had fun getting my hands dirty with JavaScript (for a change, in my case) I was fine with the time spent to learn Quill’s internals (I’ve written several other posts on that), but after three weeks I felt I understood what’s going on, and a week after that I realized any change is going to be difficult regardless.  Looking at how much progress I had achieved (that is, none) I also realized how far I was from finishing, should I remain with Quill. So that was a moment to ignore sunk costs, and pick something else (TinyMCE). More on this below.

Having considered a few editors out there, it seems like they all want to appear to be flexible, modular and customizable. Unfortunately, the only way to tell whether an editor is really flexible is to try to change something that is beyond where the buttons are and what they look like. So it’s requires quite some efforts to reach the point where one can tell if the choice of editor was correct.

Regardless, there’s a rather amusing thing about how many editors present their browser compatibility: It often says “supports latest versions of X, Y ,Z”. Do that convince anyone out there? Is it obvious to everyone that it’s pointless to support the latest browsers? It’s the oldest browsers that any random user out there may have that one need to support.

Editing rich text in general

The old school method for edit regions is by virtue of something like:

<textarea name="content" id="content" class="mceEditor" rows="3" cols="15" tabindex="2"></textarea>

However for rich text, the common trick is to set the contenteditable attribute to an HTML element, hence making its content editable by the browser itself with something like

<div contenteditable="true">This is rich text editable</div>

This sets the isContentEditable property for that element, and also opens for calls to execCommand() for making changes in the text (italics, bold etc.). But even as is, copy-pasting formatted text ends up formatted, and that can be fetched as the innerHTML property. Or the DOM can be traveled down by the inspecting script. This is how common rich editors implement the control buttons for requesting different type faces.

As the text is edited, the DOM tree of that element is updated.

There are however drawbacks with this method. The most commonly mentioned is that different browsers generate different HTML (i.e. a different DOM) in response to user edits. For example, a simple newline can result in the insertion of a <br>, a <p> or a <div>. Different browsers do different things.

But what’s even worse, is that the editing possibilities are limited to what the browser considers reasonable formatting. The fact that the underlying data structure for storing the edited text is the DOM, makes it significantly more difficult to inject information that isn’t DOM related, for example side information that isn’t displayed.

For this reason, there are “block styled editors” which maintain a separate data structure for the text and its edits. The HTML / DOM representation is just for viewing.

Selecting the editor

These are the candidates I looked at:

Block styled editors (don’t rely on the contenteditable element):

  • Quill looked right on the spot, as it has its own data structure for representing text, hence insertion of custom content types (which is exactly what I need) comes naturally. Their git repo looks senseible, and runs back to 2012. It’s apparently the most popular.
  • Trix. For better or for worse, it contains a lot of CoffeeScript.
  • Editor.js. Git repo is sometimes clear, but messy most of the time. Goes back to 2015. Lots of .ts files.
  • Slate. Currently Beta, thought. Basically written in .ts and .tsx. Git repo fairly organized, going back to 2016.
Traditional editors:
  • CKEditor
  • TinyMCE (used by to write this post in WordPress)
  • Draft
  • ProseMirror
  • Redactor

Why I tried Quill

Since I expected a need to add all kinds of unforeseen extra information into the documents, I had the idea that a block styled editor was required. In other words, an editor that keeps the info in some separate data structure.

As far as I could tell, that left me with four candidates: Quill, Slate, Editor.js and Trix.

Another thing is that I intend to keep the edited documents in a git repository, so it’s a bonus if changes play nicely along with plain text diffs. This isn’t all that bad with HTML, but the fact that Quill relies on Delta makes it appear to be better in that respect.

On the other hand, there’s a post written by someone who went from Quill to Slate, but since I don’t expect to write very long pages (which was the main problem presented there) and assuming that the related bug was probably fixed since, it didn’t turn me off Quill. Aside from those specific bugs, that post actually praises Quill.

A complaint regarding Quill is the lack of support for Shift-Enter, for the sake of inserting a <br>. This goes against Quill’s design principles, which is why the author insists on not supporting it. As it turned out, this is just the tip of the iceberg.

Why I went away from Quill

Quill has a very restrictive view on how things should be done. As long as you’re fine with it as is, Quill is great. As long as your customization needs match those envisioned when Quill was designed, it’s a piece of cake. But try something else, and you’re in for bitter fight against the machine. As for developing further, I quite doubt it ever will. It looks like it has reached the point of deadlock where it’s so hacked that every little change is an adventure.

I should also mention that the JavaScript coding style in Quill is exceptionally difficult to read. In particular, there’s a lot of games with the reduce() method and similar tricks to to avoid plain for loops (to keep the code short and concise?), and unless you’re used to those tricks, it’s quite difficult to figure out what the code does. Or with a positive attitude: Quill is a good exercise in advanced JavaScript. Actually, if there’s any reason I’m glad that I spent time learning Quill, it’s the great exercise it was learning JavaScript and how editing works.

The main thing with Quill is that it maintains two extra parallel representations of the edited document, which must be in sync at all times. It’s a nice idea theoretically, however reality brings a lot of corner cases, which haven’t always been solved elegantly. Or can be. So there are all kinds of special-case hacks around to handle special cases. The fact that the editor works appears to rely on a battery of tests that are performed automatically. So the code isn’t stable in the sense that you can make logical changes and expect the logical outcome. Things will break.

Quill is in fact quite radical about its Delta representation of the document. The thought behind the editor is that the document should be stored in Delta format only, and that the browser that displays the content to the end user should load Quill’s JavaScript code, and obtain this Delta representation (in JSON, I guess) for producing the DOM structure. Sticking to the Delta paradigm makes it increasingly difficult to support anything but a simple document structure. That can be seen as an advantage, because documents should be kept simple…? But for people like me, who don’t want the tools to tell me what’s right and what’s wrong, it’s quite a disadvantage.

This paradigm is probably why there’s no official method to obtain the HTML code directly from Quill’s own machinery.

Let’s just mention a few options that won’t necessarily work as expected:

  • Get the editor window’s innerHTML property from the DOM. The problem is that Quill inserts a Cursor blot object into the DOM under certain conditions, which is rubbish when shown to the end user. The best workaround I’ve seen for this is to generate a second instance of a Quill editor, with a hidden <div>, push the Delta there, and obtain its innerHTML. This avoids the Cursor object problem.
  • Generate the HTML with some external tool. Well, that works unless there are some customized blot classes added to the editor. They will appear in the Delta representation as “hey, put a blot of this class here” and the external tool will have no idea what to do with it.

I don’t know how common it is in the web development industry to hack around and ensure that things work by virtue of heavy testing. For someone who just wants an editor for personal use, this is a big no-no.

So if there’s anything I learned from my month of trying to figure out Quill, it’s not to pick a block styled editor, but go for a traditional one. And if the HTML gets messy because of that, fix it manually. As for meta-data in the document, let a post-processing script wipe them away from the HTML, rather than avoiding their production by virtue of special blots.

Actually, after a couple of days adopting TinyMCE instead, I went back to my TODO list, and it turned out that the majority of tasks were about tweaking Quill into doing things that are there out of the box in TinyMCE. So I literally reduced the TODO list by half by migrating to TinyMCE.

Getting started

The confusing question is what to start with. The official suggestion seems to be to include a link to something like https://cdn.quilljs.com/1.0.0/quill.js in the website itself, so the JavaScript is downloaded by all websites from Quill’s servers. Nothing I would consider in any scenario, as my website would become dependent on some server I have no control over.

So what then? Build from the git repo? From the Webpack?

So first, the important note: It’s quite difficult to set up a working environment for building Quill from its git repo. There are a lot of dependencies on different tools, spanning from Ruby, Python, Node.js and whatnot, each with its own set off packages. And apparently, it’s a matter of having just the right version of some of these software elements (not necessarily the latest). So unless you want to dedicate some significant time on developing Quill’s core itself, the git repo’s only use is to see the sources, and not to build anything from them.

Which might be a hint not to try to hack the core code, but rather extend it by virtue of adding modules and such.

I ultimately chose to download quill.tar.gz from the release download page for the release version of v1.3.7. Bonus: It’s compact, and contains a few nice examples (that is, HTML that actually makes an editor).

The HTML examples all rely on quill.min.js (fetched locally). Some also rely on external sources for KaTeX (mathematical typing) and higlight.js (for syntax highlighting). The recommended example is examples/full.html, as it presents an editor with (apparently) all modules released with quill.js appearing in the toolbar.

The quill.min.js (216 kB) is the result of minification of quill.js (440 kB).

Now, it’s possible to obtain the exact same files from the Webpack offered from the site, as I show below. After trying that, I found that all files in the node_modules/quill/dist/ directory (after building, of course), were diff-identical with the files in the release version I had downloaded (which was the last release at that time). A quill.min.js.map (which can help debugging the minified version) was present only in the dist/ directory.

However building the Webpack turned out useful as a quick way to get access to other sources, in particular those for Delta and the Parchment. Which can be obtained separately, but why not get all in one?

Quill’s full repo can be fetched with

$ git clone https://github.com/quilljs/quill.git

Some initial sources to look at (except for my own posts on the matter):

Building the Webpack

Although most likely unnecessary, the Webpack can be cloned from Quickjs’ github page:

$ git clone https://github.com/quilljs/webpack-example.git

There might be a need to go “sudo apt install npm” before going on, which may also install a lot of dependencies (Node.js and a lot of other things). Then simply follow the instructions in the repo’s README.md file:

$ cd webpack-example
$ npm install
$ npm run build

“npm install” runs without root privileges downloads a lot of stuff into .npm (some 33 MB) and then extracts that into node_modules. Took less than 3 minutes, with some warnings about deprecatd packages. OK. The second command took 25 seconds, and it just created dist/bundle.js at the root directory, which is practically useless.

Trying it out

This is a good post on how to generally get started, including adding custom styles.

A simple page with an editor could read:

<!-- Add the theme's stylesheet -->
<link rel="stylesheet" href="quill.snow.css">

<!-- Create the editor container -->
<div id="editor">
  <p>Hello World!</p>
  <p>Some initial <strong>bold</strong> text</p>
  <p><br></p>
</div>

<script src="quill.js"></script>
<script>
var quill = new Quill('#editor', {
  theme: 'snow'   // Specify theme in configuration
});
</script>

Note that two files are mentioned: quill.snow.css and quill.js. Only these two are required for this to work in this specific example.

The files to copy are in node_modules/quill/dist/. Note that there are other files with the same name in other directories (in particular quill.core.js). It’s those in quill/dist that should be used.

Installing Note.js from binaries (the hacky way)

Node.js is required to build several JavaScript packages (Quill, for example) and the version that was available from the repository of my Linux Mint 18.1 was way too old: node v4.2.6 and npm  v3.5.2. The attempt to build the Quill Webpack with those oldies failed miserably.

Truth to be said, there are instructions on how to install Node.js from binaries, but they relate to stash the installation away from the regular binary search part. So I improvised a bit, and hey, it works.

Download the latest binary (i.e. the Linux Binaries (x64) option) from Node.js’ main download page , extract and install. Everything (except the tar command) must be done as root:

$ tar -xvJf node-v16.13.0-linux-x64.tar.xz
# chown -R root:root node-v16.13.0-linux-x64/
# cd node-v16.13.0-linux-x64/
# mv include/node /usr/include/
# mv bin/* /usr/bin/
# mv lib/node_modules/ /usr/lib/
# mv share/man/man1/node.1 /usr/share/man/man1/
# mv share/systemtap/tapset/node.stp /usr/share/systemtap/tapset/

Note that some of the files in bin/ are relative symbolic links to lib/node_modules, so if the target directory outline is different from this, the symbolic links need to be remade.

After this, there should be no significant files to copy, so

$ find . -type f
./CHANGELOG.md
./LICENSE
./README.md

Run Firefox over X11 over SSH / VNC on a cheap virtual machine

To run over SSH: Not

This is how to run a Firefox browser on a cheap VPS machine (e.g. a Google Cloud VM Instance) with an X-server connection. It’s actually not a good idea, because it’s extremely slow. The correct way is to set up a VNC server, because the X server connection exchanges information on every little mouse movement or screen update. It’s a disaster on a slow connection.

My motivation was to download a 10 GB file from Microsoft’s cloud storage. With my own Internet connection it failed consistently after a Gigabyte or so (I guess the connection timed out). So the idea is to have Firefox running on a remote server with a much better connection. And then transfer the file.

Since it’s a one-off task, and I kind-of like these bizarre experiments, here we go.

These steps:

Edit /etc/ssh/sshd_config, making sure it reads

X11Forwarding yes

Install xauth, also necessary to open a remote X:

# apt install xauth

Then restart the ssh server:

# systemctl restart ssh

and then install Firefox

# apt install firefox-esr

There will be a lot of dependencies to install.

At this point, it’s possible to connect to the server with ssh -X and run firefox on the remote machine.

Expect a horribly slow browser, though. Every small animation or mouse movement is transferred on the link, so it definitely gets stuck easily. So think before every single move, and think about every single little thing in the graphics that gets updated.

Firefox “cleverly” announces that “a web page is slowing down your browser” all the time, but the animation of these announcements become part of the problem.

It’s also a good idea to keep the window small, so there isn’t much to area to keep updated. And most important: Keep the mouse pointer off the remote window unless it’s needed there for a click. Otherwise things get stuck. Just gen into the window, click, and leave. Or stay if the click was for the sake of typing (or better, pasting something).

Run over VNC instead

This requires installing an X-Windows server. Not a big deal.

# apt update
# apt-get install xfce4
# apt install x-window-system

once installed, open a VNC window. It’s really easiest by clicking a button on the user’s VPS Client Area (also available on the control panel, but why go that far) and go

# startx

at command prompt to start the server. And then start the browser as usual.

It doesn’t make sense to have a login server as it slows down the boot process and eats memory. Unless a VNC connection is the intended way to always use the virtual machine.

Firefox is still quite slow, but not as bad as with ssh.

 

The eSigner fraud: ssl.com charging my credit card arbitrarily with hundreds of dollars

Background

More than anything, this is a reminder to self why I must use a temporary credit card number when I’ll renew my EV Code Signing certificate I purchased from ssl.com, a few years from writing this (if they’ll still exist by then). I need it for Microsoft’s Attestation signing of drivers for Windows, as detailed on this separate post of mine.

The business of selling certificates to websites have seen better days since Let’s Encrypt began to offer such for free, so in a way I can understand that a company like ssl.com needs to increase its revenues on the higher end of certificates. But it seems like they’ve lost control over the machine that charges money from credit cards. Or maybe they’re struggling for cash with nothing to lose, so it could be that there will be no ssl.com to renew the certificate with. Actually, do credit card companies offer protection from companies that go bankrupt?

The story until things got wrong

Back in May 2021, I purchased a 3-year EV Code Signing certificate from ssl.com, paying 747 USD with my regular credit card. The vetting process went reasonably smooth, and I got the certificate a couple of weeks after issuing the order, which makes sense given the extensive evaluation required.

Along with the congratulation mail from ssl.com, I got an offer to use cloud signing with eSigner.com for free. That’s a web utility, allowing signing a file by dragging it into the browser, and subsequently validating oneself with the mobile phone. It’s indeed more convenient that using the Yubikey USB dongle that is physically sent from ssl.com after purchasing a certificate. So far so good.

Then in July 2021, I got a mail from ssl.com thanking me for participating in public beta of eSigner (I did?) and also asking me to participate in a follow-up survey in exchange for “100 free signatures after the free beta period ends”. And so I did. It was quick and painless.

And then on August 20th 2021, another email thanking me for participating in the eSigner Cloud Signing Beta Project. It also said that “Beginning on September 1, SSL.com will offer eSigner as a paid service available to all Document Signing and EV Code Signing customers. Current Beta participants with low to medium usage will automatically be placed in the Tier 1 group with overage fees waived”.

Frankly speaking, I didn’t read that long. Knowing I had 100 free signatures, I couldn’t care less.

And just to have this clear: There wasn’t a single word in this email about being charged, let alone mentioning a sum.

Who charged me 100 USD?

They didn’t wait long. A couple of weeks after the last email, I saw a 100 USD charge on my credit card by “SSL.COM CLOUD SERVICES HTTPSWWW.SSL”. I wasn’t even sure if this had to do with ssl.com, because the latter used a slightly different name.

Did I agree to this? Of course I didn’t. I didn’t know anything about this until I saw this on my credit card bill. So apparently, they thought it was fine informing me that I was about to join “Tier 1″, and from that I should have figured what that means: A completely ridiculous program, offering 10 eSigner signatures per month, with a monthly price of 100 USD. In other words, pay 100 USD a month for sparing yourself the effort of using the USB dongle. Max 10 times a month.

This is credit card fraud by definition. The only reason I didn’t cancel it through the credit card company was that it requires canceling the credit card altogether. That would mess up recurring payments, so trying to resolve this with sll.com got priority.

No big deal, just click “revoke”

So I dropped them a mail. The response was to read this KB article on how to cancel an eSigner account. I’ll give you the highlight: A click on a link saying “REVOKE”. Given that I had already signed things with this certificate, I wasn’t at all happy clicking on that link. Even though customer support told me this doesn’t revoke the certificate in the usual sense (i.e. invalidates its use retrospectively).

In fact, I would put a beer on that the use of the R-word was made intentionally to scare.

I could also add that the use of the certificate was only for attestation signing, so it was only checked when I submitted the drivers — the drivers themselves were signed by Microsoft, with their signature.

All in all, there should in theory not be any issue even if the certificate was revoked, but I really wasn’t in the mood of pushing my luck on this one.

Besides, given that I happened to have 100 free signings, there’s no justification to ask me to cancel my eSigner account. Don’t get me wrong: It’s not like I’m going to get anywhere close eSigner in the future. I just don’t want to mess things up.

Customer non-support

Another thing the response from ssl.com said was “I have also created a refund request ticket for the billing team to refund the charge. Please stand by for update from the billing team”.

That update failed to arrive. Also, when I pointed out the 100 free signings issue, I got “The refund request is for the 100 dollar charge. If you do not use the 100 signings, you may be subject to another charge next month but the billing team would have to remove the charge. Please let me know if I can be of further assistance”.

A couple of weeks after not getting any update on the refund, I sent a nag mail, and got “This has been escalated to the billing team for investigation. Please stand by for update from the billing team”. And hey, Win from the Billing Department finally responded and told me he would issue a refund and inform me when that was done. And so he did. That is, he informed me about the refund, but I didn’t see it.

And then I was charged again on November 1st, 100 USD again. Why not?

Looking at the billing details for October, it turned out that Win had indeed made a refund: He had effectively canceled the 100 USD charged in October, but not the one in September. So nobody ever stopped the machine charging 100 USD each month. All I got was a refund for the charging in the middle.

All in all, 200 USD nicked from my credit card. And counting.

Bottom line

I mentioned the conclusion above: Always use a temporary credit card for payments abroad, and don’t even trust a company whose core business is trust. In the past, it was possible to cancel a payment made abroad without canceling the credit card, but the rules have changed.

Epilogue

After writing this post, I kept on nagging with a couple of more emails to ssl.com, and somehow the second one caught their attention. Without getting into the details of the email exchange, it was clear that the game had changed. I saw a refund for the remaining 200 USD quite immediately. Plus a credible promise that my credit card won’t be charged again.

So while I still stand behind every word I’ve written above, it more than appears that my specific case was resolved in a good way.

Quartus Pro 19.2: List of QSF parameter names

Due to rather peculiar reasons described in this post, I found myself looking for all QSF parameter names that Quartus recognizes. I ended up searching a binary file in Quartus’ installation directory. So this is by no means an authoritative list, but since I made it, I thought I should post it. Just in case someone else is in the business of guesswork.

So this was done with Quartus Pro 19.2 running Linux. For non-Pro Quartus 17.1, refer to this post.

This is plain text search, so quite clearly not all items appearing here are legal QSF parameters, and neither is it clear if this list is complete. Or otherwise useful, for that matter.

$ strings ./quartus/linux64/libdb_acf.so | perl -ne '/^[A-Z][A-Z0-9_]+\n*$/ && print' | sort -u
  • ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS
  • ACCEPTS_NEGATIVE
  • ACCEPTS_OPEN
  • ACCEPTS_SHORT
  • ACCEPTS_TRACK_VCCIO
  • ACCEPTS_WILDCARDS
  • ACCEPTS_ZERO
  • AC_COUPLING
  • ACEX1K
  • ACF_ASSIGNMENT_USE_STRING_POOL
  • ACF_NOTIFY_ACF_MANAGER_ASSIGNMENTS_CHANGED
  • ACF_STRING_POOL_MASSIVE_DUMP
  • ACF_VARIABLE_TRAIT_TYPE_MAX_TRAIT_TYPE
  • ACF_VARIABLE_TYPE_ACF_ACF_LAST_VARIABLE
  • ACLK_CAT
  • ACLK_RULE_IMSZER_ADOMAIN
  • ACLK_RULE_NO_SZER_ACLK_DOMAIN
  • ACLK_RULE_SZER_BTW_ACLK_DOMAIN
  • ACTION
  • ACTIVE_PARALLEL
  • ACTIVE_SERIAL_CLOCK
  • ACTIVE_SERIAL
  • ACTIVE_SERIAL_X1
  • ACTIVE_SERIAL_X4
  • ADCE_ENABLED
  • ADCE_FULL_BW
  • ADCE_HALF_BW
  • ADCE_HIGH_BW
  • ADCE_HIGH_FREQ_MODE
  • ADCE_LOW_BW
  • ADCE_LOW_FREQ_MODE
  • ADCE_MED_HIGH_BW
  • ADCE_MED_HIGH_MODE
  • ADCE_MED_LOW_BW
  • ADCE_MED_LOW_MODE
  • ADD_DEFAULT_PINS_TO_OUTPUT_VECTOR_FILE
  • ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS
  • ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
  • ADD_TO_SIMULATION_OUTPUT_WAVEFORMS
  • ADVANCED_CLOCK_OPTIMIZATION
  • ADVANCED
  • ADVANCED_PHYSICAL_OPTIMIZATION
  • ADVANCED_PHYSICAL_RETIMING
  • ADVANCED_PHYSICAL_SYNTHESIS
  • ADVANCED_PHYSICAL_SYNTHESIS_REGISTER_PACKING
  • ADVANCED_PRE_PHYSICAL_SYNTHESIS
  • ADV_NETLIST_OPT_ALLOWED
  • ADV_NETLIST_OPT_DONT_TOUCH
  • ADV_NETLIST_OPT_FIT_LE_DUPLICATION
  • ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTHESIS
  • ADV_NETLIST_OPT_FIT_LE_RETIME
  • ADV_NETLIST_OPT_METASTABLE_REGS
  • ADV_NETLIST_OPT_RETIME_CORE_AND_IO
  • ADV_NETLIST_OPT_STRING
  • ADV_NETLIST_OPT_SYNTH_ALLOW_IP_WYS_UNMAPPING
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME_1
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME_2
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME
  • ADV_NETLIST_OPT_SYNTH_REMAP_1
  • ADV_NETLIST_OPT_SYNTH_REMAP_2
  • ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO
  • ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
  • ADV_NETLIST_OPT_TEST
  • AFTER_INIT_DONE
  • AGGREGATE
  • AGGREGATE_REVISION
  • AGGRESSIVE_AREA
  • AGGRESSIVE_COMPILE_TIME___INTERNAL
  • AGGRESSIVE_COMPILE_TIME
  • AGGRESSIVE
  • AGGRESSIVE_POWER
  • AHDL_FILE
  • AHDL_INCLUDE_FILE
  • AHDL_LIMIT_INT_TO_32
  • AHDL_TEXT_DESIGN_OUTPUT_FILE
  • AHDL_USE_LPM_FOR_OPERATORS
  • ALIAS
  • ALL_EDGE
  • ALL_EXCEPT_COMBINATIONAL_LOGIC_ELEMENT_OUTPUTS
  • ALL_NODES
  • ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION
  • ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
  • ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
  • ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
  • ALLOW_CASCADE_GPLL_TO_LVDS_TX
  • ALLOW_CHILD_PARTITIONS
  • ALLOW_DSP_RETIMING
  • ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER
  • ALLOW_MULTIPLE_PERSONAS
  • ALLOW_PARALLEL_TERMINATION
  • ALLOW_POWER_UP_DONT_CARE
  • ALLOW_RAM_RETIMING
  • ALLOW_REGISTER_DUPLICATION
  • ALLOW_REGISTER_MERGING
  • ALLOW_REGISTER_RETIMING
  • ALLOW_ROUTING_TO_PERIPHERY_THROUGH_GLOBAL_NETWORK
  • ALLOW_SERIES_TERMINATION
  • ALLOW_SERIES_WITH_CALIBRATION_TERMINATION
  • ALLOW_SEU_FAULT_INJECTION
  • ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
  • ALLOW_SYNCH_CTRL_USAGE
  • ALLOW_VCCR_VCCT_PER_BANK
  • ALLOW_VCCR_VCCT_PER_SIX_PACK
  • ALLOW_XOR_GATE_USAGE
  • ALL_PATHS
  • ALL_STAGES_ENABLED
  • ALM_REGISTER
  • ALM_REGISTER_PACKING_EFFORT
  • ALTERA_A10_IOPLL_BOOTSTRAP
  • ALTERA_INTERNAL_FIB
  • ALTERA
  • ALWAYS_ALLOW
  • ALWAYS_ENABLE_INPUT_BUFFERS
  • ALWAYS
  • ALWAYS_REGENERATE_IP
  • ALWAYS_REGENERATE_IP_SIM
  • ALWAYS_WRITE_TO_FILE
  • ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS
  • ANALYZE_LATCHES
  • ANALYZE_METASTABILITY
  • APEX20KC
  • APEX20K_CLIQUE_TYPE
  • APEX20K_CONFIG_DEVICE_JTAG_USER_CODE
  • APEX20K_CONFIGURATION_DEVICE
  • APEX20K_CONFIGURATION_SCHEME
  • APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • APEX20K_DEVICE_IO_STANDARD
  • APEX20KE_DEVICE_IO_STANDARD
  • APEX20KE
  • APEX20KF_DEVICE_IO_STANDARD
  • APEX20K_JTAG_USER_CODE
  • APEX20K
  • APEX20K_LOCAL_ROUTING_SOURCE
  • APEX20K_OPTIMIZATION_TECHNIQUE
  • APEX20K_TECHNOLOGY_MAPPER
  • APEX_FITTER_TYPE
  • APEXII_1_8V_HSTL
  • APEX_II_CONFIGURATION_SCHEME
  • APEXII_CONFIGURATION_SCHEME
  • APEXII_DEVICE_IO_STANDARD
  • AREA
  • AREF_VOLT_0
  • AREF_VOLT_0P5
  • AREF_VOLT_0P75
  • AREF_VOLT_1P0
  • ARM_ASM_COMMAND_LINE
  • ARM_CPP_COMMAND_LINE
  • ARM_LINK_COMMAND_LINE
  • ARMSTRONG_CARRY_CHAIN_LENGTH
  • ARMSTRONG_OPTIMIZATION_TECHNIQUE
  • ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE
  • AS_BIDIRECTIONAL
  • ASCII_REPORT_FILE
  • AS_FREQ_100MHZ
  • AS_FREQ_108MHZ
  • AS_FREQ_115MHZ_IOSC
  • AS_FREQ_125MHZ
  • AS_FREQ_133MHZ
  • AS_FREQ_166_6MHZ
  • AS_FREQ_25MHZ_IOSC
  • AS_FREQ_25MHZ
  • AS_FREQ_38MHZ_IOSC
  • AS_FREQ_50MHZ
  • AS_FREQ_58MHZ_IOSC
  • AS_FREQ_71_5MHZ
  • AS_FREQ_77MHZ_IOSC
  • AS_FREQ_80MHZ
  • ASIC_EMULATION_FAST_FLOW
  • ASIC_PROTOTYPING_ADVANCED
  • ASIC_PROTOTYPING_FEATURES
  • ASIC_PROTOTYPING_LATCH_SUPPORT
  • ASIC_PROTOTYPING
  • ASIC_PROTOTYPING_READBACK_WRITEBACK
  • AS_INPUT_TRI_STATED
  • AS_INPUT_TRI_STATED_WITH_BUS_HOLD
  • AS_INPUT_TRI_STATED_WITH_WEAK_PULL_UP
  • ASM_FILE
  • ASM_OPTIONS_FILE_KEYWORD
  • AS_OUTPUT_DRIVING_AN_UNSPECIFIED_SIGNAL
  • AS_OUTPUT_DRIVING_GROUND
  • AS_OUTPUT_DRIVING_VCC
  • ASP_ASM_COMMAND_LINE
  • ASP_CPP_COMMAND_LINE
  • ASP_LINK_COMMAND_LINE
  • ASSEMBLER_ASSIGNMENT
  • ASSG_CAT
  • ASSG_RULE_MISSING_FMAX
  • ASSG_RULE_MISSING_TIMING
  • AS_SIGNALPROBE_OUTPUT
  • ASSIGNMENT_GROUP_ASSIGNMENT
  • ASSIGNMENT_GROUP_EXCEPTION
  • ASSIGNMENT_GROUP
  • ASSIGNMENT_GROUP_MEMBER
  • AS_VREFA
  • AS_VREFB
  • AS_VREF
  • ATSH
  • ATTRACTION_GROUP
  • ATTRACTION_GROUP_SOFT_REGION
  • ATUH
  • ATUSH
  • ATUSL
  • AUATI
  • AUATL
  • AUATUH
  • AUATUSH
  • AUATUS
  • AUTO_C3_M9K_BIT_SKIP
  • AUTO_CARRY_CHAINS
  • AUTO_CARRY
  • AUTO_CASCADE_CHAINS
  • AUTO_CASCADE
  • AUTO_CLOCK_ENABLE_RECOGNITION
  • AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS
  • AUTO_DELAY_CHAINS
  • AUTO_DISCOVER_AND_SORT
  • AUTO_DISCOVERY
  • AUTO_DSP_RECOGNITION
  • AUTO_ENABLE_SMART_COMPILE
  • AUTO_EXPORT_INCREMENTAL_COMPILATION
  • AUTO_EXPORT_VER_COMPATIBLE_DB
  • AUTO_FAST_INPUT_REGISTERS
  • AUTO_FAST_OUTPUT_ENABLE_REGISTERS
  • AUTO_FAST_OUTPUT_REGISTERS
  • AUTO_FIT
  • AUTO_GLOBAL_CLOCK
  • AUTO_GLOBAL_CLOCK_MAX
  • AUTO_GLOBAL_MEM_CTRL
  • AUTO_GLOBAL_MEMORY_CONTROLS
  • AUTO_GLOBAL_OE
  • AUTO_GLOBAL_OE_MAX
  • AUTO_GLOBAL_REG_CTRL
  • AUTO_GLOBAL_REG_CTRL_MAX
  • AUTO_GLOBAL_REGISTER_CONTROLS
  • AUTO_IMPLEMENT_IN_ROM
  • AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE
  • AUTO_INCREMENT_EPROM_JTAG_CODE
  • AUTO_INCREMENT_USER_JTAG_CODE
  • AUTO_INPUT_REGISTER
  • AUTO_INPUT_REGISTERS
  • AUTO_INSERT_SLD_HUB_ENTITY
  • AUTO_INSERT_SLD_INCR_NODE_ENTITY
  • AUTO_INSERT_SLD_NODE_ENTITY
  • AUTO_LCELL_INSERTION
  • AUTO
  • AUTOMATICALLY
  • AUTOMATIC_DANGLING_PORT_TIEOFF
  • AUTOMATIC
  • AUTO_MERGE_PLLS
  • AUTO_MODIFIED_PACKED_REGISTERS
  • AUTONOMOUS_PCIE_HIP
  • AUTO_OPEN_DRAIN
  • AUTO_OPEN_DRAIN_PINS
  • AUTO_OUTPUT_ENABLE_REGISTER
  • AUTO_OUTPUT_REGISTER
  • AUTO_OUTPUT_REGISTERS
  • AUTO_PACKED_REG_CYCLONE
  • AUTO_PACKED_REGISTERS_ARMSTRONG
  • AUTO_PACKED_REGISTERS_CYCLONE
  • AUTO_PACKED_REGISTERS
  • AUTO_PACKED_REGISTERS_MAXII
  • AUTO_PACKED_REGISTERS_MAX
  • AUTO_PACKED_REGISTERS_STRATIXII
  • AUTO_PACKED_REGISTERS_STRATIX
  • AUTO_PACKED_REGISTERS_TSUNAMI
  • AUTO_PARALLEL_EXPANDERS
  • AUTO_PARALLEL_SYNTHESIS
  • AUTO_PERIPH
  • AUTO_PEXP
  • AUTO_QIC_EXPORT
  • AUTO_QXP_PARTITION
  • AUTO_RAM_BLOCK_BALANCING
  • AUTO_RAM_RECOGNITION
  • AUTO_RAM_TO_LCELL_CONVERSION
  • AUTO_RESERVE_CLKUSR_FOR_CALIBRATION
  • AUTO_RESOURCE_SHARING
  • AUTO_RESTART_CONFIGURATION
  • AUTO_RESTART
  • AUTO_ROM
  • AUTO_ROM_RECOGNITION
  • AUTO_SHIFT_REGISTER_RECOGNITION
  • AUTO_SLD_HUB_ENTITY
  • AUTO_TURBO_BIT
  • AUTO_USE_SIMULATION_PDB_NETLIST
  • AVAUA
  • AVAUATA
  • AVAUATI
  • AVAUATUH
  • AVAUATUSH
  • AVAUI
  • AVAUL
  • AVST_CLK_RESERVED
  • AVST_DATA15_0_RESERVED
  • AVST_DATA31_16_RESERVED
  • AVST_VALID_RESERVED
  • AVST_X16
  • AVST_X32
  • AVST_X8
  • AVUH
  • AWAVA
  • AWAVAUA
  • AWAVAUATA
  • AWAVAUATI
  • AWAVAUATL
  • AWAVAUATUH
  • AWAVAUATU
  • AWAVAUATUSH
  • AWAVAUATUS
  • AWAVAUI
  • AWAVAUL
  • AWAVAUM
  • AWAVE
  • AWAVI
  • AWAVL
  • AWAVM
  • BACKUP_BATTERY_RAM
  • BAK_AUTO_EXPORT
  • BAK_EXPORT_DIR
  • BALANCED
  • BASE_CLOCK
  • BASED_ON_CLOCK_SETTINGS
  • BASE
  • BASEO
  • BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
  • BASE_REVISION
  • BASE_REVISION_PROJECT_OUTPUT_DIRECTORY
  • BASIC
  • BDF_FILE
  • BEST
  • BIAS_INT
  • BIAS_VCMDRV
  • BIDIRECTIONAL
  • BINARY_FILE
  • BLACKBOX
  • BLOCK_DESIGN_NAMING
  • BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
  • BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS
  • BLOCK_RAM_TO_MLAB_CELL_CONVERSION
  • BOARD
  • BOARD_MODEL_CUSTOM
  • BOARD_MODEL_EBD_FAR_END
  • BOARD_MODEL_EBD_FILE_NAME
  • BOARD_MODEL_EBD_SIGNAL_NAME
  • BOARD_MODEL_FAR_C
  • BOARD_MODEL_FAR_DIFFERENTIAL_R
  • BOARD_MODEL_FAR_PULLDOWN_R
  • BOARD_MODEL_FAR_PULLUP_R
  • BOARD_MODEL_FAR_SERIES_R
  • BOARD_MODEL_NEAR_C
  • BOARD_MODEL_NEAR_DIFFERENTIAL_R
  • BOARD_MODEL_NEAR_PULLDOWN_R
  • BOARD_MODEL_NEAR_PULLUP_R
  • BOARD_MODEL_NEAR_SERIES_C
  • BOARD_MODEL_NEAR_SERIES_R
  • BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
  • BOARD_MODEL_NEAR_TLINE_LENGTH
  • BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
  • BOARD_MODEL_TERMINATION_V
  • BOARD_MODEL_TLINE_C_PER_LENGTH
  • BOARD_MODEL_TLINE_LENGTH
  • BOARD_MODEL_TLINE_L_PER_LENGTH
  • BOOST_1_STEP
  • BOOST_2_STEP
  • BOOST_3_STEP
  • BOOST_4_STEP
  • BOOST_5_STEP
  • BOOST_6_STEP
  • BOOST_7_STEP
  • BOOST
  • BOOT_SEL_PIN
  • BOTH_EDGES
  • BREAKPOINT_FILE
  • BREAKPOINT
  • BREAKPOINT_LINE_NUMBER
  • BREAKPOINT_STATE
  • BSF_FILE
  • BW_FULL_12P5
  • BW_HALF_6P5
  • BYPASS_ERROR_RELEASE_CLEARS_BEFORE_TRISTATES_1S25
  • BYPASS
  • BYPASS_OFF
  • BYPASS_STAGES_234
  • BYTE_ORDER
  • BYYPASS_STAGES_234
  • C0H9
  • C0M9
  • C3_M9K_BIT_SKIP
  • CALIBRATED
  • CALIBRATED_SSTL
  • CAL_SIM_ACTIVATOR
  • CAP_NAME
  • CARE
  • CARRY_CHAIN_LENGTH_ARMSTRONG
  • CARRY_CHAIN_LENGTH_DALI
  • CARRY_CHAIN_LENGTH_FLEX10K
  • CARRY_CHAIN_LENGTH_FLEX6K
  • CARRY_CHAIN_LENGTH
  • CARRY_CHAIN_LENGTH_TSUNAMI
  • CARRY_CHAIN_LENGTH_YEAGER
  • CARRY_OUT_PINS_LCELL_INSERT
  • CASCADE_CHAIN_LENGTH
  • CASE_SENSITIVE
  • CAT_ASSEMBLER
  • CAT_ASSIGNMENT_GROUP
  • CAT_DESIGN_ASSISTANT
  • CAT_FITTER
  • CAT_INCREMENTAL_COMPILATION
  • CAT_LOCATION_PIN
  • CAT_LOGICLOCK
  • CAT_MAPPER_SYNTHESIS
  • CAT_NETO
  • CAT_PARAMETERS
  • CAT_POWER_ESTIMATION
  • CAT_PROGRAMMER
  • CAT_SIGNALPROBE
  • CAT_SIGNALTAP
  • CAT_SIMULATION
  • CAT_SOFTWARE_BUILDER
  • CAT_TIMEGROUP
  • CAT_TIMING_ANALYSIS
  • CAT_TIMING
  • CB_CLKUSR
  • CB_INTOSC
  • CDF_FILE
  • CDR_BANDWIDTH_PRESET
  • CEI_11100_LR
  • CEI_11100_SR
  • CEI_4976_LR
  • CEI_4976_SR
  • CEI_6375_LR
  • CEI_6375_SR
  • CEI_9950_LR
  • CEI_9950_SR
  • CE_OPTION
  • C_FILE
  • CHAIN_FILE
  • CHECK_AGAINST_TSM_DELAY
  • CHECK_OUTPUTS
  • CHIP
  • CHIP_WIDE_OE
  • CHIP_WIDE_RESET
  • CKN_CK_PAIR
  • CLAMPING_DIODE
  • CLIQUE
  • CLIQUE_TYPE_APEX20K
  • CLIQUE_TYPE_DALI
  • CLIQUE_TYPE_FLEX10K
  • CLIQUE_TYPE_FLEX6K
  • CLIQUE_TYPE
  • CLIQUE_TYPE_MAX7K
  • CLK_CAT
  • CLK_FPLL_VREG_BOOST_1_STEP
  • CLK_FPLL_VREG_BOOST_2_STEP
  • CLK_FPLL_VREG_BOOST_3_STEP
  • CLK_FPLL_VREG_BOOST_4_STEP
  • CLK_FPLL_VREG_BOOST_5_STEP
  • CLK_FPLL_VREG_BOOST_6_STEP
  • CLK_FPLL_VREG_BOOST_7_STEP
  • CLK_FPLL_VREG_NO_VOLTAGE_BOOST
  • CLKLOCKX1_INPUT_FREQ
  • CLK_RULE_ALL
  • CLK_RULE_CLKNET_CLKSPINES
  • CLK_RULE_CLKNET_CLKSPINES_THRESHOLD
  • CLK_RULE_COMB_CLOCK
  • CLK_RULE_GATED_CLK_FANOUT
  • CLK_RULE_GATING_SCHEME
  • CLK_RULE_INPINS_CLKNET
  • CLK_RULE_INV_CLOCK
  • CLK_RULE_MIX_EDGES
  • CLKUSR
  • CLOCK_ANALYSIS_ONLY
  • CLOCK_DIVISOR
  • CLOCK_ENABLE_MULTICYCLE_HOLD
  • CLOCK_ENABLE_MULTICYCLE
  • CLOCK_ENABLE_ROUTING
  • CLOCK_ENABLE_SOURCE_MULTICYCLE_HOLD
  • CLOCK_ENABLE_SOURCE_MULTICYCLE
  • CLOCK_FREQUENCY
  • CLOCK_HOLD_UNCERTAINTY
  • CLOCK
  • CLOCK_MAX_ROUTING
  • CLOCK_REGION
  • CLOCK_SETTINGS
  • CLOCK_SETUP_UNCERTAINTY
  • CLOCK_SOURCE
  • CLOCK_SPINE
  • CLOCK_TO_OUTPUT_DELAY
  • CLOUD_NOTIFY_COMPILE_ID
  • CLOUD_NOTIFY_ENABLE
  • CLOUD_NOTIFY_ENABLE_LOGGING
  • CLOUD_NOTIFY_GROUP_ID
  • CLOUD_NOTIFY_LOGGING
  • CLOUD_NOTIFY_PROXY
  • CLOUD_NOTIFY_SEND_CRIT_WARNINGS
  • CLOUD_NOTIFY_SEND_ERRORS
  • CLOUD_NOTIFY_SEND_JSON_REPORTS
  • CLOUD_NOTIFY_SERVER
  • CLOUD_NOTIFY_TOKEN
  • COMMAND_MACRO_FILE
  • COMMAND_MACRO_MODE
  • COMPANION_REVISION_NAME
  • COMPARED_CLOCK
  • COMPATIBLE_PLACEMENT_AND_ROUTING
  • COMPATIBLE_PLACEMENT
  • COMPILATION_LEVEL
  • COMPILE_NEW_PROJECT
  • COMPILER_ACTION_POINTS
  • COMPILER_ASSIGNMENT
  • COMPILER_CONFIGURED
  • COMPILER_SETTINGS
  • COMPILER_SETTINGS_LIST
  • COMPILER_SIGNATURE_ID
  • COMPRESSION_MODE
  • CONBINATION10
  • CONBINATION11
  • CONBINATION1
  • CONBINATION2
  • CONBINATION3
  • CONBINATION4
  • CONBINATION5
  • CONBINATION6
  • CONBINATION7
  • CONBINATION8
  • CONBINATION9
  • CONFIG_DEVICE_JTAG_USER_CODE_DALI
  • CONFIG_DEVICE_JTAG_USER_CODE_FLEX6K
  • CONFIG_DEVICE_JTAG_USER_CODE
  • CONFIGURATION_CLOCK_DIVISOR
  • CONFIGURATION_CLOCK_FREQUENCY
  • CONFIGURATION_DEVICE_DALI
  • CONFIGURATION_DEVICE_FLEX6K
  • CONFIGURATION_DEVICE
  • CONFIGURATION_PINS
  • CONFIGURATION_SCHEME_DALI
  • CONFIGURATION_SCHEME_FLEX6K
  • CONFIGURATION_SCHEME
  • CONFIGURATION_VCCIO_LEVEL
  • CONNECT_BIDIR_PIN_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_BIDIR_PIN_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_PIN_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_PIN_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_PIN_TO_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_PIN_TO_SLD_NODE_ENTITY_PORT
  • CONNECT_SIGNALPROBE_PIN
  • CONNECT_TO
  • CONNECT_TO_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_TO_SLD_NODE_ENTITY_PORT
  • CONTAINS_FAMILY_SPECIFIC_DATA
  • CONVERT_ALOAD_TO_CLEAR_PRESET
  • CONVERT_PR_WARNINGS_TO_ERRORS
  • COPY_IF_NODE_IS_DUPLICATED
  • COPY_VARIABLE_TYPE_IN_PIN_PLANNER
  • CORE_INITIALIZATION_AND_UPDATE
  • CORE_INITIALIZATION
  • CORE
  • CORE_ONLY_PLACE_REGION
  • CORE_UPDATE
  • COVERAGE_COMPLETE_PANEL_ENABLED
  • COVERAGE
  • COVERAGE_MISSING_0_VALUE_PANEL_ENABLED
  • COVERAGE_MISSING_1_VALUE_PANEL_ENABLED
  • CPH9
  • CPP_FILE
  • CPP_INCLUDE_FILE
  • CPRI_12500
  • CPRI_E12HV
  • CPRI_E12LVIII
  • CPRI_E12LVII
  • CPRI_E12LV
  • CPRI_E24LVIII
  • CPRI_E24LVII
  • CPRI_E24LV
  • CPRI_E30LVIII
  • CPRI_E30LVII
  • CPRI_E30LV
  • CPRI_E48LVIII
  • CPRI_E48LVII
  • CPRI_E60LVIII
  • CPRI_E60LVII
  • CPRI_E6HV
  • CPRI_E6LVIII
  • CPRI_E6LVII
  • CPRI_E6LV
  • CPRI_E96LVIII
  • CPRI_E99LVIII
  • CPRI
  • CRC_ERROR_CHECKING
  • CRC_ERROR_CHECKING_YEAGER
  • CRC_ERROR_OPEN_DRAIN
  • CREATED_BY
  • CREATED_FROM
  • CREATE_PARTITION_BOUNDARY_PORTS
  • CREATE_SIGNALPROBE_PIN
  • CRITICAL_CHAIN_VIEWER
  • CROSS_BOUNDARY_OPTIMIZATIONS
  • CURRENT_STRENGTH
  • CURRENT_STRENGTH_NEW
  • CUSP_FILE
  • CUSTOM_BUILD_COMMAND_LINE
  • CUSTOM_CLOCK_TREE
  • CUT_OFF_CLEAR_AND_PRESET_PATHS
  • CUT_OFF_IO_PIN_FEEDBACK
  • CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS
  • CUT_OFF_READ_DURING_WRITE_PATH
  • CUT_OFF_READ_DURING_WRITE_PATHS
  • CVPCIE_CONFDONE_OPEN_DRAIN
  • CVPCIE_MODE
  • CVP_CONFDONE_OPEN_DRAIN
  • CVP_MODE
  • CVP_REVISION
  • CVWF
  • CYCLONE_CONFIGURATION_DEVICE
  • CYCLONE_CONFIGURATION_SCHEME
  • CYCLONEII_CONFIGURATION_SCHEME
  • CYCLONEIII_CONFIGURATION_DEVICE
  • CYCLONEIII_CONFIGURATION_SCHEME
  • CYCLONEII_M4K_COMPATIBILITY
  • CYCLONEII_OPTIMIZATION_TECHNIQUE
  • CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION
  • CYCLONEII_TERMINATION
  • CYCLONE_OPTIMIZATION_TECHNIQUE
  • D1_DELAY
  • D1_FINE_DELAY
  • D2_DELAY
  • D3_DELAY
  • D4_DELAY
  • D4_FINE_DELAY
  • D5_DELAY
  • D5_FINE_DELAY
  • D5_OCT_DELAY
  • D5_OE_DELAY
  • D6_DELAY
  • D6_FINE_DELAY
  • D6_OCT_DELAY
  • D6_OE_DELAY
  • D6_OE_FINE_DELAY
  • DA_CUSTOM_RULE_FILE
  • DANGEROUS_EXCEPTION_FOR_READ_ONLY_CONTACT_INFRASTRUCTURE_GROUP
  • DATA0_PIN
  • DATA0_RESERVED
  • DATA15_8_RESERVED
  • DATA1_RESERVED
  • DATA31_16_RESERVED
  • DATA7_1_RESERVED
  • DATA7_2_RESERVED
  • DATA7_5_RESERVED
  • DC_COUPLING_EXTERNAL_RESISTOR
  • DC_COUPLING_EXTERNAL_TERMINATION
  • DC_COUPLING_INTERNAL_100_OHMS
  • DC_CURRENT_FOR_ELECTROMIGRATION_CHECK
  • DCLK
  • DCLK_PIN
  • DCLK_RESERVED
  • DDIO_INPUT_REGISTER
  • DDIO_OUTPUT_REGISTER_DISTANCE
  • DDIO_OUTPUT_REGISTER
  • DEBUG_BOUNDARY
  • DEBUG_TRACE
  • DECREASE_INPUT_DELAY_TO_INPUT_REGISTER
  • DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER
  • DEFAULT_DESIGN_ASSISTANT_SETTINGS
  • DEFAULT_DEVICE_OPTIONS
  • DEFAULT_EQUIVALENCE_CHECKER_SETTINGS
  • DEFAULT_HARDCOPY_SETTINGS
  • DEFAULT_HOLD_MULTICYCLE
  • DEFAULT
  • DEFAULT_LOGIC_OPTIONS
  • DEFAULT_NETLIST_VIEWER_SETTINGS
  • DEFAULT_PARAMETERS
  • DEFAULT_SDC_FILE
  • DEFAULT_TIMING_REQUIREMENTS
  • DEFAULT_VALUE
  • DELAY_MATCH_RELATED_CLOCKS
  • DELAY_SETTING_FROM_CORE_TO_CE_INPUT_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_IO_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_OE_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_OUTPUT_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_OUTPUT_REGISTER
  • DELAY_SETTING_FROM_VIO_TO_CORE
  • DELAY_SETTING_TO_CORE_APEX20K
  • DELAY_SETTING_TO_CORE_DALI
  • DELAY_SETTING_TO_CORE_FLEX10K
  • DELAY_SETTING_TO_CORE_FLEX6K
  • DELAY_SETTING_TO_CORE_TO_OUTPUT_REGISTER
  • DELAY_SETTING_TO_CORE_TSUNAMI
  • DELAY_SETTING_TO_CORE_YEAGER
  • DELAY_SETTING_TO_INPUT_REGISTER
  • DELAY_SETTING_TO_OUTPUT_ENABLE
  • DELAY_SETTING_TO_OUTPUT
  • DELAY_SETTING_TO_ZBT
  • DEPENDENCY_FILE
  • DESIGN_ASISTANT_INCLUDE_IP_BLOCKS
  • DESIGN_ASSISTANT_ASSIGNMENT
  • DESIGN_ASSISTANT_INCLUDE_IP_BLOCKS
  • DESIGN_ASSISTANT_MAX_VIOLATIONS_PER_RULE
  • DESIGN_HASH
  • DESIGN_PARTITION
  • DEV_FAMILY_ACEX1K
  • DEV_FAMILY_APEX20KC
  • DEV_FAMILY_APEX20KE
  • DEV_FAMILY_APEX20K
  • DEV_FAMILY_APEXII
  • DEV_FAMILY_ARMSTRONG
  • DEV_FAMILY_ARRIAIIGZ
  • DEV_FAMILY_ARRIAVGZ
  • DEV_FAMILY_ARRIAV
  • DEV_FAMILY_ASC
  • DEV_FAMILY_AURORA
  • DEV_FAMILY_BEDROCK
  • DEV_FAMILY_BS
  • DEV_FAMILY_CUDA
  • DEV_FAMILY_CYCLONE10GX
  • DEV_FAMILY_CYCLONE10LP
  • DEV_FAMILY_CYCLONEII
  • DEV_FAMILY_CYCLONEIVE
  • DEV_FAMILY_CYCLONEV
  • DEV_FAMILY_DALI
  • DEV_FAMILY_EMBEDDED_PROCESSOR
  • DEV_FAMILY_EPC1
  • DEV_FAMILY_EPC2
  • DEV_FAMILY_EXCALIBUR_ARM
  • DEV_FAMILY_FALCONMESA_EMULATOR
  • DEV_FAMILY_FALCONMESA
  • DEV_FAMILY_FLASH_LOGIC
  • DEV_FAMILY_FLEX10KA
  • DEV_FAMILY_FLEX10KB
  • DEV_FAMILY_FLEX10KE
  • DEV_FAMILY_FLEX10K
  • DEV_FAMILY_FLEX6K
  • DEV_FAMILY_FLEX8000
  • DEV_FAMILY_FUSION
  • DEV_FAMILY_HCXIV
  • DEV_FAMILY_HCX
  • DEV_FAMILY_INTEL_CFI
  • DEV_FAMILY_MAX3000A
  • DEV_FAMILY_MAX7000AE
  • DEV_FAMILY_MAX7000A
  • DEV_FAMILY_MAX7000B
  • DEV_FAMILY_MAX7000S
  • DEV_FAMILY_MAX9000
  • DEV_FAMILY_MAXV
  • DEV_FAMILY_NADDER_EMULATOR
  • DEV_FAMILY_NADDER
  • DEV_FAMILY_NIGHTFURY
  • DEV_FAMILY_PGM_DUMMY_FAMILY
  • DEV_FAMILY_PGM_EOL_FAMILY
  • DEV_FAMILY_PIRANHA
  • DEV_FAMILY_SOC_HPS
  • DEV_FAMILY_STINGRAY
  • DEV_FAMILY_STRATIXHC
  • DEV_FAMILY_STRATIXIIGX
  • DEV_FAMILY_STRATIXIIGXLITE
  • DEV_FAMILY_STRATIXV
  • DEV_FAMILY_SYN
  • DEV_FAMILY_TARPON
  • DEV_FAMILY_TGX
  • DEV_FAMILY_TITAN
  • DEV_FAMILY_TORNADO
  • DEV_FAMILY_TSUNAMI
  • DEV_FAMILY_VERMEER
  • DEV_FAMILY_VIRTUAL_JTAG_TAP
  • DEV_FAMILY_YEAGER
  • DEV_FAMILY_ZIPPLEBACK
  • DEVICE_FILTER_PACKAGE
  • DEVICE_FILTER_PIN_COUNT
  • DEVICE_FILTER_SPEED_GRADE
  • DEVICE_FILTER_VOLTAGE
  • DEVICE_INITIALIZATION_CLOCK
  • DEVICE_IO_STANDARD_APEX20KE
  • DEVICE_IO_STANDARD_APEX20KF
  • DEVICE_IO_STANDARD_APEX20K
  • DEVICE_IO_STANDARD_DALI
  • DEVICE_IO_STANDARD_FLEX10K
  • DEVICE_IO_STANDARD_FLEX6K
  • DEVICE_IO_STANDARD
  • DEVICE_IO_STANDARD_MAX7000
  • DEVICE_IO_STANDARD_YEAGER
  • DEVICE
  • DEVICE_MIGRATION_LIST
  • DEVICE_TECHNOLOGY_MIGRATION_LIST
  • DEV_PART_GENERIC
  • DEV_PART_INVALID
  • DEV_PART_MAX
  • DFE_PI_BW_0P5GHZ
  • DFE_PI_BW_10GHZ
  • DFE_PI_BW_2P5GHZ
  • DFE_PI_BW_5GHZ
  • DIFFERENTIAL
  • DIRECT_FORMAT
  • DIRECT
  • DISABLE_CONF_DONE_AND_NSTATUS_ON_EPROM
  • DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE
  • DISABLE_CORE_CLK
  • DISABLE_DA_GX_RULE
  • DISABLE_DA_RULE
  • DISABLED
  • DISABLE_DSP_NEGATE_INFERENCING
  • DISABLE_EMBEDDED_TIMING_CONSTRAINT
  • DISABLE
  • DISABLE_MLAB_RAM_USE
  • DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE
  • DISABLE_OCP_HW_EVAL
  • DISABLE_PLL_COMPENSATION_DELAY_CHANGE_WARNING
  • DISABLE_REGION_HIERARCHY
  • DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
  • DISABLE_REGISTER_POWERUP_INITIALIZATION
  • DISABLE_TRI
  • DISALLOW_GLOBAL_ASSIGNMENT_IN_QIP
  • DIV2
  • DIV4
  • DIVIDE_BASE_CLOCK_BY
  • DIVIDE_BASE_CLOCK_PERIOD_BY
  • DM_PIN
  • DO_COMBINED_ANALYSIS
  • DO_MIN_ANALYSIS
  • DO_MINMAX_ANALYSIS_USING_RISEFALL_DELAYS
  • DO_MIN_TIMING
  • DONE
  • DONT_AUTODISCOVER_CPP_FILES
  • DONT_CARE
  • DONT_CONVERT_TO_USER_FRIENDLY_STRING
  • DONT_COPY_TO_CREATED_COMPANION_REVISION
  • DONT_COPY_TO_NEW_FILE_FORMAT
  • DONT_COPY_TO_NEW_REVISION
  • DONT_MERGE_REGISTER
  • DONT_REUSE_REMOVED_ASSIGNMENT
  • DONT_TOUCH_USER_CELL
  • DO_POST_BUILD_COMMAND_LINE
  • DO_SYSTEM_FMAX
  • DOWN
  • DP_1620
  • DP_2700
  • DP_5400
  • DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1
  • DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_DEEP_MODE_INPUT_EPXA4_10
  • DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_DEEP_MODE_OUTPUT_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_INPUT_EPXA1
  • DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10
  • DPRAM_INPUT_EPXA4_10
  • DPRAM_OTHER_SIGNALS_EPXA4_10
  • DPRAM_OUTPUT_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10
  • DPRAM_WIDE_MODE_INPUT_EPXA4_10
  • DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_WIDE_MODE_OUTPUT_EPXA4_10
  • DPRIO_CHANNEL_NUM
  • DPRIO_CRUCLK_NUM
  • DPRIO_INTERFACE_REG
  • DPRIO_NORMAL_STATUS
  • DPRIO_QUAD_NUM
  • DPRIO_QUAD_PLL_NUM
  • DPRIO_TX_PLL0_REFCLK_NUM
  • DPRIO_TX_PLL1_REFCLK_NUM
  • DPRIO_TX_PLL_NUM
  • DQ_GROUP
  • DQ_PIN
  • DQSB_DQS_PAIR
  • DQS_DELAY
  • DQS_ENABLE_DELAY_CHAIN
  • DQS_FREQUENCY
  • DQS_LOCAL_CLOCK_DELAY_CHAIN
  • DQSOUT_DELAY_CHAIN
  • DQS_SHIFT
  • DQS_SYSTEM_CLOCK
  • DRC_DEADLOCK_STATE_LIMIT
  • DRC_DETAIL_MESSAGE_LIMIT
  • DRC_FANOUT_EXCEEDING
  • DRC_GATED_CLOCK_FEED
  • DRC_MAX_TOP_FANOUT
  • DRC_REPORT_FANOUT_EXCEEDING
  • DRC_REPORT_MAX_TOP_FANOUT
  • DRC_REPORT_TOP_FANOUT
  • DRC_TOP_FANOUT
  • DRC_VIOLATION_MESSAGE_LIMIT
  • DSE_SEND_REPORT_PANEL
  • DSE_SERVER_SEND_REPORTS
  • DSE_SERVER_URL
  • DSE_SYNTH_EXTRA_EFFORT_MODE
  • DSE_WORKER_ID
  • DSM_DFT_OUT
  • DSM_LSB_OUT
  • DSM_MSB_OUT
  • DSP_BLOCK_BALANCING_IMPLEMENTATION
  • DSP_BLOCK_BALANCING
  • DSP_BLOCKS
  • DSPBUILDER_FILE
  • DSP_REGISTER_PACKING
  • DUAL_FAST_REGIONAL_CLOCK
  • DUAL_IMAGES
  • DUAL_PURPOSE_CLOCK_PIN_DELAY
  • DUAL_REGIONAL_CLOCK
  • DUPLICATE_ATOM
  • DUPLICATE_HIERARCHY_DEPTH
  • DUPLICATE_LOGIC_EXTRACTION
  • DUPLICATE_REGISTER_EXTRACTION
  • DUPLICATE_REGISTER
  • DUP_LOGIC_EXTRACTION
  • DUP_REG_EXTRACTION
  • DUTY_CYCLE
  • DYNAMIC_ATOM_CONNECTION
  • DYNAMIC_CTL
  • DYNAMIC_OCT_CONTROL_GROUP
  • EARLY_CLOCK_LATENCY
  • ECO_ALLOW_ROUTING_CHANGES
  • ECO_OPTIMIZE_TIMING
  • ECO_REGENERATE_REPORT
  • ECO_TIMING_DRIVEN_COMPILE
  • EDA_BOARD_BOUNDARY_SCAN_OPERATION
  • EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL
  • EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL
  • EDA_BOARD_DESIGN_SYMBOL_TOOL
  • EDA_BOARD_DESIGN_TIMING_TOOL
  • EDA_BOARD_DESIGN_TOOL
  • EDA_COPY_TO_SNAPSHOT
  • EDA_DATA_FORMAT
  • EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
  • EDA_DESIGN_EXTRA_ALTERA_SIM_LIB
  • EDA_DESIGN_INSTANCE_NAME
  • EDA_ENABLE_GLITCH_FILTERING
  • EDA_ENABLE_IPUTF_MODE
  • EDA_ENABLE_OCV_TIMING_ANALYSIS
  • EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE
  • EDA_EXCALIBUR_SINGLE_SLICE
  • EDA_EXTRA_ELAB_OPTION
  • EDA_FLATTEN_BUSES
  • EDA_FORMAL_VERIFICATION_ALLOW_RETIMING
  • EDA_FORMAL_VERIFICATION_TOOL
  • EDA_FV_HIERARCHY
  • EDA_GENERATE_FUNCTIONAL_NETLIST
  • EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT
  • EDA_GENERATE_POWER_INPUT_FILE
  • EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT
  • EDA_GENERATE_SDF_FOR_POWER
  • EDA_GENERATE_SDF_OUTPUT_FILE
  • EDA_GENERATE_TIMING_CLOSURE_DATA
  • EDA_IBIS_EXTENDED_MODEL_SELECTOR
  • EDA_IBIS_MODEL_SELECTOR
  • EDA_IBIS_MUTUAL_COUPLING
  • EDA_IBIS_SPECIFICATION_VERSION
  • EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION
  • EDA_INPUT_DATA_FORMAT
  • EDA_INPUT_GND
  • EDA_INPUT_GND_NAME
  • EDA_INPUT_VCC
  • EDA_INPUT_VCC_NAME
  • EDA_IPFS_FILE
  • EDA_LAUNCH_CMD_LINE_TOOL
  • EDA_LAUNCH_TOOL
  • EDA_LMF_FILE
  • EDA_MAINTAIN_DESIGN_HIERARCHY
  • EDA_MAP_ILLEGAL_CHARACTERS
  • EDA_MAP_ILLEGAL
  • EDA_NATIVELINK_GENERATE_SCRIPT_ONLY
  • EDA_NATIVELINK_PORTABLE_FILE_PATHS
  • EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT
  • EDA_NATIVELINK_SIMULATION_TEST_BENCH
  • EDA_NETLIST_TYPE
  • EDA_NETLIST_WRITER_OUTPUT_DIR
  • EDA_OCV_CORE_DERATING_FACTOR
  • EDA_OCV_IO_DERATING_FACTOR
  • EDA_OUTPUT_DATA_FORMAT
  • EDA_RESYNTHESIS_TOOL
  • EDA_RTL_SIM_MODE
  • EDA_RTL_SIMULATION_RUN_SCRIPT
  • EDA_RTL_TEST_BENCH_FILE_NAME
  • EDA_RTL_TEST_BENCH_NAME
  • EDA_RTL_TEST_BENCH_RUN_FOR
  • EDA_RUN_TOOL_AUTOMATICALLY
  • EDA_SDC_FILE_NAME
  • EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
  • EDA_SHOW_LMF_MAPPING_MESSAGES
  • EDA_SHOW_LMF_MAPPING_MSGS
  • EDA_SIMULATION_RUN_SCRIPT
  • EDA_SIMULATION_TOOL
  • EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE
  • EDA_SIMULATION_VCD_OUTPUT_TCL_FILE
  • EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME
  • EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
  • EDA_TEST_BENCH_ENABLE_STATUS
  • EDA_TEST_BENCH_ENTITY_MODULE_NAME
  • EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB
  • EDA_TEST_BENCH_FILE
  • EDA_TEST_BENCH_FILE_NAME
  • EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY
  • EDA_TEST_BENCH_MODULE_NAME
  • EDA_TEST_BENCH_NAME
  • EDA_TEST_BENCH_RUN_FOR
  • EDA_TEST_BENCH_RUN_SIM_FOR
  • EDA_TEST_BENCH_SETTINGS
  • EDA_TIME_SCALE
  • EDA_TIMESCALE
  • EDA_TIMING_ANALYSIS_TOOL
  • EDA_TOOL_SETTINGS
  • EDA_TRUNCATE_HPATH
  • EDA_TRUNCATE_LONG_HIERARCHY_PATHS
  • EDA_USE_IBIS_RLC_TYPE
  • EDA_USE_LMF
  • EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY
  • EDA_USE_RISE_FALL_DELAYS
  • EDA_VHDL_ARCH_NAME
  • EDA_VHDL_LIBRARY
  • EDA_WAIT_FOR_GUI_TOOL_COMPLETION
  • EDA_WRITE_CONFIG
  • EDA_WRITE_DEVICE_CONTROL_PORTS
  • EDA_WRITE_NODES_FOR_POWER_ESTIMATION
  • EDA_WRITER_DONT_WRITE_TOP_ENTITY
  • EDIF_FILE
  • ELA_FILE
  • ELEMENT_INDEX
  • ELF_FILE
  • EMBEDDED_PROCESSOR
  • EMIF_SOC_PHYCLK_ADVANCE_MODELING
  • EMPTY
  • EMPTY_PLACE_REGION
  • EMU_REPLICATE_SIGNAL_PER_SECTOR
  • ENABLE_ACCELERATED_INCREMENTAL_COMPILE
  • ENABLE_ADVANCED_IO_DELAY_CHAIN_OPTIMIZATION
  • ENABLE_ADV_SEU_DETECTION
  • ENABLE_ALT2GXB_CONFIGURATION
  • ENABLE_APEX_FITTER_CHOICE
  • ENABLE_ASMI_FOR_FLASH_LOADER
  • ENABLE_ASM_OPTIONS_FILE
  • ENABLE_ATTEMPT_SIMILAR_PLACEMENT
  • ENABLE_AUTONOMOUS_PCIE_HIP
  • ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS
  • ENABLE_BENEFICIAL_SKEW_OPTIMIZATION
  • ENABLE_BOOT_SEL_PIN
  • ENABLE_BUS_HOLD_CIRCUITRY
  • ENABLE_BUS_HOLD
  • ENABLE_CHIP_WIDE_OE
  • ENABLE_CHIP_WIDE_RESET
  • ENABLE_CLOCK_LATENCY
  • ENABLE_COMPACT_REPORT_TABLE
  • ENABLE_CONFIGURATION_PINS
  • ENABLE_CORE_CLK
  • ENABLE_CRC_ERROR_PIN
  • ENABLE_CVPCIE_CONFDONE
  • ENABLE_CVP_CONFDONE
  • ENABLE_DA_RULE
  • ENABLE_DEVICE_WIDE_OE
  • ENABLE_DEVICE_WIDE_RESET
  • ENABLE_DISABLED_STRATIX_LVDS_MODES
  • ENABLED
  • ENABLE_DRC
  • ENABLE_DRC_SETTINGS
  • ENABLE_ED_CRC_CHECK
  • ENABLE_EXTRA_DQ_DELAY
  • ENABLE_FALLBACK_TO_EXTERNAL_FLASH
  • ENABLE_FORMAL_VERIFICATION
  • ENABLE_HOLD_BACK_OFF
  • ENABLE_HOLD_MULTICYCLE
  • ENABLE_HPS_INTERNAL_TIMING
  • ENABLE_INCREMENTAL_DESIGN
  • ENABLE_INCREMENTAL_REUSE
  • ENABLE_INCREMENTAL_SYNTHESIS
  • ENABLE_INIT_DONE_OUTPUT
  • ENABLE_INTERMEDIATE_SNAPSHOTS
  • ENABLE_IP_DEBUG
  • ENABLE_JTAG_BST_SUPPORT
  • ENABLE_JTAG_PIN_SHARING
  • ENABLE_LAB_SHARING_WITH_PARENT_PARTITION
  • ENABLE
  • ENABLE_LLIS
  • ENABLE_LOGIC_ANALYZER_INTERFACE
  • ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
  • ENABLE_LOW_VOLT_MODE_FLEX10K
  • ENABLE_LOW_VOLT_MODE_FLEX6K
  • ENABLE_LOW_VOLT_MODE
  • ENABLE_M512
  • ENABLE_MERCURY_CDR
  • ENABLE_MIXED_PORT_RDW_OLD_DATA_FOR_RAM_WITH_TWO_CLOCKS
  • ENABLE_MULTICYCLE_HOLD
  • ENABLE_MULTICYCLE
  • ENABLE_MULTITAP
  • ENABLE_NCEO_OUTPUT
  • ENABLE_NCE_PIN
  • ENABLE_NCONFIG_FROM_CORE
  • ENABLE_NO_HIPI_INITIALIZATION_FLOW
  • ENABLE_OCT_DONE
  • ENABLE_OCTDONE
  • ENABLE_PHYSICAL_DSP_MERGING
  • ENABLE_PR_PINS
  • ENABLE_PR_POF_ID
  • ENABLE_RAPID_RECOMPILE
  • ENABLE_RECOVERY_REMOVAL_ANALYSIS
  • ENABLE_REDUCED_MEMORY_MODE
  • ENABLE_SIGNALTAP
  • ENABLE_SMART_VOLTAGE_ID
  • ENABLE_SOURCE_MULTICYCLE_HOLD
  • ENABLE_SOURCE_MULTICYCLE
  • ENABLE_SPI_MODE_CHECK
  • ENABLE_SRC_HOLD_MULTICYCLE
  • ENABLE_SRC_MULTICYCLE
  • ENABLE_STATE_MACHINE_INFERENCE
  • ENABLE_STRATIX_II_DPA_DEBUG
  • ENABLE_STRATIXII_DPA_DEBUG
  • ENABLE_STRATIX_II_LVDS_LOOPBACK
  • ENABLE_STRATIXII_LVDS_LOOPBACK
  • ENABLE_STRICT_PRESERVATION
  • ENABLE_SYNCH_INPUT_REGISTER_1S25
  • ENABLE_TRI
  • ENABLE_UNUSED_RX_CLOCK_WORKAROUND
  • ENABLE_VREFA_PIN
  • ENABLE_VREFB_PIN
  • ENCRYPTED_LUTMASK
  • ENCRYPT_PROGRAMMING_BITSTREAM
  • END_TIME
  • ENFORCE_CONFIGURATION_VCCIO
  • EN_SPI_IO_WEAK_PULLUP
  • ENTITY_REBINDING
  • EN_USER_IO_WEAK_PULLUP
  • EPC1
  • EPC2
  • EPROM_JTAG_CODE_APEX20K
  • EPROM_JTAG_CODE_DALI
  • EPROM_JTAG_CODE_FLEX10K
  • EPROM_JTAG_CODE_FLEX6K
  • EPROM_JTAG_CODE
  • EPROM_JTAG_CODE_YEAGER
  • EPROM_USE_CHECKSUM_AS_USERCODE
  • EQ_BW_1
  • EQ_BW_2
  • EQ_BW_3
  • EQ_BW_4
  • EQC_AUTO_BREAK_CONE
  • EQC_AUTO_COMP_LOOP_CUT
  • EQC_AUTO_INVERSION
  • EQC_AUTO_PORTSWAP
  • EQC_AUTO_TERMINATE
  • EQC_BBOX_MERGE
  • EQC_CONSTANT_DFF_DETECTION
  • EQC_DETECT_DONT_CARES
  • EQC_DFF_SS_EMULATION
  • EQC_DUPLICATE_DFF_DETECTION
  • EQC_ENUM_AUTO_BREAK_CONE
  • EQC_ENUM_AUTO_COMP_LOOP_CUT
  • EQC_ENUM_AUTO_INVERSION
  • EQC_ENUM_AUTO_PORTSWAP
  • EQC_ENUM_AUTO_TERMINATE
  • EQC_ENUM_BBOX_MERGE
  • EQC_ENUM_CONSTANT_DFF_DETECTION
  • EQC_ENUM_DETECT_DONT_CARES
  • EQC_ENUM_DFF_SS_EMULATION
  • EQC_ENUM_DUPLICATE_DFF_DETECTION
  • EQC_ENUM_IO_BUFFER_CONVERSION
  • EQC_ENUM_LVDS_MERGE
  • EQC_ENUM_MAC_REGISTER_UNPACK
  • EQC_ENUM_MANUAL_MAP_LIST
  • EQC_ENUM_MAX_BDD_NODES
  • EQC_ENUM_PARAMETER_CHECK
  • EQC_ENUM_POWER_UP_COMPARE
  • EQC_ENUM_RAM_REGISTER_UNPACK
  • EQC_ENUM_RAM_UNMERGING
  • EQC_ENUM_RENAMING_RULES
  • EQC_ENUM_RENAMING_RULES_LIST
  • EQC_ENUM_SET_PARTITION_BB_TO_VCC_GND
  • EQC_ENUM_SHOW_ALL_MAPPED_POINTS
  • EQC_ENUM_STRUCTURE_MATCHING
  • EQC_ENUM_SUB_CONE_REPORT
  • EQC_LVDS_MERGE
  • EQC_MAC_REGISTER_UNPACK
  • EQC_PARAMETER_CHECK
  • EQC_POWER_UP_COMPARE
  • EQC_RAM_REGISTER_UNPACK
  • EQC_RAM_UNMERGING
  • EQC_RENAMING_RULES
  • EQC_RENAMING_RULES_LIST
  • EQC_SET_PARTITION_BB_TO_VCC_GND
  • EQC_SHOW_ALL_MAPPED_POINTS
  • EQC_STRUCTURE_MATCHING
  • EQC_SUB_CONE_REPORT
  • EQUATION_FILE
  • EQUIVALENCE_CHECKER_ASSIGNMENT
  • EQZP_DIS_PEAKING
  • EQZP_EN_PEAKING
  • ERROR_CHECK_FREQUENCY_DIVISOR
  • ESTIMATE_POWER_CONSUMPTION
  • EXCALIBUR_ARM
  • EXCALIBUR_CONFIGURATION_DEVICE
  • EXCALIBUR_CONFIGURATION_SCHEME
  • EXC_BUSTRANS_SIM_FILE
  • EXCLUDE_FMAX_PATHS_GREATER_THAN
  • EXCLUDE_SLACK_PATHS_GREATER_THAN
  • EXCLUDE_TCO_PATHS_LESS_THAN
  • EXCLUDE_TH_PATHS_LESS_THAN
  • EXCLUDE_TPD_PATHS_LESS_THAN
  • EXCLUDE_TSU_PATHS_LESS_THAN
  • EXCLUSIVE_IO_GROUP
  • EXI9
  • EXPANDED
  • EXPORT_BLOCK_NAME_OBFUSCATION
  • EXPORT_PARTITION_SNAPSHOT_FINAL
  • EXPORT_PARTITION_SNAPSHOT_SYNTHESIZED
  • EXTENDS_TOP_BLOCK
  • EXTERNAL_FEEDBACK
  • EXTERNAL_FLASH_FALLBACK_ADDRESS
  • EXTERNAL_INPUT_DELAY
  • EXTERNAL
  • EXTERNAL_LVDS_RX_USES_DPA
  • EXTERNAL_OUTPUT_DELAY
  • EXTERNAL_PIN_CONNECTION
  • EXTERNAL_RESISTOR
  • EXTRACT_AND_OPTIMIZE_BUS_MUXES
  • EXTRACT_VERILOG_STATE_MACHINES
  • EXTRACT_VHDL_STATE_MACHINES
  • EXTRA_EFFORT
  • EYEQ_BW_1G_TO_2P5G
  • EYEQ_BW_2P5G_TO_7P5G
  • EYEQ_BW_GREATER_THAN_7P5G
  • EYEQ_BW_LESS_THAN_1G
  • F10K_ACEX1K_PCI_LOW_CAP
  • FALLBACK_TO_EXTERNAL_FLASH
  • FALL
  • FALSE
  • FAMILY
  • FANIN_PER_CELL_MAX7000
  • FAP_NAME
  • FAR_END
  • FAR_GLOBAL_CLOCK
  • FAR_REGIONAL_CLOCK
  • FAST_FIT_COMPILATION
  • FAST_FIT
  • FAST_INPUT_REGISTER
  • FAST_IO
  • FAST
  • FAST_OCT_REGISTER
  • FAST_OPENCL_COMPILE
  • FAST_OUTPUT_ENABLE_REGISTER
  • FAST_OUTPUT_REGISTER
  • FAST_PASSIVE_PARALLEL
  • FAST_POR_DELAY
  • FAST_PRESERVE
  • FAST_REGIONAL_CLOCK
  • FASTROW_INTERCONNECT
  • FAST_VIO
  • FBCLK_COUNTER_OUT
  • FFFFFFFF
  • FFFF
  • FILES
  • FILTER_PACKAGE
  • FILTER_PIN_COUNT
  • FILTER_SPEED_GRADE
  • FILTER_VOLTAGE
  • FINAL_PLACEMENT_OPTIMIZATION
  • FIR_POST_1T_NEG
  • FIR_POST_1T_POS
  • FIR_POST_2T_NEG
  • FIR_POST_2T_POS
  • FIR_PRE_1T_NEG
  • FIR_PRE_1T_POS
  • FIR_PRE_2T_NEG
  • FIR_PRE_2T_POS
  • FIT_ATTEMPTS_TO_SKIP
  • FIT_FAST_FORWARD
  • FIT_FINALIZE
  • FIT_INI_VARS
  • FIT_ONLY_ONE_ATTEMPT
  • FIT_PLACE
  • FIT_PLAN
  • FIT_ROUTE
  • FIT_SCRIPT_FILE
  • FIT_SEED
  • FIT_SMART_IO
  • FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND
  • FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION
  • FITTER_ASSIGNMENT
  • FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN
  • FITTER_EARLY_RETIMING
  • FITTER_EARLY_TIMING_ESTIMATE_MODE
  • FITTER_EFFORT
  • FITTER_OPTIMIZED
  • FITTER_PACK_AGGRESSIVE_ROUTABILITY
  • FITTER_PLL_SCAN_CHAIN_RECONFIG_FILE
  • FITTER_RESYNTHESIS
  • FITTER_TCL_CALLBACK_FILE
  • FITTER_TYPE
  • FITTER_WILDARDS
  • FITTER_WILDCARDS
  • FIT_WYSIWYG_PIA
  • FLASH_NCE_RESERVED
  • FLASH_PROGRAMMING_FILE_NAME
  • FLEX10KA
  • FLEX10KB
  • FLEX10K_CARRY_CHAIN_LENGTH
  • FLEX10K_CLIQUE_TYPE
  • FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE
  • FLEX10K_CONFIGURATION_DEVICE
  • FLEX10K_CONFIGURATION_SCHEME
  • FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • FLEX10K_DEVICE_IO_STANDARD
  • FLEX10KE
  • FLEX10K_ENABLE_LOCK_OUTPUT
  • FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
  • FLEX10KE_PCI_LOW_CAP_ADJUST
  • FLEX10K_JTAG_USER_CODE
  • FLEX10K
  • FLEX10K_MAX_PERIPHERAL_OE
  • FLEX10K_OPTIMIZATION_TECHNIQUE
  • FLEX10K_TECHNOLOGY_MAPPER
  • FLEX6000
  • FLEX6K_CARRY_CHAIN_LENGTH
  • FLEX6K_CLIQUE_TYPE
  • FLEX6K_CONFIG_DEVICE_JTAG_USER_CODE
  • FLEX6K_CONFIGURATION_DEVICE
  • FLEX6K_CONFIGURATION_SCHEME
  • FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • FLEX6K_DEVICE_IO_STANDARD
  • FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
  • FLEX6K_JTAG_USER_CODE
  • FLEX6K_LOCAL_ROUTING_DESTINATION
  • FLEX6K_LOCAL_ROUTING_SOURCE
  • FLEX6K_OPTIMIZATION_TECHNIQUE
  • FLEX6K_TECHNOLOGY_MAPPER
  • FLEX8000
  • FLEXIBLE_TIMING
  • FLOATING
  • FLOATING_REGION
  • FLOW_DISABLE_ASSEMBLER
  • FLOW_ENABLE_DESIGN_ASSISTANT
  • FLOW_ENABLE_EARLY_PLACE
  • FLOW_ENABLE_HC_COMPARE
  • FLOW_ENABLE_HCII_COMPARE
  • FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD
  • FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS
  • FLOW_ENABLE_PARALLEL_MODULES
  • FLOW_ENABLE_POWER_ANALYZER
  • FLOW_ENABLE_RTL_VIEWER
  • FLOW_ENABLE_TIMEQUEST_AFTER_EARLY_PLACE_STAGE
  • FLOW_ENABLE_TIMEQUEST_AFTER_PLAN_STAGE
  • FLOW_ENABLE_TIMING_ANALYZER_AFTER_EARLY_PLACE_STAGE
  • FLOW_ENABLE_TIMING_ANALYZER_AFTER_PLAN_STAGE
  • FLOW_ENABLE_TIMING_CONSTRAINT_CHECK
  • FLOW_HARDCOPY_DESIGN_READINESS_CHECK
  • FMAX_REQUIREMENT
  • FOCUS_ENTITY_NAME
  • FORCE_ALL_TILES_WITH_FAILING_TIMING_PATHS_TO_HIGH_SPEED
  • FORCE_ALL_USED_TILES_TO_HIGH_SPEED
  • FORCE_CONFIGURATION_VCCIO
  • FORCED_IF_ASYNCHRONOUS
  • FORCED
  • FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS
  • FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION
  • FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER
  • FORCE_HYPER_REGISTER_FOR_PERIPHERY_CORE_TRANSFER
  • FORCE_HYPER_REGISTER_FOR_UIB_ESRAM_CORE_REGISTER
  • FORCE_MERGE_PLL_FANOUTS
  • FORCE_MERGE_PLL
  • FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION
  • FORCE_POINT_TO_POINT
  • FORCE_RECOMPILE
  • FORCE_SLACK
  • FORCE_SSMCLK_TO_ISMCLK
  • FORCE_SYNCH_CLEAR
  • FORM_DDR_CLUSTERING_CLIQUE
  • FPLL
  • FPLL_VREG1_BOOST_1_STEP
  • FPLL_VREG1_BOOST_2_STEP
  • FPLL_VREG1_BOOST_3_STEP
  • FPLL_VREG1_BOOST_4_STEP
  • FPLL_VREG1_BOOST_5_STEP
  • FPLL_VREG1_BOOST_6_STEP
  • FPLL_VREG1_BOOST_7_STEP
  • FPLL_VREG1_NO_VOLTAGE_BOOST
  • FPLL_VREG_BOOST_1_STEP
  • FPLL_VREG_BOOST_2_STEP
  • FPLL_VREG_BOOST_3_STEP
  • FPLL_VREG_BOOST_4_STEP
  • FPLL_VREG_BOOST_5_STEP
  • FPLL_VREG_BOOST_6_STEP
  • FPLL_VREG_BOOST_7_STEP
  • FPLL_VREG_NO_VOLTAGE_BOOST
  • FRACTAL_SYNTHESIS
  • FREQ_100MHZ
  • FREQ_12_5MHZ
  • FREQ_20MHZ
  • FREQ_25MHZ
  • FREQ_40MHZ
  • FREQ_50MHZ
  • FSDA_LEVEL_AUTO
  • FSDA_LEVEL_C1
  • FSDA_LEVEL_C2
  • FSDA_LEVEL_U
  • FSM_CAT
  • FSM_RULE_DEADLOCK_STATE
  • FSM_RULE_NO_RESET_STATE
  • FSM_RULE_NO_SZER_ACLK_DOMAIN
  • FSM_RULE_UNREACHABLE_STATE
  • FSM_RULE_UNUSED_TRANSITION
  • FSYN_AND_ICP_REGTEST_MODE
  • FULL_BW
  • FULL_COMPILATION
  • FULL_INCREMENTAL_COMPILATION
  • FULL_INCREMENTAL_DESIGN
  • FULL
  • FULL_VPACK
  • FULL_VPR
  • FUNCTIONAL
  • FV_BLACKBOX
  • GBE_1250
  • GDF_FILE
  • GEN3_OFF
  • GEN3_ON
  • GEN4_OFF
  • GEN4_ON
  • GENERAL_POOL
  • GENERATE_CONFIG_HEXOUT_FILE
  • GENERATE_CONFIG_ISC_FILE
  • GENERATE_CONFIG_JAM_FILE
  • GENERATE_CONFIG_JBC_FILE_COMPRESSED
  • GENERATE_CONFIG_JBC_FILE
  • GENERATE_CONFIG_SVF_FILE
  • GENERATE_GXB_RECONFIG_MIF
  • GENERATE_GXB_RECONFIG_MIF_WITH_PLL
  • GENERATE_HEX_FILE
  • GENERATE_ISC_FILE
  • GENERATE_JAM_FILE
  • GENERATE_JBC_FILE_COMPRESSED
  • GENERATE_JBC_FILE
  • GENERATE_PMSF_FILES
  • GENERATE_PR_RBF_FILE
  • GENERATE_RBF_FILE
  • GENERATE_SVF_FILE
  • GENERATE_TTF_FILE
  • GENERATION_DIRECTORY
  • GENERIC_TRAIT
  • GIGE
  • GIVE_ERROR
  • GIVE_INFO
  • GIVE_WARNING
  • GLITCH_DETECTION
  • GLITCH_DETECTION_PULSE
  • GLITCH_INTERVAL
  • GLOBAL_CLOCK
  • GLOBAL
  • GLOBAL_PLACEMENT_EFFORT
  • GLOBAL_SIGNAL_CLKCTRL_LOCATION
  • GLOBAL_SIGNAL
  • GLOBAL_SKEW_BALANCED
  • GNDIO_CURRENT_1PT8V
  • GNDIO_CURRENT_2PT5V
  • GNDIO_CURRENT_GTL
  • GNDIO_CURRENT_GTL_PLUS
  • GNDIO_CURRENT_LVCMOS
  • GNDIO_CURRENT_LVTTL
  • GNDIO_CURRENT_PCI
  • GNDIO_CURRENT_SSTL2_CLASS1
  • GNDIO_CURRENT_SSTL2_CLASS2
  • GNDIO_CURRENT_SSTL3_CLASS1
  • GNDIO_CURRENT_SSTL3_CLASS2
  • GNU_ASM_COMMAND_LINE
  • GNU_CPP_COMMAND_LINE
  • GNU_CSP_ASM_COMMAND_LINE
  • GNU_CSP_CPP_COMMAND_LINE
  • GNU_CSP_LINK_COMMAND_LINE
  • GNU_LINK_COMMAND_LINE
  • GNUPRO_ARM_ASM_COMMAND_LINE
  • GNUPRO_ARM_CPP_COMMAND_LINE
  • GNUPRO_ARM_LINK_COMMAND_LINE
  • GNUPRO_MIPS_ASM_COMMAND_LINE
  • GNUPRO_MIPS_CPP_COMMAND_LINE
  • GNUPRO_MIPS_LINK_COMMAND_LINE
  • GNUPRO_NIOS_ASM_COMMAND_LINE
  • GNUPRO_NIOS_CPP_COMMAND_LINE
  • GNUPRO_NIOS_LINK_COMMAND_LINE
  • GPH9
  • GPLL_TO_LVDS_TX
  • GPON_1244
  • GPON_155
  • GPON_2488
  • GPON_622
  • GRAY
  • GROUNDED
  • GROUP_COMB_LOGIC_IN_CLOUD
  • GROUP_COMB_LOGIC_IN_CLOUD_TMV
  • GROUP_NODES
  • GROUP_NODES_TMV
  • GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME
  • GXB_0PPM_CLOCK_GROUP_DRIVER
  • GXB_0PPM_CLOCK_GROUP
  • GXB_0PPM_CORECLK
  • GXB_0PPM_CORE_CLOCK
  • GXB_CLOCK_GROUP_DRIVER
  • GXB_CLOCK_GROUP
  • GXB_IO_PIN_TERMINATION
  • GXB_RECONFIG_GROUP
  • GXB_RECONFIG_MIF
  • GXB_RECONFIG_MIF_PLL
  • GXB_REFCLK_COUPLING_TERMINATION_SETTING
  • GXB_REFCLK_PIN_TERMINATION
  • GXB_RESERVED_TRANSMIT_CHANNEL
  • GXB_TX_PLL_RECONFIG_GROUP
  • GXB_VCCA_VOLTAGE
  • GXB_VCCR_VCCT_VOLTAGE
  • H9K8
  • HALF_BW
  • HALF
  • HALF_MEGALAB_COLUMN
  • HALF_RESOLUTION
  • HALF_ROW
  • HARD_BLOCK_PARTITION
  • HARDCOPY_DEVICE_IDENTIFIER
  • HARDCOPY_EXTERNAL_CLOCK_JITTER
  • HARDCOPY_FLOW_AUTOMATION
  • HARDCOPYII_COMPANION_REVISION_NAME
  • HARDCOPYII_POWER_ON_EXTRA_DELAY
  • HARDCOPYII_RUN_COMPARISON_ON_EVERY_COMPILE
  • HARDCOPYII_SAVE_MIGRATION_INFO_DURING_COMPILATION
  • HARDCOPY_INDIVIDUAL_SETTINGS
  • HARDCOPY_INPUT_TRANSITION_CLOCK_PIN
  • HARDCOPY_INPUT_TRANSITION_DATA_PIN
  • HARDCOPY_NEW_PROJECT_PATH
  • HARD_POST_FIT
  • HCII_OUTPUT_DIR
  • HC_OUTPUT_DIR
  • HCPY_ALOAD_SIGNALS
  • HCPY_ASYN_RAM
  • HCPY_CAT
  • HCPY_EXCEED_RAM_USAGE
  • HCPY_EXCEED_USER_IO_USAGE
  • HCPY_EXT_CLK_JITTER_CHECK
  • HCPY_EXT_CLK_JITTER_EDGE
  • HCPY_EXT_CLK_JITTER
  • HCPY_ILLEGAL_HC_DEV_PKG
  • HCPY_INPUT_TRANS_CLK_PIN
  • HCPY_INPUT_TRANS_DATA_PIN
  • HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES
  • HCPY_TRANS_CONDITION_CLK_PIN
  • HCPY_TRANS_CONDITION_DATA_PIN
  • HCPY_TRANS_EDGE_CLK_PIN
  • HCPY_TRANS_EDGE_DATA_PIN
  • HCPY_VREF_PINS
  • HDL_INITIAL_FANOUT_LIMIT
  • HDL_INTERFACE_INSTANCE_ENTITY
  • HDL_INTERFACE_INSTANCE_NAME
  • HDL_INTERFACE_INSTANCE_PARAMETERS
  • HDL_INTERFACE_OUTPUT_PATH
  • HDL_MESSAGE_LEVEL
  • HDL_MESSAGE_OFF
  • HDL_MESSAGE_ON
  • HDL_SETTINGS
  • HDL_VERSION
  • HEIGHT
  • HEX_FILE_COUNT_UP_DOWN
  • HEX_FILE_COUNT_UP_OR_DOWN
  • HEX_FILE
  • HEX_FILE_START_ADDRESS
  • HEXOUT_FILE_COUNT_DIRECTION
  • HEXOUT_FILE
  • HEXOUT_FILE_START_ADDRESS
  • HEX_OUTPUT_FILE
  • HIDE_RCF_WARNINGS
  • HIERARCHICAL_COMPILE
  • HIERARCHICAL_PRPOF_ID_CHECK
  • HIERARCHY_BLACKBOX_FILE
  • HIGH_EFFORT
  • HIGH_EFFORT_ROUTE_INI
  • HIGH
  • HIGH_PACKING_ROUTABILITY_EFFORT
  • HIGH_PERF
  • HIGH_PERFORMANCE_EFFORT
  • HIGH_PERFORMANCE_EFFORT_WITH_MAXIMUM_PLACEMENT_EFFORT
  • HIGH_PLACEMENT_ROUTABILITY_EFFORT
  • HIGH_POWER_EFFORT
  • HIGH_ROUTABILITY_EFFORT
  • HIGH_VCM
  • HIGIG_4062
  • HIGIG_5000
  • HIGIG_6250
  • HIGIG_6562
  • HOLD_MULTICYCLE_DEFAULT
  • HOLD_MULTICYCLE
  • HOLD_RELATIONSHIP
  • HPS_AUTO_PARTITION
  • HPS_COLD_RESET_PIN_MODE
  • HPS_DAP_SPLIT_MODE
  • HPS_EARLY_IO_RELEASE
  • HPS_FIRST
  • HPS_INITIALIZATION
  • HPS_IO
  • HPS_ISW_DATA
  • HPS_ISW_EMIF
  • HPS_ISW_FILE
  • HPS_LOCATION
  • HPS_PARTITION
  • HPS_PINS
  • HPS_WARM_RESET_PIN_MODE
  • HSSI_A10_CDR_PLL_ANALOG_MODE
  • HSSI_A10_CDR_PLL_POWER_MODE
  • HSSI_A10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • HSSI_A10_CDR_PLL_UC_RO_CAL
  • HSSI_A10_CMU_FPLL_ANALOG_MODE
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • HSSI_A10_CMU_FPLL_POWER_MODE
  • HSSI_A10_LC_PLL_ANALOG_MODE
  • HSSI_A10_LC_PLL_POWER_MODE
  • HSSI_A10_PM_UC_CLKDIV_SEL
  • HSSI_A10_PM_UC_CLKSEL_CORE
  • HSSI_A10_PM_UC_CLKSEL_OSC
  • HSSI_A10_REFCLK_TERM_TRISTATE
  • HSSI_A10_RX_ADAPT_DFE_CONTROL_SEL
  • HSSI_A10_RX_ADAPT_DFE_SEL
  • HSSI_A10_RX_ADAPT_VGA_SEL
  • HSSI_A10_RX_ADAPT_VREF_SEL
  • HSSI_A10_RX_ADP_CTLE_ACGAIN_4S
  • HSSI_A10_RX_ADP_CTLE_EQZ_1S_SEL
  • HSSI_A10_RX_ADP_DFE_FLTAP_POSITION
  • HSSI_A10_RX_ADP_DFE_FXTAP10
  • HSSI_A10_RX_ADP_DFE_FXTAP10_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP11
  • HSSI_A10_RX_ADP_DFE_FXTAP11_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP1
  • HSSI_A10_RX_ADP_DFE_FXTAP2
  • HSSI_A10_RX_ADP_DFE_FXTAP2_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP3
  • HSSI_A10_RX_ADP_DFE_FXTAP3_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP4
  • HSSI_A10_RX_ADP_DFE_FXTAP4_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP5
  • HSSI_A10_RX_ADP_DFE_FXTAP5_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP6
  • HSSI_A10_RX_ADP_DFE_FXTAP6_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP7
  • HSSI_A10_RX_ADP_DFE_FXTAP7_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP8
  • HSSI_A10_RX_ADP_DFE_FXTAP8_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP9
  • HSSI_A10_RX_ADP_DFE_FXTAP9_SGN
  • HSSI_A10_RX_ADP_LFEQ_FB_SEL
  • HSSI_A10_RX_ADP_ONETIME_DFE
  • HSSI_A10_RX_ADP_VGA_SEL
  • HSSI_A10_RX_ADP_VREF_SEL
  • HSSI_A10_RX_BYPASS_EQZ_STAGES_234
  • HSSI_A10_RX_EQ_BW_SEL
  • HSSI_A10_RX_EQ_DC_GAIN_TRIM
  • HSSI_A10_RX_INPUT_VCM_SEL
  • HSSI_A10_RX_LINK
  • HSSI_A10_RX_OFFSET_CANCELLATION_CTRL
  • HSSI_A10_RX_ONE_STAGE_ENABLE
  • HSSI_A10_RX_POWER_MODE
  • HSSI_A10_RX_QPI_ENABLE
  • HSSI_A10_RX_RX_SEL_BIAS_SOURCE
  • HSSI_A10_RX_SD_OUTPUT_OFF
  • HSSI_A10_RX_SD_OUTPUT_ON
  • HSSI_A10_RX_SD_THRESHOLD
  • HSSI_A10_RX_TERM_SEL
  • HSSI_A10_RX_TERM_TRI_ENABLE
  • HSSI_A10_RX_UC_RX_DFE_CAL
  • HSSI_A10_RX_VCCELA_SUPPLY_VOLTAGE
  • HSSI_A10_RX_VCM_CURRENT_ADD
  • HSSI_A10_RX_VCM_SEL
  • HSSI_A10_RX_XRX_PATH_ANALOG_MODE
  • HSSI_A10_TX_COMPENSATION_EN
  • HSSI_A10_TX_DCD_DETECTION_EN
  • HSSI_A10_TX_DPRIO_CGB_VREG_BOOST
  • HSSI_A10_TX_LINK
  • HSSI_A10_TX_LOW_POWER_EN
  • HSSI_A10_TX_POWER_MODE
  • HSSI_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • HSSI_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • HSSI_A10_TX_RES_CAL_LOCAL
  • HSSI_A10_TX_RX_DET
  • HSSI_A10_TX_RX_DET_OUTPUT_SEL
  • HSSI_A10_TX_RX_DET_PDB
  • HSSI_A10_TX_SLEW_RATE_CTRL
  • HSSI_A10_TX_TERM_CODE
  • HSSI_A10_TX_TERM_SEL
  • HSSI_A10_TX_UC_DCD_CAL
  • HSSI_A10_TX_UC_GEN3
  • HSSI_A10_TX_UC_GEN4
  • HSSI_A10_TX_UC_SKEW_CAL
  • HSSI_A10_TX_UC_TXVOD_CAL_CONT
  • HSSI_A10_TX_UC_TXVOD_CAL
  • HSSI_A10_TX_UC_VCC_SETTING
  • HSSI_A10_TX_USER_FIR_COEFF_CTRL_SEL
  • HSSI_A10_TX_VOD_OUTPUT_SWING_CTRL
  • HSSI_A10_TX_XTX_PATH_ANALOG_MODE
  • HSSI_ADCE_RGEN_MODE
  • HSSI_ANALOG_SETTINGS_PROTOCOL
  • HSSI_C10_CDR_PLL_ANALOG_MODE
  • HSSI_C10_CDR_PLL_POWER_MODE
  • HSSI_C10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • HSSI_C10_CDR_PLL_UC_RO_CAL
  • HSSI_C10_CMU_FPLL_ANALOG_MODE
  • HSSI_C10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • HSSI_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • HSSI_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • HSSI_C10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • HSSI_C10_CMU_FPLL_POWER_MODE
  • HSSI_C10_LC_PLL_ANALOG_MODE
  • HSSI_C10_LC_PLL_POWER_MODE
  • HSSI_C10_PM_UC_CLKDIV_SEL
  • HSSI_C10_PM_UC_CLKSEL_CORE
  • HSSI_C10_PM_UC_CLKSEL_OSC
  • HSSI_C10_REFCLK_TERM_TRISTATE
  • HSSI_C10_RX_ADAPT_DFE_CONTROL_SEL
  • HSSI_C10_RX_ADAPT_DFE_SEL
  • HSSI_C10_RX_ADAPT_VGA_SEL
  • HSSI_C10_RX_ADAPT_VREF_SEL
  • HSSI_C10_RX_ADP_CTLE_ACGAIN_4S
  • HSSI_C10_RX_ADP_CTLE_EQZ_1S_SEL
  • HSSI_C10_RX_ADP_DFE_FLTAP_POSITION
  • HSSI_C10_RX_ADP_DFE_FXTAP10
  • HSSI_C10_RX_ADP_DFE_FXTAP10_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP11
  • HSSI_C10_RX_ADP_DFE_FXTAP11_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP1
  • HSSI_C10_RX_ADP_DFE_FXTAP2
  • HSSI_C10_RX_ADP_DFE_FXTAP2_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP3
  • HSSI_C10_RX_ADP_DFE_FXTAP3_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP4
  • HSSI_C10_RX_ADP_DFE_FXTAP4_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP5
  • HSSI_C10_RX_ADP_DFE_FXTAP5_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP6
  • HSSI_C10_RX_ADP_DFE_FXTAP6_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP7
  • HSSI_C10_RX_ADP_DFE_FXTAP7_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP8
  • HSSI_C10_RX_ADP_DFE_FXTAP8_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP9
  • HSSI_C10_RX_ADP_DFE_FXTAP9_SGN
  • HSSI_C10_RX_ADP_LFEQ_FB_SEL
  • HSSI_C10_RX_ADP_ONETIME_DFE
  • HSSI_C10_RX_ADP_VGA_SEL
  • HSSI_C10_RX_ADP_VREF_SEL
  • HSSI_C10_RX_BYPASS_EQZ_STAGES_234
  • HSSI_C10_RX_EQ_BW_SEL
  • HSSI_C10_RX_EQ_DC_GAIN_TRIM
  • HSSI_C10_RX_INPUT_VCM_SEL
  • HSSI_C10_RX_LINK
  • HSSI_C10_RX_OFFSET_CANCELLATION_CTRL
  • HSSI_C10_RX_ONE_STAGE_ENABLE
  • HSSI_C10_RX_POWER_MODE
  • HSSI_C10_RX_QPI_ENABLE
  • HSSI_C10_RX_RX_SEL_BIAS_SOURCE
  • HSSI_C10_RX_SD_OUTPUT_OFF
  • HSSI_C10_RX_SD_OUTPUT_ON
  • HSSI_C10_RX_SD_THRESHOLD
  • HSSI_C10_RX_TERM_SEL
  • HSSI_C10_RX_TERM_TRI_ENABLE
  • HSSI_C10_RX_UC_RX_DFE_CAL
  • HSSI_C10_RX_VCCELA_SUPPLY_VOLTAGE
  • HSSI_C10_RX_VCM_CURRENT_ADD
  • HSSI_C10_RX_VCM_SEL
  • HSSI_C10_RX_XRX_PATH_ANALOG_MODE
  • HSSI_C10_TX_COMPENSATION_EN
  • HSSI_C10_TX_DCD_DETECTION_EN
  • HSSI_C10_TX_DPRIO_CGB_VREG_BOOST
  • HSSI_C10_TX_LINK
  • HSSI_C10_TX_LOW_POWER_EN
  • HSSI_C10_TX_POWER_MODE
  • HSSI_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • HSSI_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • HSSI_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • HSSI_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • HSSI_C10_TX_RES_CAL_LOCAL
  • HSSI_C10_TX_RX_DET
  • HSSI_C10_TX_RX_DET_OUTPUT_SEL
  • HSSI_C10_TX_RX_DET_PDB
  • HSSI_C10_TX_SLEW_RATE_CTRL
  • HSSI_C10_TX_TERM_CODE
  • HSSI_C10_TX_TERM_SEL
  • HSSI_C10_TX_UC_DCD_CAL
  • HSSI_C10_TX_UC_GEN3
  • HSSI_C10_TX_UC_GEN4
  • HSSI_C10_TX_UC_SKEW_CAL
  • HSSI_C10_TX_UC_TXVOD_CAL_CONT
  • HSSI_C10_TX_UC_TXVOD_CAL
  • HSSI_C10_TX_UC_VCC_SETTING
  • HSSI_C10_TX_USER_FIR_COEFF_CTRL_SEL
  • HSSI_C10_TX_VOD_OUTPUT_SWING_CTRL
  • HSSI_C10_TX_XTX_PATH_ANALOG_MODE
  • HSSI_CLOCK_TOPOLOGY
  • HSSI_FAST_LOCK_MODE
  • HSSI_GT_FORCE_VCO_CONST
  • HSSI_GT_RX_CTLE
  • HSSI_GT_RX_RX_DC_GAIN
  • HSSI_GT_RX_VCM_SEL
  • HSSI_GT_TERMINATION
  • HSSI_GT_TX_COMMON_MODE_DRIVER_SEL
  • HSSI_GT_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_GT_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP
  • HSSI_GT_TX_SIG_INV_PRE_TAP
  • HSSI_GT_TX_VOD_SWITCHING_CTRL_MAIN_TAP
  • HSSI_ODI_EYE_MONITOR_BW_SEL
  • HSSI_PARAMETER
  • HSSI_REFCLK_TERMINATION
  • HSSI_RX_ACGAIN_A
  • HSSI_RX_ACGAIN_V
  • HSSI_RX_ADCE_HSF_HFBW
  • HSSI_RX_ADCE_RGEN_BW
  • HSSI_RX_BYPASS_EQZ_STAGES_234
  • HSSI_RX_CT_EQUALIZER_SETTING
  • HSSI_RX_DFE_PI_BW
  • HSSI_RX_ENABLE_RX_GAINCTRL_PCIEMODE
  • HSSI_RX_EQ_BW_SEL
  • HSSI_RX_INPUT_VCM_SEL
  • HSSI_RX_PDB_SD
  • HSSI_RX_PMOS_GAIN_PEAK
  • HSSI_RX_QPI_ENABLE
  • HSSI_RX_RX_DC_GAIN
  • HSSI_RX_RX_SEL_BIAS_SOURCE
  • HSSI_RX_SD_OFF
  • HSSI_RX_SD_ON
  • HSSI_RX_SD_THRESHOLD
  • HSSI_RX_SEL_HALF_BW
  • HSSI_RX_VCCELA_SUPPLY_VOLTAGE
  • HSSI_RX_VCM_CURRENT_ADD
  • HSSI_RX_VCM_SEL
  • HSSI_S10_REFCLK_TERM_TRISTATE
  • HSSI_TERMINATION
  • HSSI_TX_COMMON_MODE_DRIVER_SEL
  • HSSI_TX_DRIVER_RESOLUTION_CTRL
  • HSSI_TX_FIR_COEFF_CTRL_SEL
  • HSSI_TX_LOCAL_IB_CTL
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP_USER
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_USER
  • HSSI_TX_QPI_EN
  • HSSI_TX_RX_DET
  • HSSI_TX_RX_DET_OUTPUT_SEL
  • HSSI_TX_RX_DET_PDB
  • HSSI_TX_SIG_INV_2ND_TAP
  • HSSI_TX_SIG_INV_PRE_TAP
  • HSSI_TX_SLEW_RATE_CTRL
  • HSSI_TX_SWING_BOOST
  • HSSI_TX_VCM_CTRL_SEL
  • HSSI_TX_VCM_CURRENT_ADDL
  • HSSI_TX_VOD_BOOST
  • HSSI_TX_VOD_SWITCHING_CTRL_MAIN_TAP
  • HSSI_VCCEH_VOLTAGE
  • HSSI_VCCER_VCCET_VOLTAGE
  • HTML_FILE
  • HTML_REPORT_FILE
  • HUB_AUTO_INSERT
  • HUB_ENTITY_NAME
  • HUB_INSTANCE_NAME
  • HUB_SOURCE_FILE
  • HYBRID_FLOW_NEW_EXTRACTOR
  • HYBRID
  • HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS
  • HYPER_AWARE_OPTIMIZE_SHORT_PATHS
  • HYPER_AWARE_OPTIMIZE_TIMING
  • HYPER_AWARE_REGISTER_PLACEMENT
  • HYPER_AWARE_SET_REGISTER_BYPASS
  • HYPER_AWARE_SET_REGISTER_INITIAL_STATE
  • HYPER_EARLY_RETIMER
  • HYPER_REGISTER_DELAY_CHAIN
  • HYPER_REGISTER
  • HYPER_RETIMER_ADD_PIPELINING_GROUP
  • HYPER_RETIMER_ADD_PIPELINING
  • HYPER_RETIMER_ENABLE_ADD_PIPELINING
  • HYPER_RETIMER_FALSE_PATH_RESTRICTION
  • HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING
  • HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX
  • HYPER_RETIMER_FAST_FORWARD_AGGRESSIVE_EXPLORATION
  • HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR
  • HYPER_RETIMER_FAST_FORWARD_CUT_ALL_CLOCK_TRANSFERS
  • HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_ADD_PIPELINING
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_AGGRESSIVE_EXPLORATION
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_ASYNCH_CLEAR
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_USER_PRESERVE_RESTRICTION
  • HYPER_RETIMER_FAST_FORWARD
  • HYPER_RETIMER_FAST_FORWARD_OFF_DESCRIPTION
  • HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS
  • HYPER_RETIMER_FAST_FORWARD_TARGET_MAX_PERFORMANCE
  • HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION
  • HYPER_RETIMER
  • HYPER_RETIMER_REGISTERS_REMOVED
  • IB_22OHM
  • IB_29OHM
  • IB_42OHM
  • IB_49OHM
  • IEEE_10G_BASE_CR_10312
  • IEEE_10G_KR_10312
  • IEEE_40G_BASE_KR_10312
  • IGNORE_CARRY_BUFFERS
  • IGNORE_CARRY
  • IGNORE_CASCADE_BUFFERS
  • IGNORE_CASCADE
  • IGNORE_CLOCK_SETTINGS
  • IGNORE_DUPLICATE_DESIGN_ENTITY
  • IGNORE_GLOBAL_BUFFERS
  • IGNORE_GLOBAL
  • IGNORE_HSSI_COLUMN_POWER_FOR_BTI_MITIGATION
  • IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS
  • IGNORE_LCELL_BUFFERS
  • IGNORE_LCELL
  • IGNORE_LCELL_MAX7000
  • IGNORE_MAX_FANOUT_ASSIGNMENTS
  • IGNORE_MODE_FOR_MERGE
  • IGNORE_PARTITIONS
  • IGNORE_ROW_GLOBAL_BUFFERS
  • IGNORE_ROW_GLOBAL
  • IGNORE_SOFT_BUFFERS
  • IGNORE_SOFT
  • IGNORE_SOFT_MAX7000
  • IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
  • IGNORE_TRANSLATE_OFF
  • IGNORE_VERILOG_INITIAL_CONSTRUCTS
  • IGNORE_VREF_RESTRICTION
  • IMMEDIATE_ASSERTION_FAIL_ACTION
  • IMMEDIATE_ASSERTION_FAIL_MESSAGE
  • IMMEDIATE_ASSERTION
  • IMMEDIATE_ASSERTION_PASS_MESSAGE
  • IMMEDIATE_ASSERTION_STATE
  • IMMEDIATE_ASSERTION_TEST_CONDITION
  • IMPLEMENT_AS_CLOCK_ENABLE
  • IMPLEMENT_AS_LCELL
  • IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL
  • IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE
  • IMPLEMENTS_FREE_RUNNING_CLOCK
  • IMPORT_BASED_POST_FIT
  • IMPORT_BLOCK
  • IMPORTED
  • IMPORT
  • INCLUDED_IN_OLD_CHIP_SECTION
  • INCLUDED_IN_OLD_PROJECT_INFO_SECTION
  • INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
  • INCLUDE_FILE
  • INCLUDE_IN_ALL_TB2
  • INCLUDE_IN_COMPILER_REPORT
  • INCLUDE_IN_FITTER_TB2
  • INCLUDE_IN_POWER_TB2
  • INCLUDE_IN_SIMULATOR_REPORT
  • INCLUDE_IN_SYNTHESIS_REPORT
  • INCLUDE_IN_SYNTHESIS_TB2
  • INCLUDE_IN_TIMING_TB2
  • INCLUDE_PATHS_GREATER_THAN_TCO
  • INCLUDE_PATHS_GREATER_THAN_TH
  • INCLUDE_PATHS_GREATER_THAN_TPD
  • INCLUDE_PATHS_GREATER_THAN_TSU
  • INCLUDE_PATHS_LESS_THAN_FMAX
  • INCLUDE_PATHS_LESS_THAN_SLACK
  • INCLUDE_PIN_DELAYS_IN_CALCULATIONS
  • INC_PLACE_PREF_LOCATION
  • INC_PLC_MODE
  • INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN
  • INCREASE_DELAY_TO_OUTPUT_PIN
  • INCREASE_INPUT_CLOCK_ENABLE_DELAY
  • INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER
  • INCREASE_OUTPUT_CLOCK_ENABLE_DELAY
  • INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY
  • INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAYR
  • INCREASE_TZX_DELAY_TO_OUTPUT_PIN
  • INCREMENTAL_COMPILATION_EXPORT_FILE
  • INCREMENTAL_COMPILATION_EXPORT_FLATTEN
  • INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE
  • INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME
  • INCREMENTAL_COMPILATION_EXPORT_POST_FIT
  • INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH
  • INCREMENTAL_COMPILATION_EXPORT_ROUTING
  • INCREMENTAL_COMPILATION
  • INCREMENTAL_INPUT_VECTOR_FILE
  • INCREMENTAL_SYNTHESIS_FULL
  • INCREMENTAL_SYNTHESIS
  • INCREMENTAL_SYNTHESIS_PARTITION
  • INCREMENTAL_SYNTHESIS_TOP
  • INCREMENTAL_TIME_INPUT
  • INCREMENTAL_VECTOR_INPUT_SOURCE
  • INCR_SIGNALTAP_PARTITION
  • INCR_TAP
  • INDIRECT_PORT_ASSIGNMENT
  • INERTIAL
  • INFER_RAMS_FROM_RAW_LOGIC
  • INIT_CLKUSR
  • INIT_DCLK
  • INIT_DONE_OPEN_DRAIN
  • INIT_DONE_OUTPUT
  • INITIALIZATION_CLOCK
  • INITIAL_PLACEMENT_CONFIGURATION
  • INIT_INTOSC
  • INI_VARS
  • INNER_NUM
  • INPUT_DELAY_CHAIN
  • INPUT_DELAY
  • INPUT_EDGE
  • INPUT
  • INPUT_MAX_DELAY
  • INPUT_MIN_DELAY
  • INPUT_OCT_VALUE
  • INPUT_ONLY
  • INPUT_PERSONA
  • INPUT_REFERENCE
  • INPUT_REGISTER
  • INPUT_TERMINATION
  • INPUT_TRANSITION_TIME
  • INSERT_ADDITIONAL_LOGIC_CELL
  • INSERT_BOUNDARY_WIRE_LUTS
  • INSTANT_ON
  • INTERFACE
  • INTERFACE_ROLE
  • INTERFACES
  • INTERFACE_TYPE
  • INTERLAKEN_11100
  • INTERLAKEN_12500
  • INTERLAKEN_3125
  • INTERLAKEN_6375
  • INTERLAKEN
  • INTERNAL_CONFIGURATION
  • INTERNAL_FLASH_UPDATE_MODE
  • INTERNAL
  • INTERNAL_OSCILLATOR_DIVIDE_DOWN
  • INTERNAL_SCRUBBING
  • INTERNAL_VREF_MODE
  • INVALID_DESIGN_SOURCE
  • INVERT_BASE_CLOCK
  • INVERTED_CLOCK
  • IO_12_LANE_INPUT_DATA_DELAY_CHAIN
  • IO_12_LANE_INPUT_DATA_DELAY
  • IO_12_LANE_INPUT_STROBE_DELAY_CHAIN
  • IO_12_LANE_INPUT_STROBE_DELAY
  • IOBANK
  • IOBANK_VCCIO
  • IO_MAXIMUM_TOGGLE_RATE
  • IO_PARTITION_PLACEMENT
  • IO_PATHS_AND_MINIMUM_TPD_PATHS
  • IO_PLACEMENT_OPTIMIZATION
  • IOPLL
  • IO_SSO_CHECKING
  • IO_STANDARD
  • IP_ADVISOR_FILE
  • IPA_FILE
  • IP_COMPONENT_AUTHOR
  • IP_COMPONENT_DESCRIPTION
  • IP_COMPONENT_DISPLAY_NAME
  • IP_COMPONENT_DOCUMENTATION_LINK
  • IP_COMPONENT_GROUP
  • IP_COMPONENT_INTERNAL
  • IP_COMPONENT_NAME
  • IP_COMPONENT_PARAMETER
  • IP_COMPONENT_REPORT_HIERARCHY
  • IP_COMPONENT_SETTING
  • IP_COMPONENT_VERSION
  • IP_DEBUG_VISIBLE
  • IP_FILE
  • IP_GENERATED_DEVICE_FAMILY
  • IP_QSYS_MODE
  • IP_SEARCH_PATHS
  • IP_SHOW_ANALYSIS_MESSAGES
  • IP_SHOW_ELABORATION_MESSAGES
  • IP_TARGETED_DEVICE_FAMILY
  • IP_TARGETED_PART_TRAIT
  • IP_TOOL_ENV
  • IP_TOOL_HIERARCHY_LEVELS
  • IP_TOOL_NAME
  • IP_TOOL_VENDOR_NAME
  • IP_TOOL_VERSION_CREATED
  • IP_TOOL_VERSION
  • IP_TOP_LEVEL_COMPONENT_NAME
  • IP_TOP_LEVEL_ENTITY_NAME
  • IPX_FILE
  • ISC_FILE
  • IS_DEBUG
  • IS_FREEFORM
  • ISL82XX
  • ISP_CLAMP_STATE_DEFAULT
  • ISP_CLAMP_STATE
  • JAM_FILE
  • JBC_FILE
  • JESD204_A_B_12500
  • JESD204_A_B_6375
  • JOHNSON
  • JTAG_BST_SUPPORT
  • JTAG_BST_SUPPORT_MAX7000
  • JTAG_PIN_SHARING
  • JTAG_USER_CODE_DALI
  • JTAG_USER_CODE_FLEX6K
  • JTAG_USER_CODE
  • K0H9
  • KEEP_LCELL_FOLLOWING_PLL
  • KEEP_LUT_SYN_ONLY
  • KXL9
  • LARGE
  • LARGE_PERIPHERY_CLOCK
  • LAST_QUARTUS_VERSION
  • LATE_CLOCK_LATENCY
  • LCELL_AS_VIO
  • LCELL_INSERTION
  • LCELL_PERIPHERY_ROUTER
  • LEVEL1
  • LEVEL2
  • LEVEL3
  • LIBRARY
  • LIBRARY_SEARCH_ORDER
  • LICENSE_FILE
  • LIMIT_AHDL_INTEGERS_TO_32_BITS
  • LINEAR_FORMAT
  • LL_AUTO_SIZE
  • LL_COLOR
  • LL_CORE_ONLY
  • LL_ENABLED
  • LL_EXCLUDE
  • LL_FSDA_LEVEL
  • LL_FSDA_ROUTING_INTERFACE
  • LL_HEIGHT
  • LL_HORIZONTAL_FLIP
  • LL_IGNORE_IO_BANK_FSDA_CONSTRAINT
  • LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT
  • LL_IGNORE_IO_PIN_FSDA_CONSTRAINT
  • LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT
  • LL_IMPORT_FILE
  • LL_MEMBER_EXCEPTIONS
  • LL_MEMBER_OF_FSDA_ROUTING_INTERFACE
  • LL_MEMBER_OF
  • LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE
  • LL_MEMBER_OPTION
  • LL_MEMBER_RESOURCE_EXCLUDE
  • LL_MEMBER_STATE
  • LL_NODE_LOCATION
  • LL_OLD_BEHAVIOR
  • LL_ORIGIN
  • LL_OUTPUT_SIGNAL_FSDA_LEVEL
  • LL_PARENT
  • LL_PATH_EXCLUDE
  • LL_PATH_INCLUDE
  • LL_PRIORITY
  • LL_PR_REGION
  • LL_RCF_IMPORT_FILE
  • LL_RECT
  • LL_REGION_SECURITY_LEVEL
  • LL_RESERVED_IS_LIMITED
  • LL_RESERVED
  • LL_RESERVED_MEMBERS_OF_IMMEDIATE_PARENT_REGION_HIERARCHY_ONLY
  • LL_RESERVE
  • LL_ROOT_REGION
  • LL_ROUGH
  • LL_ROUTING_REGION_EXPANSION_SIZE
  • LL_ROUTING_REGION
  • LL_SECURITY_ROUTING_INTERFACE
  • LL_SIGNAL_SECURITY_LEVEL
  • LL_SOFT
  • LL_SOURCE_PARTITION_HIERARCHY
  • LL_SOURCE_PARTITION
  • LL_SOURCE_REGION
  • LL_STATE
  • LL_WIDTH
  • LMF_FILE
  • LOCAL
  • LOCAL_LINE_DELAY_CHAIN
  • LOCATION
  • LOCATION_PIN_ASSIGNMENT
  • LOCKED
  • LOGIC_ANALYZER_INTERFACE_FILE
  • LOGIC_ELEMENTS
  • LOGIC
  • LOGICLOCK_ASSIGNMENT
  • LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT
  • LOGICLOCK_INCREMENTAL_COMPILE_FILE
  • LOGICLOCK_REGION
  • LOGIC_MINIMIZATION_SCRIPT
  • LOW_CAP_ADJUST_FLEX10KE
  • LOW_POWER
  • LOW_VCM
  • LTM4677
  • LUTRAM_INSTANCES_FOR_ASIC_PROTOTYPING
  • LVDS_CLOCK_DATA_DESKEW_ADJUST
  • LVDS_DESKEW
  • LVDS_DIRECT_LOOPBACK_MODE
  • LVDS_FIXED_CLOCK_DATA_PHASE
  • LVDS
  • LVDS_RX_REGISTER
  • M10K
  • M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
  • M144K
  • M144K_USE_DCD
  • M20K
  • M512
  • MACRO_HEAD
  • MACRO_MEMBER
  • MACRO_TIMING
  • MAP_FILE
  • MAPPER_SYNTHESIS_ASSIGNMENT
  • MASK
  • MASK_REVISION
  • MATCH_PLL_COMPENSATION_CLOCK
  • MAX10FPGA_CONFIGURATION_SCHEME
  • MAX3000A
  • MAX7000AE
  • MAX7000A
  • MAX7000B
  • MAX7000B_VCCIO_IOBANK1
  • MAX7000B_VCCIO_IOBANK2
  • MAX7000_DEVICE_IO_STANDARD
  • MAX7000_ENABLE_JTAG_BST_SUPPORT
  • MAX7000_FANIN_PER_CELL
  • MAX7000_IGNORE_LCELL_BUFFERS
  • MAX7000_IGNORE_SOFT_BUFFERS
  • MAX7000_INDIVIDUAL_TURBO_BIT
  • MAX7000_JTAG_USER_CODE
  • MAX7000_OPTIMIZATION_TECHNIQUE
  • MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH
  • MAX7000S_JTAG_USER_CODE
  • MAX7000S
  • MAX7000_TECHNOLOGY_MAPPER
  • MAX7000_USE_CHECKSUM_AS_USERCODE
  • MAX7K_CLIQUE_TYPE
  • MAX9000
  • MAX_AUTO_GLOBAL_REGISTER_CONTROLS
  • MAX_BALANCING_DSP_BLOCKS
  • MAX_CLOCK_ARRIVAL_SKEW
  • MAX_CLOCKS_ALLOWED
  • MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION
  • MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION
  • MAX_CORE_JUNCTION_TEMP
  • MAX_CORE_SUPPLY_VOLTAGE
  • MAX_CURRENT_FOR_ELECTROMIGRATION
  • MAX_CURRENT_FOR_VIO_ELECTROMIGRATION
  • MAX_DATA_ARRIVAL_SKEW
  • MAX_DELAY_FOR_CORE_PERIPHERY_TRANSFER
  • MAX_DELAY_FOR_PERIPHERY_CORE_TRANSFER
  • MAX_DELAY
  • MAX_FANOUT
  • MAX_GLOBAL_CLOCKS_ALLOWED
  • MAX_IGNORED_ASGN_MSG
  • MAXII_CARRY_CHAIN_LENGTH
  • MAXII_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • MAXII_OPTIMIZATION_TECHNIQUE
  • MAXIMUM_EFFORT
  • MAXIMUM
  • MAX_LABS
  • MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED
  • MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS
  • MAX_PERIPHERY_CLOCKS_ALLOWED
  • MAXPLUSII
  • MAX_PROCESSORS_USED_FOR_MULTITHREADING
  • MAX_RAM_BLOCKS_M4K
  • MAX_RAM_BLOCKS_M512
  • MAX_RAM_BLOCKS_MRAM
  • MAX_REGIONAL_CLOCKS_ALLOWED
  • MAX_SCC_SIZE
  • MAX_WIRES_FOR_CORE_PERIPHERY_ROUTER
  • MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER
  • MAX_WIRES_FOR_PERIPHERY_CORE_ROUTER
  • MAX_WIRES_FOR_PERIPHERY_CORE_TRANSFER
  • MEDIUM
  • MEGAFUNCTION_GENERATED_TRI
  • MEGALAB_COLUMN
  • MEGALAB
  • MEGARAM
  • MEMBER_OF
  • MEM_INTERFACE_DELAY_CHAIN_CONFIG
  • MEMORY_INTERFACE_DATA_PIN_GROUP
  • MERCURY_CARRY_CHAIN_LENGTH
  • MERCURY_CLIQUE_TYPE
  • MERCURY_CONFIG_DEVICE_JTAG_USER_CODE
  • MERCURY_CONFIGURATION_DEVICE
  • MERCURY_CONFIGURATION_SCHEME
  • MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • MERCURY_DEVICE_IO_STANDARD
  • MERCURY_FITTER_TYPE
  • MERCURY_JTAG_USER_CODE
  • MERCURY_OPTIMIZATION_TECHNIQUE
  • MERCURY_TECHNOLOGY_MAPPER
  • MERGE_EQUIVALENT_BIDIRS
  • MERGE_EQUIVALENT_INPUTS
  • MERGE_HEX_FILE
  • MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR
  • MESSAGE_DISABLE
  • MESSAGE_ENABLE
  • MESSAGE_SUPPRESSION_RULE_FILE
  • MFCU
  • MID_POWER
  • MIF_FILE
  • MIGRATION_ASSIGNMENT
  • MIGRATION_AUTO_PACKED_REGISTERS
  • MIGRATION_AUTO_PORT_SWAP
  • MIGRATION_CONSTRAIN_CORE_RESOURCES
  • MIGRATION_DEVICES
  • MIGRATION_DIFFERENT_SOURCE_FILE
  • MIGRATION_ONLY
  • MIGRATION_PORT_SWAPPING
  • MIGRATION_RAM_INFORMATION
  • MIGRATION_RAM_PACKING_INFORMATION
  • MIGRATION_REGISTER_PACKING
  • MILLIVOLTS
  • MIN_CORE_JUNCTION_TEMP
  • MIN_CORE_SUPPLY_VOLTAGE
  • MIN_DELAY_FOR_CORE_PERIPHERY_TRANSFER
  • MIN_DELAY_FOR_PERIPHERY_CORE_TRANSFER
  • MIN_DELAY
  • MINIMAL_BITS
  • MINIMIZE_AREA
  • MINIMIZE_AREA_WITH_CHAINS
  • MINIMIZE_POWER_ONLY
  • MINIMUM_DELAY_REQUIREMENT
  • MINIMUM
  • MINIMUM_SEU_INTERVAL
  • MINIMUM_TPD_REQUIREMENT
  • MINIMUM_WIDTH_CLOCK_ENABLE
  • MINIMUM_WIDTH_SLOAD_SCLEAR
  • MIN_MTBF_REQUIREMENT
  • MIN_TCO_REQUIREMENT
  • MIN_TPD_REQUIREMENT
  • MINUS_DELTA10
  • MINUS_DELTA11
  • MINUS_DELTA12
  • MINUS_DELTA13
  • MINUS_DELTA14
  • MINUS_DELTA15
  • MINUS_DELTA1
  • MINUS_DELTA2
  • MINUS_DELTA3
  • MINUS_DELTA4
  • MINUS_DELTA5
  • MINUS_DELTA6
  • MINUS_DELTA7
  • MINUS_DELTA8
  • MINUS_DELTA9
  • MIN_WIRES_FOR_CORE_PERIPHERY_TRANSFER
  • MIN_WIRES_FOR_PERIPHERY_CORE_TRANSFER
  • MISC_FILE
  • MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE
  • MLAB
  • MLAB_TIMING_CONSTRAINTS_IN_FEED_THROUGH_DONT_CARE_MODE
  • MODE_0
  • MODE_10
  • MODE_11
  • MODE_12
  • MODE_13
  • MODE_14
  • MODE_15
  • MODE_1
  • MODE_2
  • MODE_3
  • MODE_4
  • MODE_5
  • MODE_6
  • MODE_7
  • MODE_8
  • MODE_9
  • MODE_DEFAULT
  • MODEL_1
  • MODEL_2
  • MODEL_3
  • MODULE_BLOATING_FACTOR
  • MOVE_TO_TOP_IO
  • MP2_EXPORT_FILE
  • MULTICYCLE_HOLD
  • MULTICYCLE
  • MULTIPLY_BASE_CLOCK_BY
  • MULTIPLY_BASE_CLOCK_PERIOD_BY
  • MULTITAP_FILE
  • MUX_RESTRUCTURE
  • MUX_USE_ROUTING_ASSIGNMENT
  • NCEO_OPEN_DRAIN
  • NCEO_RESERVED_CYCLONEII
  • NCEO_RESERVED
  • NCE_PIN
  • NDQS_LOCAL_CLOCK_DELAY_CHAIN
  • NEAR_END
  • NEAR_GLOBAL_CLOCK
  • NEAR_REGIONAL_CLOCK
  • NEGATIVE_180
  • NEGATIVE_90
  • NEGATIVE_EDGE
  • NETLIST_ONLY
  • NETLIST_VIEWER_ASSIGNMENT
  • NETO_ASSIGNMENT
  • NEVER_ALLOW
  • NEVER
  • NEVER_REGENERATE_IP
  • NEVER_REGENERATE_IP_SIM
  • NEW_EXTRACTOR
  • NO_AUTO_INST_DISCOVERY
  • NO_BACK_ANNOTATION
  • NO_BYTE_ENABLE
  • NO_DC_GAIN
  • NO_GLOBAL_ROUTE
  • NOMINAL_CORE_SUPPLY_VOLTAGE
  • NONDEFAULT_LIBS
  • NONE
  • NON_LOCAL
  • NON_QPI_MODE
  • NON_S1_MODE
  • NONSYNCHSTRUCT_CAT
  • NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE
  • NONSYNCHSTRUCT_RULE_COMBLOOP
  • NONSYNCHSTRUCT_RULE_DELAY_CHAIN
  • NONSYNCHSTRUCT_RULE_DLATCH
  • NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN
  • NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED
  • NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR
  • NONSYNCHSTRUCT_RULE_REG_LOOP
  • NONSYNCHSTRUCT_RULE_RIPPLE_CLK
  • NONSYNCHSTRUCT_RULE_SRLATCH
  • NORMAL_COMPILATION
  • NORMAL_LCELL_INSERT
  • NORMAL
  • NO_SDC_PROMOTION
  • NOT_A_CLOCK
  • NOT_BOOST
  • NOT_CLOCK
  • NOT_GATE_PUSH_BACK
  • NO_TO_OPTION_REQUIRED
  • NOT_USED
  • NO_VOLTAGE_BOOST
  • NTFQ_MSG_ACF_ASSIGNMENTS_CHANGED
  • NUMBER_OF_DESTINATION_TO_REPORT
  • NUMBER_OF_EXAMPLE_NODES_REPORTED
  • NUMBER_OF_INVERTED_REGISTERS_REPORTED
  • NUMBER_OF_PATHS_TO_REPORT
  • NUMBER_OF_PROTECTED_REGISTERS_REPORTED
  • NUMBER_OF_REMOVED_REGISTERS_REPORTED
  • NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT
  • NUMBER_OF_SWEPT_NODES_REPORTED
  • NUMBER_OF_SYNTHESIS_MIGRATION_ROWS
  • NUM_PARALLEL_PROCESSORS
  • NWS_NRS_NCS_CS_RESERVED
  • OBJECT_FILE
  • OBSAI_1536
  • OBSAI_3072
  • OBSAI_6144
  • OBSAI_768
  • OBSERVABLE
  • OCP_AUTO_PARTITION
  • OCP_FILE
  • OCP_HW_EVAL
  • OCP_PARTITION
  • OCP_TIMEOUT_PARTITION
  • OCT_100_OHMS
  • OCT_120_OHMS
  • OCT_150_OHMS
  • OCT_AND_IMPEDANCE_MATCHING_CYCLONEII
  • OCT_AND_IMPEDANCE_MATCHING
  • OCT_AND_IMPEDANCE_MATCHING_STRATIXII
  • OCT_CONTROL_BLOCK
  • OCT_REGISTER
  • OE_DELAY_CHAIN
  • OE_DELAY
  • OE_OPTION
  • OFFSET_FROM_BASE_CLOCK
  • OFFSET_MAIN
  • OFFSET_PO1
  • OFFSET_PRE
  • ON_CHIP_BITSTREAM_DECOMPRESSION
  • ONE_HOT
  • OPTIMISTIC
  • OPTIMIZATION_MODE
  • OPTIMIZATION_TECHNIQUE_APEX20K
  • OPTIMIZATION_TECHNIQUE_ARMSTRONG
  • OPTIMIZATION_TECHNIQUE_CYCLONEII
  • OPTIMIZATION_TECHNIQUE_CYCLONE
  • OPTIMIZATION_TECHNIQUE_DALI
  • OPTIMIZATION_TECHNIQUE_FLEX10K
  • OPTIMIZATION_TECHNIQUE_FLEX6K
  • OPTIMIZATION_TECHNIQUE
  • OPTIMIZATION_TECHNIQUE_MAX7000
  • OPTIMIZATION_TECHNIQUE_TSUNAMI
  • OPTIMIZATION_TECHNIQUE_YEAGER
  • OPTIMIZED_EFFORT
  • OPTIMIZE_FAST_CORNER_TIMING
  • OPTIMIZE_FOR_METASTABILITY
  • OPTIMIZE_HOLD_TIMING
  • OPTIMIZE_INTERNAL_TIMING
  • OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING
  • OPTIMIZE_IO_TIMING
  • OPTIMIZE_MULTI_CORNER_TIMING
  • OPTIMIZE_NETLIST_FOR_ROUTABILITY
  • OPTIMIZE_PERSONA_ROUTABILITY
  • OPTIMIZE_POWER_DURING_FITTING
  • OPTIMIZE_POWER_DURING_SYNTHESIS
  • OPTIMIZE_SIGNAL_INTEGRITY
  • OPTIMIZE_SSN
  • OPTIMIZE_TIMING
  • OPTIONS_FOR_ENTITIES_ONLY
  • OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
  • OPTIONS_FOR_NODES_AND_ENTITIES
  • ORIGINAL_INTERFACE_PORT_NAME
  • ORIGINAL_QUARTUS_VERSION
  • ORIGINATING_COMPANION_REVISION
  • OSC_CLK_1_100MHZ
  • OSC_CLK_1_125MHZ
  • OSC_CLK_1_25MHZ
  • OTHER_APF_RESERVED
  • OTHER
  • OTP_AUTO_PARTITION
  • OTP_PARTITION
  • OUTPUT_BUFFER_DELAY_CONTROL
  • OUTPUT_BUFFER_DELAY
  • OUTPUT_DELAY_CHAIN
  • OUTPUT_DELAY
  • OUTPUT_ENABLE_DELAY
  • OUTPUT_ENABLE_GROUP
  • OUTPUT_ENABLE_REGISTER_DUPLICATION
  • OUTPUT_ENABLE_REGISTER
  • OUTPUT_ENABLE_ROUTING
  • OUTPUT_FILE_NAME
  • OUTPUT_IO_TIMING_ENDPOINT
  • OUTPUT_IO_TIMING_FAR_END_VMEAS
  • OUTPUT_IO_TIMING_NEAR_END_VMEAS
  • OUTPUT
  • OUTPUT_MAX_DELAY
  • OUTPUT_MIN_DELAY
  • OUTPUT_OCT_VALUE
  • OUTPUT_PIN_C_FAR
  • OUTPUT_PIN_C_NEAR
  • OUTPUT_PIN_C_PER_LENGTH
  • OUTPUT_PIN_LENGTH
  • OUTPUT_PIN_LOAD
  • OUTPUT_PIN_L_PER_LENGTH
  • OUTPUT_PIN_R_FAR_HIGH
  • OUTPUT_PIN_R_FAR_LOW
  • OUTPUT_PIN_R_FAR_SERIES
  • OUTPUT_PIN_R_NEAR_HIGH
  • OUTPUT_PIN_R_NEAR_LOW
  • OUTPUT_PIN_R_NEAR_SERIES
  • OUTPUT_PIN_V_TERMINATION
  • OUTPUT_REGISTER
  • OUTPUT_TERMINATION
  • OUTPUT_TYPE
  • OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS
  • OWNED_BY_UPPER_PARTITION
  • P0H9
  • P0L9
  • PACKAGE_SKEW_COMPENSATION
  • PACK_ALL_IO_REGISTERS
  • PAD_TO_CORE_DELAY
  • PAD_TO_DDIO_REGISTER_DELAY
  • PAD_TO_INPUT_REGISTER_DELAY
  • PARALLEL_50_OHMS_WITH_CALIBRATION
  • PARALLEL_EXPANDER_CHAIN_LENGTH
  • PARALLEL
  • PARALLEL_SYNTHESIS
  • PARAMETER_ARRAY
  • PARAMETER_BOOL
  • PARAMETER_CHAR
  • PARAMETER_ENUM
  • PARAMETER
  • PARAMETER_PHYSICAL
  • PARAMETER_SIGNED_BIN
  • PARAMETER_SIGNED_DEC
  • PARAMETER_SIGNED_FLOAT
  • PARAMETER_SIGNED_HEX
  • PARAMETER_SIGNED_OCT
  • PARAMETERS
  • PARAMETER_STRING
  • PARAMETER_UNKNOWN
  • PARAMETER_UNSIGNED_BIN
  • PARAMETER_UNSIGNED_DEC
  • PARAMETER_UNSIGNED_FLOAT
  • PARAMETER_UNSIGNED_HEX
  • PARAMETER_UNSIGNED_OCT
  • PARAMETER_UNSIZED_BIT_LITERAL
  • PARTIAL_RECONFIGURATION_PARTITION
  • PARTIAL_SRAM_OBJECT_FILE
  • PARTITION_ALWAYS_USE_QXP_NETLIST
  • PARTITION_ASD_REGION_ID
  • PARTITION_ASD_REGION
  • PARTITION_BACK_ANNOTATION
  • PARTITION_COLOR
  • PARTITION_COLOUR
  • PARTITION_ENABLE_STRICT_PRESERVATION
  • PARTITION_EXTRACT_HARD_BLOCK_NODES
  • PARTITION_FITTER_PRESERVATION_LEVEL
  • PARTITION_HIERARCHY
  • PARTITION_IGNORE_SOURCE_FILE_CHANGES
  • PARTITION_IMPORT_ASSIGNMENTS
  • PARTITION_IMPORT_EXISTING_ASSIGNMENTS
  • PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS
  • PARTITION_IMPORT_FILE
  • PARTITION_IMPORT_NEW_ASSIGNMENTS
  • PARTITION_IMPORT_PIN_ASSIGNMENTS
  • PARTITION_IMPORT_PROMOTE_ASSIGNMENTS
  • PARTITION_LAST_IMPORTED_FILE
  • PARTITION
  • PARTITION_NETLIST_TYPE
  • PARTITION_ONLY
  • PARTITION_PRESERVE_HIGH_SPEED_TILES
  • PARTITION_SOURCE
  • PARTITION_TYPE
  • PASSIVE_PARALLEL_ASYNCHRONOUS
  • PASSIVE_PARALLEL_SYNCHRONOUS
  • PASSIVE_PARALLEL_X16
  • PASSIVE_PARALLEL_X32
  • PASSIVE_PARALLEL_X8
  • PASSIVE_PROGRAMMING_FILE_NAME
  • PASSIVE_RESISTOR
  • PASSIVE_SERIAL_ASYNCHRONOUS
  • PASSIVE_SERIAL
  • PBIP_FILE
  • PCB_LAYERS
  • PCIE_CABLE
  • PCIE_GEN1_3P5DB
  • PCIE_GEN1
  • PCIE_GEN2_3P5DB
  • PCIE_GEN2_6DB
  • PCIE_GEN2
  • PCIE_GEN3
  • PCIE_PRE_EMPH_GEN1
  • PCIE_PRE_EMPH_GEN2_3_5DB_DEEMPH
  • PCIE_PRE_EMPH_GEN2_6DB_DEEMPH
  • PCIE_PRE_EMPH_GEN2_LOW_MARGIN
  • PCIE_PRE_EMPH_GEN2_LOW_SWING
  • PCIE_VOD_GEN1
  • PCIE_VOD_GEN2_3_5DB_DEEMPH
  • PCIE_VOD_GEN2_6DB_DEEMPH
  • PCIE_VOD_GEN2_LOW_MARGIN
  • PCIE_VOD_GEN2_LOW_SWING
  • PCI_IO
  • PDC_FILE
  • PERIPHERAL
  • PERIPHERY_CLOCK
  • PERIPHERY_REUSE_CORE
  • PERIPHERY_SEED
  • PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION
  • PERIPH_FITTER_SCRIPT
  • PERIPH_REPORT_SCRIPT
  • PERSONA_FILE
  • PESSIMISTIC
  • PEXP_LENGTH
  • PEXP_LENGTH_MAX7000
  • PHASE_FROM_BASE_CLOCK
  • PHASE_OF_0_DEGREES
  • PHASE_OF_72_DEGREES
  • PHASE_OF_90_DEGREES
  • PHYSICAL_SHIFT_REGISTER_INFERENCE
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING_DISABLE_DESTINATION_CHECK
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING_REG_REACH
  • PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
  • PHYSICAL_SYNTHESIS_COMBO_LOGIC
  • PHYSICAL_SYNTHESIS_EFFORT
  • PHYSICAL_SYNTHESIS
  • PHYSICAL_SYNTHESIS_LOG_FILE
  • PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA
  • PHYSICAL_SYNTHESIS_PIPELINE
  • PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
  • PHYSICAL_SYNTHESIS_REGISTER_RETIMING
  • PIN_CONNECT_FROM_NODE
  • PIN_FILE
  • PIN_PLANNER_DISPLAY_ASSIGNMENT_VALUE_FROM_POSITIVE_PIN_TO_NEGATIVE_PIN
  • PIN_PLANNER_FILE
  • PIN_PLANNER_GROUP_EXCEPTION
  • PIN_PLANNER_GROUP_MEMBER
  • PIN_PLANNER_GROUP_SETTINGS
  • PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILE
  • PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILES
  • PLACEMENT_AND_ROUTING_AND_TILE
  • PLACEMENT_AND_ROUTING
  • PLACEMENT_EFFORT_MULTIPLIER
  • PLACEMENT
  • PLACE_REGION
  • PLD_TO_STRIPE_INTERRUPTS_EPXA4_10
  • PLL_APLLY_PFD_ISSUE_WORKAROUND
  • PLL_AUTO_RESET
  • PLL_BANDWIDTH_PRESET
  • PLL_C_COUNTER_DELAY_CHAIN
  • PLL_CHANNEL_SPACING
  • PLL_COMPENSATE
  • PLL_COMPENSATION_MODE
  • PLL_DISABLE_COUNTER_SETTINGS_OPTIMIZATION
  • PLL_ENFORCE_USER_PHASE_SHIFT
  • PLL_EXTERNAL_FEEDBACK_BOARD_DELAY
  • PLL_FEEDBACK_CLOCK_SIGNAL
  • PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY
  • PLL_FORCE_OUTPUT_COUNTER
  • PLL_IGNORE_MIGRATION_DEVICES
  • PLL_LOCK_10K
  • PLL_LOCK
  • PLL_LVDS_DELAY_CHAIN
  • PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING
  • PLL_OUTPUT_CLOCK_FREQUENCY
  • PLL_PFD_CLOCK_FREQUENCY
  • PLL_PHASE_RECONFIG_COUNTER_REMAP_LCELL
  • PLL_PRE_C_COUNTER_DELAY_CHAIN
  • PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL
  • PLL_TYPE
  • PLL_VCO_CLOCK_FREQUENCY
  • PLUS_DELTA10
  • PLUS_DELTA11
  • PLUS_DELTA12
  • PLUS_DELTA13
  • PLUS_DELTA14
  • PLUS_DELTA15
  • PLUS_DELTA1
  • PLUS_DELTA2
  • PLUS_DELTA3
  • PLUS_DELTA4
  • PLUS_DELTA5
  • PLUS_DELTA6
  • PLUS_DELTA7
  • PLUS_DELTA8
  • PLUS_DELTA9
  • PMBUS_MASTER
  • PMBUS_SLAVE
  • POF_VERIFY_PROTECT
  • POR_SCHEME
  • POSITIVE_180
  • POSITIVE_90
  • POSITIVE_EDGE
  • POST_BUILD_COMMAND_LINE
  • POST_CONFIG
  • POST_FIT_CONNECT_FROM_SLD_NODE_ENTITY_PORT
  • POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT
  • POST_FIT
  • POST_FIT_WITH_ROUTING
  • POST_FLOW_SCRIPT_FILE
  • POST_MAPPING_RESYNTHESIS
  • POST_MODULE_SCRIPT_FILE
  • POST_SYNTH
  • POWER_APPLY_THERMAL_MARGIN
  • POWER_AUTO_COMPUTE_TJ
  • POWER_BOARD_TEMPERATURE
  • POWER_BOARD_THERMAL_MODEL
  • POWER_COOLING_FOR_MAX_TJ
  • POWER_DEFAULT_INPUT_IO_TOGGLE_RATE
  • POWER_DEFAULT_TOGGLE_RATE
  • POWER_ESTIMATION_ASSIGNMENT
  • POWER_ESTIMATION_END_TIME
  • POWER_ESTIMATION_START_TIME
  • POWER_GLITCH_FACTOR
  • POWER_HPS_DYNAMIC_POWER_DUAL
  • POWER_HPS_DYNAMIC_POWER_SINGLE
  • POWER_HPS_ENABLE
  • POWER_HPS_JUNCTION_TEMPERATURE
  • POWER_HPS_PROC_FREQ
  • POWER_HPS_STATIC_POWER
  • POWER_HPS_TOTAL_POWER
  • POWER_HSSI_LEFT
  • POWER_HSSI
  • POWER_HSSI_RIGHT
  • POWER_HSSI_VCCHIP_LEFT
  • POWER_HSSI_VCCHIP_RIGHT
  • POWER_INPUT_FILE
  • POWER_INPUT_FILE_NAME
  • POWER_INPUT_FILE_SETTINGS
  • POWER_INPUT_FILE_TYPE
  • POWER
  • POWER_MAX_TJ_VALUE
  • POWER_OCS_VALUE
  • POWER_OJB_VALUE
  • POWER_OJC_VALUE
  • POWER_OSA_VALUE
  • POWER_OUTPUT_SAF_NAME
  • POWER_PRESET_COOLING_SOLUTION
  • POWER_READ_INPUT_FILE
  • POWER_REPORT_POWER_DISSIPATION
  • POWER_REPORT_SIGNAL_ACTIVITY
  • POWER_STATIC_PROBABILITY
  • POWER_STATIC_TOGGLE_RATE
  • POWER_TJ_VALUE
  • POWER_TOGGLE_RATE
  • POWER_TOGGLE_RATE_PERCENTAGE
  • POWER_UP_HIGH
  • POWER_UP_LEVEL
  • POWER_USE_CUSTOM_COOLING_SOLUTION
  • POWER_USE_DEVICE_CHARACTERISTICS
  • POWER_USE_INPUT_FILES
  • POWER_USE_PVA
  • POWER_USE_TA_VALUE
  • POWER_USE_VOLTAGE
  • POWER_VCCA_FPLL_USER_VOLTAGE
  • POWER_VCCA_GTBR_USER_VOLTAGE
  • POWER_VCCA_GTB_USER_VOLTAGE
  • POWER_VCCA_GXBL_USER_OPTION
  • POWER_VCCA_GXBL_USER_VOLTAGE
  • POWER_VCCA_GXBR_USER_OPTION
  • POWER_VCCA_GXBR_USER_VOLTAGE
  • POWER_VCCA_GXB_USER_OPTION
  • POWER_VCCA_GXB_USER_VOLTAGE
  • POWER_VCCA_L_USER_OPTION
  • POWER_VCCA_L_USER_VOLTAGE
  • POWER_VCCA_PLL_USER_VOLTAGE
  • POWER_VCCA_R_USER_OPTION
  • POWER_VCCA_R_USER_VOLTAGE
  • POWER_VCCA_USER_VOLTAGE
  • POWER_VCCAUX_SHARED_USER_VOLTAGE
  • POWER_VCCAUX_USER_OPTION
  • POWER_VCCAUX_USER_VOLTAGE
  • POWER_VCCBAT_USER_VOLTAGE
  • POWER_VCCCB_USER_OPTION
  • POWER_VCCCB_USER_VOLTAGE
  • POWER_VCCD_FPLL_USER_VOLTAGE
  • POWER_VCCD_PLL_USER_VOLTAGE
  • POWER_VCCD_USER_VOLTAGE
  • POWER_VCCE_GXBL_USER_VOLTAGE
  • POWER_VCCE_GXBR_USER_VOLTAGE
  • POWER_VCCE_GXB_USER_VOLTAGE
  • POWER_VCCEH_GXBL_USER_VOLTAGE
  • POWER_VCCEH_GXBR_USER_VOLTAGE
  • POWER_VCCEH_GXB_USER_VOLTAGE
  • POWER_VCCERAM_USER_VOLTAGE
  • POWER_VCCE_USER_VOLTAGE
  • POWER_VCCH_GTBR_USER_VOLTAGE
  • POWER_VCCH_GTB_USER_VOLTAGE
  • POWER_VCCH_GXBL_USER_OPTION
  • POWER_VCCH_GXBL_USER_VOLTAGE
  • POWER_VCCH_GXBR_USER_OPTION
  • POWER_VCCH_GXBR_USER_VOLTAGE
  • POWER_VCCH_GXB_USER_OPTION
  • POWER_VCCH_GXB_USER_VOLTAGE
  • POWER_VCCHIP_L_USER_VOLTAGE
  • POWER_VCCHIP_R_USER_VOLTAGE
  • POWER_VCCHIP_USER_VOLTAGE
  • POWER_VCCH_L_USER_VOLTAGE
  • POWER_VCC_HPS_USER_VOLTAGE
  • POWER_VCCH_R_USER_VOLTAGE
  • POWER_VCCHSSI_L_USER_VOLTAGE
  • POWER_VCCHSSI_R_USER_VOLTAGE
  • POWER_VCCINT_USER_VOLTAGE
  • POWER_VCCIO_HPS_USER_VOLTAGE
  • POWER_VCCIOREF_HPS_USER_VOLTAGE
  • POWER_VCCIO_USER_OPTION
  • POWER_VCCIO_USER_VOLTAGE
  • POWER_VCCL_GTBL_USER_VOLTAGE
  • POWER_VCCL_GTBR_USER_VOLTAGE
  • POWER_VCCL_GTB_USER_VOLTAGE
  • POWER_VCCL_GXBL_USER_VOLTAGE
  • POWER_VCCL_GXBR_USER_VOLTAGE
  • POWER_VCCL_GXB_USER_OPTION
  • POWER_VCCL_GXB_USER_VOLTAGE
  • POWER_VCCL_HPS_USER_VOLTAGE
  • POWER_VCCL_USER_VOLTAGE
  • POWER_VCCPD_USER_OPTION
  • POWER_VCCPD_USER_VOLTAGE
  • POWER_VCCPGM_USER_VOLTAGE
  • POWER_VCCPLL_HPS_USER_VOLTAGE
  • POWER_VCCPT_USER_VOLTAGE
  • POWER_VCCP_USER_VOLTAGE
  • POWER_VCCR_GTBL_USER_VOLTAGE
  • POWER_VCCR_GTBR_USER_VOLTAGE
  • POWER_VCCR_GTB_USER_VOLTAGE
  • POWER_VCCR_GXBL_USER_OPTION
  • POWER_VCCR_GXBL_USER_VOLTAGE
  • POWER_VCCR_GXBR_USER_OPTION
  • POWER_VCCR_GXBR_USER_VOLTAGE
  • POWER_VCCR_GXB_USER_OPTION
  • POWER_VCCR_GXB_USER_VOLTAGE
  • POWER_VCCR_L_USER_VOLTAGE
  • POWER_VCCR_R_USER_VOLTAGE
  • POWER_VCCRSTCLK_HPS_USER_VOLTAGE
  • POWER_VCCR_USER_VOLTAGE
  • POWER_VCCT_GTBL_USER_VOLTAGE
  • POWER_VCCT_GTBR_USER_VOLTAGE
  • POWER_VCCT_GTB_USER_VOLTAGE
  • POWER_VCCT_GXBL_USER_OPTION
  • POWER_VCCT_GXBL_USER_VOLTAGE
  • POWER_VCCT_GXBR_USER_OPTION
  • POWER_VCCT_GXBR_USER_VOLTAGE
  • POWER_VCCT_GXB_USER_OPTION
  • POWER_VCCT_GXB_USER_VOLTAGE
  • POWER_VCCT_L_USER_VOLTAGE
  • POWER_VCCT_R_USER_VOLTAGE
  • POWER_VCCT_USER_VOLTAGE
  • POWER_VCC_USER_VOLTAGE
  • POWER_VCD_FILE_END_TIME
  • POWER_VCD_FILE_START_TIME
  • POWER_VCD_FILTER_GLITCHES
  • POWER_WILDCARDS
  • PPF_FILE
  • PPLQ_GROUP_EXCEPTION
  • PPLQ_GROUP
  • PPLQ_GROUP_MEMBER
  • PR_ALLOW_GLOBAL_LIMS
  • PR_BASE
  • PR_BASE_MSF
  • PR_BASE_SOF
  • PR_DONE_OPEN_DRAIN
  • PRE_CONFIG
  • PRE_FLOW_SCRIPT_FILE
  • PRE_MAPPING_RESYNTHESIS
  • PR_ERROR_OPEN_DRAIN
  • PRESERVED_HANGING_NODES
  • PRESERVE_FANOUT_FREE_NODE
  • PRESERVE_FANOUT_FREE_WYSIWYG
  • PRESERVE_HIERARCHICAL_BOUNDARY
  • PRESERVE
  • PRESERVE_PLL_COUNTER_ORDER
  • PRESERVE_PORT_NAME
  • PRESERVE_REGISTER
  • PRESERVE_REGISTER_SYN_ONLY
  • PRESERVE_SYNONYMS
  • PRESERVE_UNUSED_XCVR_CHANNEL
  • PR_IMPL
  • PRINT_DEBUG_MSG_AND_EXIT
  • PRIORITY_SEU_AREA
  • PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10
  • PROCESSOR
  • PRODUCT_TERM
  • PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES
  • PROGRAMMABLE_POWER_TECHNOLOGY_SETTING
  • PROGRAMMABLE_PREEMPHASIS
  • PROGRAMMABLE_VOD
  • PROGRAMMER_ASSIGNMENT
  • PROGRAMMER_OBJECT_FILE
  • PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT
  • PROGRAMMING_BITSTREAM_ENCRYPTION_UPDATE_RATIO
  • PROGRAMMING_FILE_TYPE
  • PROGRAMMING_MODE_APEX20KF
  • PROGRAMMING_MODE_APEX20K
  • PROGRAMMING_MODE_ARMSTRONG
  • PROGRAMMING_MODE_CUDA
  • PROGRAMMING_MODE_CYCLONEII
  • PROGRAMMING_MODE_DALI
  • PROGRAMMING_MODE_EXCALIBUR
  • PROGRAMMING_MODE_FLEX10K
  • PROGRAMMING_MODE_FLEX6K
  • PROGRAMMING_MODE
  • PROGRAMMING_MODE_TITAN
  • PROGRAMMING_MODE_TORNADO
  • PROGRAMMING_MODE_YEAGER
  • PROGRAMMING_MODE_ZIPPLEBACK
  • PROJECT_ASSIGNMENT
  • PROJECT_CREATION_TIME_DATE
  • PROJECT_INFO
  • PROJECT_IP_GEN_PARALLEL_ENABLED
  • PROJECT_IP_GEN_SIM_FILESETS_WITH_SYNTHESIS
  • PROJECT_IP_REGENERATION_POLICY
  • PROJECT_IP_SEARCH_PATHS
  • PROJECT_IP_SIM_REGENERATION_POLICY
  • PROJECT_MIGRATION_TIMESTAMP
  • PROJECT_OUTPUT_DIRECTORY
  • PROJECT_SHOW_ENTITY_NAME
  • PROJECT_SOURCE_FILE
  • PROJECT_THUNDER_BAY
  • PROJECT_USE_SIMPLIFIED_NAMES
  • PRO_ONLY
  • PROPAGATE_CONSTANTS_ON_INPUTS
  • PROPAGATE_INVERSIONS_ON_INPUTS
  • PR_PARTITION
  • PR_PINS_OPEN_DRAIN
  • PRPOF_ID_CHECK
  • PRPOF_ID
  • PRPOF_ID_VALUE
  • PR_READY_OPEN_DRAIN
  • PR_SECURITY_VALIDATION
  • PR_SKIP_BASE_CHECK
  • PR_SYN
  • PULL_DN
  • PULLDOWN_DRIVE_STRENGTH_BITS
  • PULL_DOWN
  • PULL_RESISTOR
  • PULLUP_DRIVE_STRENGTH_BITS
  • PULL_UP
  • PULL_UP_TO_VCCELA
  • PULSE_WIDTH_0
  • PULSE_WIDTH_1
  • PULSE_WIDTH_2_LARGE
  • PULSE_WIDTH_2
  • PULSE_WIDTH_NONE
  • PWRMGT_ADV_CLOCK_DATA_FALL_TIME
  • PWRMGT_ADV_CLOCK_DATA_RISE_TIME
  • PWRMGT_ADV_DATA_HOLD_TIME
  • PWRMGT_ADV_DATA_SETUP_TIME
  • PWRMGT_ADV_FPGA_RELEASE_DELAY
  • PWRMGT_ADV_INITIAL_DELAY
  • PWRMGT_ADV_VOLTAGE_STABLE_DELAY
  • PWRMGT_ADV_VOUT_READING_ERR_MARGIN
  • PWRMGT_BUS_SPEED_MODE
  • PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_B
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_M
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_R
  • PWRMGT_LINEAR_FORMAT_N
  • PWRMGT_PAGE_COMMAND_ENABLE
  • PWRMGT_SLAVE_DEVICE0_ADDRESS
  • PWRMGT_SLAVE_DEVICE1_ADDRESS
  • PWRMGT_SLAVE_DEVICE2_ADDRESS
  • PWRMGT_SLAVE_DEVICE3_ADDRESS
  • PWRMGT_SLAVE_DEVICE4_ADDRESS
  • PWRMGT_SLAVE_DEVICE5_ADDRESS
  • PWRMGT_SLAVE_DEVICE6_ADDRESS
  • PWRMGT_SLAVE_DEVICE7_ADDRESS
  • PWRMGT_SLAVE_DEVICE_TYPE
  • PWRMGT_TABLE_VERSION
  • PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT
  • PWRMGT_VOLTAGE_OUTPUT_FORMAT
  • QAR_FILE
  • QARLOG_FILE
  • QDB_FILE
  • QDB_FILE_PARTITION
  • QDB_PATH
  • QDFS_USE_CHERRY
  • QDR_D_PIN_GROUP
  • QHD_MODE
  • QIC_EXPORT_FILE
  • QIC_EXPORT_FLATTEN
  • QIC_EXPORT_NETLIST_TYPE
  • QIC_EXPORT_PARTITION_NAME
  • QIC_EXPORT_ROUTING
  • QIC_USE_BINARY_DATABASES
  • QID_ASSIGNMENT
  • QII_AUTO_PACKED_REGISTERS
  • QIP_FILE
  • QKY_FILE
  • QPI_MODE
  • QSGMII_5000
  • QSYS_FILE
  • QUARTUS_ACF_FILE
  • QUARTUS_COMPILER_SETTINGS_FILE
  • QUARTUS_ENTITY_SETTINGS_FILE
  • QUARTUS_GUI_SIGNATURE_ID
  • QUARTUSII
  • QUARTUS_PROJECT_FILE
  • QUARTUS_PROJECT_SETTINGS_FILE
  • QUARTUS_PTF_FILE
  • QUARTUS_SBD_FILE
  • QUARTUS_SIMULATOR_SETTINGS_FILE
  • QUARTUS_SOFTWARE_SETTINGS_FILE
  • QUARTUS_STANDARD_DELAY_FILE
  • QUARTUS_WORKSPACE_FILE
  • QVAR_FILE
  • QXP_FILE
  • R_ADAPT_DFE_CONTROL_SEL_0
  • R_ADAPT_DFE_CONTROL_SEL_1
  • R_ADAPT_DFE_CONTROL_SEL_2
  • R_ADAPT_DFE_CONTROL_SEL_3
  • R_ADAPT_DFE_SEL_0
  • R_ADAPT_DFE_SEL_1
  • R_ADAPT_VGA_SEL_0
  • R_ADAPT_VGA_SEL_1
  • R_ADAPT_VREF_SEL_0
  • R_ADAPT_VREF_SEL_1
  • R_ADAPT_VREF_SEL_2
  • R_ADAPT_VREF_SEL_3
  • RADP_CTLE_ACGAIN_4S_0
  • RADP_CTLE_ACGAIN_4S_10
  • RADP_CTLE_ACGAIN_4S_11
  • RADP_CTLE_ACGAIN_4S_12
  • RADP_CTLE_ACGAIN_4S_13
  • RADP_CTLE_ACGAIN_4S_14
  • RADP_CTLE_ACGAIN_4S_15
  • RADP_CTLE_ACGAIN_4S_16
  • RADP_CTLE_ACGAIN_4S_17
  • RADP_CTLE_ACGAIN_4S_18
  • RADP_CTLE_ACGAIN_4S_19
  • RADP_CTLE_ACGAIN_4S_1
  • RADP_CTLE_ACGAIN_4S_20
  • RADP_CTLE_ACGAIN_4S_21
  • RADP_CTLE_ACGAIN_4S_22
  • RADP_CTLE_ACGAIN_4S_23
  • RADP_CTLE_ACGAIN_4S_24
  • RADP_CTLE_ACGAIN_4S_25
  • RADP_CTLE_ACGAIN_4S_26
  • RADP_CTLE_ACGAIN_4S_27
  • RADP_CTLE_ACGAIN_4S_28
  • RADP_CTLE_ACGAIN_4S_2
  • RADP_CTLE_ACGAIN_4S_3
  • RADP_CTLE_ACGAIN_4S_4
  • RADP_CTLE_ACGAIN_4S_5
  • RADP_CTLE_ACGAIN_4S_6
  • RADP_CTLE_ACGAIN_4S_7
  • RADP_CTLE_ACGAIN_4S_8
  • RADP_CTLE_ACGAIN_4S_9
  • RADP_CTLE_EQZ_1S_SEL_0
  • RADP_CTLE_EQZ_1S_SEL_10
  • RADP_CTLE_EQZ_1S_SEL_11
  • RADP_CTLE_EQZ_1S_SEL_12
  • RADP_CTLE_EQZ_1S_SEL_13
  • RADP_CTLE_EQZ_1S_SEL_14
  • RADP_CTLE_EQZ_1S_SEL_15
  • RADP_CTLE_EQZ_1S_SEL_1
  • RADP_CTLE_EQZ_1S_SEL_2
  • RADP_CTLE_EQZ_1S_SEL_3
  • RADP_CTLE_EQZ_1S_SEL_4
  • RADP_CTLE_EQZ_1S_SEL_5
  • RADP_CTLE_EQZ_1S_SEL_6
  • RADP_CTLE_EQZ_1S_SEL_7
  • RADP_CTLE_EQZ_1S_SEL_8
  • RADP_CTLE_EQZ_1S_SEL_9
  • RADP_DFE_FLTAP_POSITION_0
  • RADP_DFE_FLTAP_POSITION_10
  • RADP_DFE_FLTAP_POSITION_11
  • RADP_DFE_FLTAP_POSITION_12
  • RADP_DFE_FLTAP_POSITION_13
  • RADP_DFE_FLTAP_POSITION_14
  • RADP_DFE_FLTAP_POSITION_15
  • RADP_DFE_FLTAP_POSITION_16
  • RADP_DFE_FLTAP_POSITION_17
  • RADP_DFE_FLTAP_POSITION_18
  • RADP_DFE_FLTAP_POSITION_19
  • RADP_DFE_FLTAP_POSITION_1
  • RADP_DFE_FLTAP_POSITION_20
  • RADP_DFE_FLTAP_POSITION_21
  • RADP_DFE_FLTAP_POSITION_22
  • RADP_DFE_FLTAP_POSITION_23
  • RADP_DFE_FLTAP_POSITION_24
  • RADP_DFE_FLTAP_POSITION_25
  • RADP_DFE_FLTAP_POSITION_26
  • RADP_DFE_FLTAP_POSITION_27
  • RADP_DFE_FLTAP_POSITION_28
  • RADP_DFE_FLTAP_POSITION_29
  • RADP_DFE_FLTAP_POSITION_2
  • RADP_DFE_FLTAP_POSITION_30
  • RADP_DFE_FLTAP_POSITION_31
  • RADP_DFE_FLTAP_POSITION_32
  • RADP_DFE_FLTAP_POSITION_33
  • RADP_DFE_FLTAP_POSITION_34
  • RADP_DFE_FLTAP_POSITION_35
  • RADP_DFE_FLTAP_POSITION_36
  • RADP_DFE_FLTAP_POSITION_37
  • RADP_DFE_FLTAP_POSITION_38
  • RADP_DFE_FLTAP_POSITION_39
  • RADP_DFE_FLTAP_POSITION_3
  • RADP_DFE_FLTAP_POSITION_40
  • RADP_DFE_FLTAP_POSITION_41
  • RADP_DFE_FLTAP_POSITION_42
  • RADP_DFE_FLTAP_POSITION_43
  • RADP_DFE_FLTAP_POSITION_44
  • RADP_DFE_FLTAP_POSITION_45
  • RADP_DFE_FLTAP_POSITION_46
  • RADP_DFE_FLTAP_POSITION_47
  • RADP_DFE_FLTAP_POSITION_48
  • RADP_DFE_FLTAP_POSITION_49
  • RADP_DFE_FLTAP_POSITION_4
  • RADP_DFE_FLTAP_POSITION_50
  • RADP_DFE_FLTAP_POSITION_51
  • RADP_DFE_FLTAP_POSITION_52
  • RADP_DFE_FLTAP_POSITION_53
  • RADP_DFE_FLTAP_POSITION_54
  • RADP_DFE_FLTAP_POSITION_55
  • RADP_DFE_FLTAP_POSITION_5
  • RADP_DFE_FLTAP_POSITION_6
  • RADP_DFE_FLTAP_POSITION_7
  • RADP_DFE_FLTAP_POSITION_8
  • RADP_DFE_FLTAP_POSITION_9
  • RADP_DFE_FXTAP10_0
  • RADP_DFE_FXTAP10_10
  • RADP_DFE_FXTAP10_11
  • RADP_DFE_FXTAP10_12
  • RADP_DFE_FXTAP10_13
  • RADP_DFE_FXTAP10_14
  • RADP_DFE_FXTAP10_15
  • RADP_DFE_FXTAP10_16
  • RADP_DFE_FXTAP10_17
  • RADP_DFE_FXTAP10_18
  • RADP_DFE_FXTAP10_19
  • RADP_DFE_FXTAP10_1
  • RADP_DFE_FXTAP10_20
  • RADP_DFE_FXTAP10_21
  • RADP_DFE_FXTAP10_22
  • RADP_DFE_FXTAP10_23
  • RADP_DFE_FXTAP10_24
  • RADP_DFE_FXTAP10_25
  • RADP_DFE_FXTAP10_26
  • RADP_DFE_FXTAP10_27
  • RADP_DFE_FXTAP10_28
  • RADP_DFE_FXTAP10_29
  • RADP_DFE_FXTAP10_2
  • RADP_DFE_FXTAP10_30
  • RADP_DFE_FXTAP10_31
  • RADP_DFE_FXTAP10_32
  • RADP_DFE_FXTAP10_33
  • RADP_DFE_FXTAP10_34
  • RADP_DFE_FXTAP10_35
  • RADP_DFE_FXTAP10_36
  • RADP_DFE_FXTAP10_37
  • RADP_DFE_FXTAP10_38
  • RADP_DFE_FXTAP10_39
  • RADP_DFE_FXTAP10_3
  • RADP_DFE_FXTAP10_40
  • RADP_DFE_FXTAP10_41
  • RADP_DFE_FXTAP10_42
  • RADP_DFE_FXTAP10_43
  • RADP_DFE_FXTAP10_44
  • RADP_DFE_FXTAP10_45
  • RADP_DFE_FXTAP10_46
  • RADP_DFE_FXTAP10_47
  • RADP_DFE_FXTAP10_48
  • RADP_DFE_FXTAP10_49
  • RADP_DFE_FXTAP10_4
  • RADP_DFE_FXTAP10_50
  • RADP_DFE_FXTAP10_51
  • RADP_DFE_FXTAP10_52
  • RADP_DFE_FXTAP10_53
  • RADP_DFE_FXTAP10_54
  • RADP_DFE_FXTAP10_55
  • RADP_DFE_FXTAP10_56
  • RADP_DFE_FXTAP10_57
  • RADP_DFE_FXTAP10_58
  • RADP_DFE_FXTAP10_59
  • RADP_DFE_FXTAP10_5
  • RADP_DFE_FXTAP10_60
  • RADP_DFE_FXTAP10_61
  • RADP_DFE_FXTAP10_62
  • RADP_DFE_FXTAP10_63
  • RADP_DFE_FXTAP10_6
  • RADP_DFE_FXTAP10_7
  • RADP_DFE_FXTAP10_8
  • RADP_DFE_FXTAP10_9
  • RADP_DFE_FXTAP1_0
  • RADP_DFE_FXTAP10_SGN_0
  • RADP_DFE_FXTAP10_SGN_1
  • RADP_DFE_FXTAP1_100
  • RADP_DFE_FXTAP1_101
  • RADP_DFE_FXTAP1_102
  • RADP_DFE_FXTAP1_103
  • RADP_DFE_FXTAP1_104
  • RADP_DFE_FXTAP1_105
  • RADP_DFE_FXTAP1_106
  • RADP_DFE_FXTAP1_107
  • RADP_DFE_FXTAP1_108
  • RADP_DFE_FXTAP1_109
  • RADP_DFE_FXTAP1_10
  • RADP_DFE_FXTAP11_0
  • RADP_DFE_FXTAP1_110
  • RADP_DFE_FXTAP11_10
  • RADP_DFE_FXTAP1_111
  • RADP_DFE_FXTAP11_11
  • RADP_DFE_FXTAP1_112
  • RADP_DFE_FXTAP11_12
  • RADP_DFE_FXTAP1_113
  • RADP_DFE_FXTAP11_13
  • RADP_DFE_FXTAP1_114
  • RADP_DFE_FXTAP11_14
  • RADP_DFE_FXTAP1_115
  • RADP_DFE_FXTAP11_15
  • RADP_DFE_FXTAP1_116
  • RADP_DFE_FXTAP11_16
  • RADP_DFE_FXTAP1_117
  • RADP_DFE_FXTAP11_17
  • RADP_DFE_FXTAP1_118
  • RADP_DFE_FXTAP11_18
  • RADP_DFE_FXTAP1_119
  • RADP_DFE_FXTAP11_19
  • RADP_DFE_FXTAP1_11
  • RADP_DFE_FXTAP11_1
  • RADP_DFE_FXTAP1_120
  • RADP_DFE_FXTAP11_20
  • RADP_DFE_FXTAP1_121
  • RADP_DFE_FXTAP11_21
  • RADP_DFE_FXTAP1_122
  • RADP_DFE_FXTAP11_22
  • RADP_DFE_FXTAP1_123
  • RADP_DFE_FXTAP11_23
  • RADP_DFE_FXTAP1_124
  • RADP_DFE_FXTAP11_24
  • RADP_DFE_FXTAP1_125
  • RADP_DFE_FXTAP11_25
  • RADP_DFE_FXTAP1_126
  • RADP_DFE_FXTAP11_26
  • RADP_DFE_FXTAP1_127
  • RADP_DFE_FXTAP11_27
  • RADP_DFE_FXTAP11_28
  • RADP_DFE_FXTAP11_29
  • RADP_DFE_FXTAP1_12
  • RADP_DFE_FXTAP11_2
  • RADP_DFE_FXTAP11_30
  • RADP_DFE_FXTAP11_31
  • RADP_DFE_FXTAP11_32
  • RADP_DFE_FXTAP11_33
  • RADP_DFE_FXTAP11_34
  • RADP_DFE_FXTAP11_35
  • RADP_DFE_FXTAP11_36
  • RADP_DFE_FXTAP11_37
  • RADP_DFE_FXTAP11_38
  • RADP_DFE_FXTAP11_39
  • RADP_DFE_FXTAP1_13
  • RADP_DFE_FXTAP11_3
  • RADP_DFE_FXTAP11_40
  • RADP_DFE_FXTAP11_41
  • RADP_DFE_FXTAP11_42
  • RADP_DFE_FXTAP11_43
  • RADP_DFE_FXTAP11_44
  • RADP_DFE_FXTAP11_45
  • RADP_DFE_FXTAP11_46
  • RADP_DFE_FXTAP11_47
  • RADP_DFE_FXTAP11_48
  • RADP_DFE_FXTAP11_49
  • RADP_DFE_FXTAP1_14
  • RADP_DFE_FXTAP11_4
  • RADP_DFE_FXTAP11_50
  • RADP_DFE_FXTAP11_51
  • RADP_DFE_FXTAP11_52
  • RADP_DFE_FXTAP11_53
  • RADP_DFE_FXTAP11_54
  • RADP_DFE_FXTAP11_55
  • RADP_DFE_FXTAP11_56
  • RADP_DFE_FXTAP11_57
  • RADP_DFE_FXTAP11_58
  • RADP_DFE_FXTAP11_59
  • RADP_DFE_FXTAP1_15
  • RADP_DFE_FXTAP11_5
  • RADP_DFE_FXTAP11_60
  • RADP_DFE_FXTAP11_61
  • RADP_DFE_FXTAP11_62
  • RADP_DFE_FXTAP11_63
  • RADP_DFE_FXTAP1_16
  • RADP_DFE_FXTAP11_6
  • RADP_DFE_FXTAP1_17
  • RADP_DFE_FXTAP11_7
  • RADP_DFE_FXTAP1_18
  • RADP_DFE_FXTAP11_8
  • RADP_DFE_FXTAP1_19
  • RADP_DFE_FXTAP11_9
  • RADP_DFE_FXTAP1_1
  • RADP_DFE_FXTAP11_SGN_0
  • RADP_DFE_FXTAP11_SGN_1
  • RADP_DFE_FXTAP1_20
  • RADP_DFE_FXTAP1_21
  • RADP_DFE_FXTAP1_22
  • RADP_DFE_FXTAP1_23
  • RADP_DFE_FXTAP1_24
  • RADP_DFE_FXTAP1_25
  • RADP_DFE_FXTAP1_26
  • RADP_DFE_FXTAP1_27
  • RADP_DFE_FXTAP1_28
  • RADP_DFE_FXTAP1_29
  • RADP_DFE_FXTAP1_2
  • RADP_DFE_FXTAP1_30
  • RADP_DFE_FXTAP1_31
  • RADP_DFE_FXTAP1_32
  • RADP_DFE_FXTAP1_33
  • RADP_DFE_FXTAP1_34
  • RADP_DFE_FXTAP1_35
  • RADP_DFE_FXTAP1_36
  • RADP_DFE_FXTAP1_37
  • RADP_DFE_FXTAP1_38
  • RADP_DFE_FXTAP1_39
  • RADP_DFE_FXTAP1_3
  • RADP_DFE_FXTAP1_40
  • RADP_DFE_FXTAP1_41
  • RADP_DFE_FXTAP1_42
  • RADP_DFE_FXTAP1_43
  • RADP_DFE_FXTAP1_44
  • RADP_DFE_FXTAP1_45
  • RADP_DFE_FXTAP1_46
  • RADP_DFE_FXTAP1_47
  • RADP_DFE_FXTAP1_48
  • RADP_DFE_FXTAP1_49
  • RADP_DFE_FXTAP1_4
  • RADP_DFE_FXTAP1_50
  • RADP_DFE_FXTAP1_51
  • RADP_DFE_FXTAP1_52
  • RADP_DFE_FXTAP1_53
  • RADP_DFE_FXTAP1_54
  • RADP_DFE_FXTAP1_55
  • RADP_DFE_FXTAP1_56
  • RADP_DFE_FXTAP1_57
  • RADP_DFE_FXTAP1_58
  • RADP_DFE_FXTAP1_59
  • RADP_DFE_FXTAP1_5
  • RADP_DFE_FXTAP1_60
  • RADP_DFE_FXTAP1_61
  • RADP_DFE_FXTAP1_62
  • RADP_DFE_FXTAP1_63
  • RADP_DFE_FXTAP1_64
  • RADP_DFE_FXTAP1_65
  • RADP_DFE_FXTAP1_66
  • RADP_DFE_FXTAP1_67
  • RADP_DFE_FXTAP1_68
  • RADP_DFE_FXTAP1_69
  • RADP_DFE_FXTAP1_6
  • RADP_DFE_FXTAP1_70
  • RADP_DFE_FXTAP1_71
  • RADP_DFE_FXTAP1_72
  • RADP_DFE_FXTAP1_73
  • RADP_DFE_FXTAP1_74
  • RADP_DFE_FXTAP1_75
  • RADP_DFE_FXTAP1_76
  • RADP_DFE_FXTAP1_77
  • RADP_DFE_FXTAP1_78
  • RADP_DFE_FXTAP1_79
  • RADP_DFE_FXTAP1_7
  • RADP_DFE_FXTAP1_80
  • RADP_DFE_FXTAP1_81
  • RADP_DFE_FXTAP1_82
  • RADP_DFE_FXTAP1_83
  • RADP_DFE_FXTAP1_84
  • RADP_DFE_FXTAP1_85
  • RADP_DFE_FXTAP1_86
  • RADP_DFE_FXTAP1_87
  • RADP_DFE_FXTAP1_88
  • RADP_DFE_FXTAP1_89
  • RADP_DFE_FXTAP1_8
  • RADP_DFE_FXTAP1_90
  • RADP_DFE_FXTAP1_91
  • RADP_DFE_FXTAP1_92
  • RADP_DFE_FXTAP1_93
  • RADP_DFE_FXTAP1_94
  • RADP_DFE_FXTAP1_95
  • RADP_DFE_FXTAP1_96
  • RADP_DFE_FXTAP1_97
  • RADP_DFE_FXTAP1_98
  • RADP_DFE_FXTAP1_99
  • RADP_DFE_FXTAP1_9
  • RADP_DFE_FXTAP2_0
  • RADP_DFE_FXTAP2_100
  • RADP_DFE_FXTAP2_101
  • RADP_DFE_FXTAP2_102
  • RADP_DFE_FXTAP2_103
  • RADP_DFE_FXTAP2_104
  • RADP_DFE_FXTAP2_105
  • RADP_DFE_FXTAP2_106
  • RADP_DFE_FXTAP2_107
  • RADP_DFE_FXTAP2_108
  • RADP_DFE_FXTAP2_109
  • RADP_DFE_FXTAP2_10
  • RADP_DFE_FXTAP2_110
  • RADP_DFE_FXTAP2_111
  • RADP_DFE_FXTAP2_112
  • RADP_DFE_FXTAP2_113
  • RADP_DFE_FXTAP2_114
  • RADP_DFE_FXTAP2_115
  • RADP_DFE_FXTAP2_116
  • RADP_DFE_FXTAP2_117
  • RADP_DFE_FXTAP2_118
  • RADP_DFE_FXTAP2_119
  • RADP_DFE_FXTAP2_11
  • RADP_DFE_FXTAP2_120
  • RADP_DFE_FXTAP2_121
  • RADP_DFE_FXTAP2_122
  • RADP_DFE_FXTAP2_123
  • RADP_DFE_FXTAP2_124
  • RADP_DFE_FXTAP2_125
  • RADP_DFE_FXTAP2_126
  • RADP_DFE_FXTAP2_127
  • RADP_DFE_FXTAP2_12
  • RADP_DFE_FXTAP2_13
  • RADP_DFE_FXTAP2_14
  • RADP_DFE_FXTAP2_15
  • RADP_DFE_FXTAP2_16
  • RADP_DFE_FXTAP2_17
  • RADP_DFE_FXTAP2_18
  • RADP_DFE_FXTAP2_19
  • RADP_DFE_FXTAP2_1
  • RADP_DFE_FXTAP2_20
  • RADP_DFE_FXTAP2_21
  • RADP_DFE_FXTAP2_22
  • RADP_DFE_FXTAP2_23
  • RADP_DFE_FXTAP2_24
  • RADP_DFE_FXTAP2_25
  • RADP_DFE_FXTAP2_26
  • RADP_DFE_FXTAP2_27
  • RADP_DFE_FXTAP2_28
  • RADP_DFE_FXTAP2_29
  • RADP_DFE_FXTAP2_2
  • RADP_DFE_FXTAP2_30
  • RADP_DFE_FXTAP2_31
  • RADP_DFE_FXTAP2_32
  • RADP_DFE_FXTAP2_33
  • RADP_DFE_FXTAP2_34
  • RADP_DFE_FXTAP2_35
  • RADP_DFE_FXTAP2_36
  • RADP_DFE_FXTAP2_37
  • RADP_DFE_FXTAP2_38
  • RADP_DFE_FXTAP2_39
  • RADP_DFE_FXTAP2_3
  • RADP_DFE_FXTAP2_40
  • RADP_DFE_FXTAP2_41
  • RADP_DFE_FXTAP2_42
  • RADP_DFE_FXTAP2_43
  • RADP_DFE_FXTAP2_44
  • RADP_DFE_FXTAP2_45
  • RADP_DFE_FXTAP2_46
  • RADP_DFE_FXTAP2_47
  • RADP_DFE_FXTAP2_48
  • RADP_DFE_FXTAP2_49
  • RADP_DFE_FXTAP2_4
  • RADP_DFE_FXTAP2_50
  • RADP_DFE_FXTAP2_51
  • RADP_DFE_FXTAP2_52
  • RADP_DFE_FXTAP2_53
  • RADP_DFE_FXTAP2_54
  • RADP_DFE_FXTAP2_55
  • RADP_DFE_FXTAP2_56
  • RADP_DFE_FXTAP2_57
  • RADP_DFE_FXTAP2_58
  • RADP_DFE_FXTAP2_59
  • RADP_DFE_FXTAP2_5
  • RADP_DFE_FXTAP2_60
  • RADP_DFE_FXTAP2_61
  • RADP_DFE_FXTAP2_62
  • RADP_DFE_FXTAP2_63
  • RADP_DFE_FXTAP2_64
  • RADP_DFE_FXTAP2_65
  • RADP_DFE_FXTAP2_66
  • RADP_DFE_FXTAP2_67
  • RADP_DFE_FXTAP2_68
  • RADP_DFE_FXTAP2_69
  • RADP_DFE_FXTAP2_6
  • RADP_DFE_FXTAP2_70
  • RADP_DFE_FXTAP2_71
  • RADP_DFE_FXTAP2_72
  • RADP_DFE_FXTAP2_73
  • RADP_DFE_FXTAP2_74
  • RADP_DFE_FXTAP2_75
  • RADP_DFE_FXTAP2_76
  • RADP_DFE_FXTAP2_77
  • RADP_DFE_FXTAP2_78
  • RADP_DFE_FXTAP2_79
  • RADP_DFE_FXTAP2_7
  • RADP_DFE_FXTAP2_80
  • RADP_DFE_FXTAP2_81
  • RADP_DFE_FXTAP2_82
  • RADP_DFE_FXTAP2_83
  • RADP_DFE_FXTAP2_84
  • RADP_DFE_FXTAP2_85
  • RADP_DFE_FXTAP2_86
  • RADP_DFE_FXTAP2_87
  • RADP_DFE_FXTAP2_88
  • RADP_DFE_FXTAP2_89
  • RADP_DFE_FXTAP2_8
  • RADP_DFE_FXTAP2_90
  • RADP_DFE_FXTAP2_91
  • RADP_DFE_FXTAP2_92
  • RADP_DFE_FXTAP2_93
  • RADP_DFE_FXTAP2_94
  • RADP_DFE_FXTAP2_95
  • RADP_DFE_FXTAP2_96
  • RADP_DFE_FXTAP2_97
  • RADP_DFE_FXTAP2_98
  • RADP_DFE_FXTAP2_99
  • RADP_DFE_FXTAP2_9
  • RADP_DFE_FXTAP2_SGN_0
  • RADP_DFE_FXTAP2_SGN_1
  • RADP_DFE_FXTAP3_0
  • RADP_DFE_FXTAP3_100
  • RADP_DFE_FXTAP3_101
  • RADP_DFE_FXTAP3_102
  • RADP_DFE_FXTAP3_103
  • RADP_DFE_FXTAP3_104
  • RADP_DFE_FXTAP3_105
  • RADP_DFE_FXTAP3_106
  • RADP_DFE_FXTAP3_107
  • RADP_DFE_FXTAP3_108
  • RADP_DFE_FXTAP3_109
  • RADP_DFE_FXTAP3_10
  • RADP_DFE_FXTAP3_110
  • RADP_DFE_FXTAP3_111
  • RADP_DFE_FXTAP3_112
  • RADP_DFE_FXTAP3_113
  • RADP_DFE_FXTAP3_114
  • RADP_DFE_FXTAP3_115
  • RADP_DFE_FXTAP3_116
  • RADP_DFE_FXTAP3_117
  • RADP_DFE_FXTAP3_118
  • RADP_DFE_FXTAP3_119
  • RADP_DFE_FXTAP3_11
  • RADP_DFE_FXTAP3_120
  • RADP_DFE_FXTAP3_121
  • RADP_DFE_FXTAP3_122
  • RADP_DFE_FXTAP3_123
  • RADP_DFE_FXTAP3_124
  • RADP_DFE_FXTAP3_125
  • RADP_DFE_FXTAP3_126
  • RADP_DFE_FXTAP3_127
  • RADP_DFE_FXTAP3_12
  • RADP_DFE_FXTAP3_13
  • RADP_DFE_FXTAP3_14
  • RADP_DFE_FXTAP3_15
  • RADP_DFE_FXTAP3_16
  • RADP_DFE_FXTAP3_17
  • RADP_DFE_FXTAP3_18
  • RADP_DFE_FXTAP3_19
  • RADP_DFE_FXTAP3_1
  • RADP_DFE_FXTAP3_20
  • RADP_DFE_FXTAP3_21
  • RADP_DFE_FXTAP3_22
  • RADP_DFE_FXTAP3_23
  • RADP_DFE_FXTAP3_24
  • RADP_DFE_FXTAP3_25
  • RADP_DFE_FXTAP3_26
  • RADP_DFE_FXTAP3_27
  • RADP_DFE_FXTAP3_28
  • RADP_DFE_FXTAP3_29
  • RADP_DFE_FXTAP3_2
  • RADP_DFE_FXTAP3_30
  • RADP_DFE_FXTAP3_31
  • RADP_DFE_FXTAP3_32
  • RADP_DFE_FXTAP3_33
  • RADP_DFE_FXTAP3_34
  • RADP_DFE_FXTAP3_35
  • RADP_DFE_FXTAP3_36
  • RADP_DFE_FXTAP3_37
  • RADP_DFE_FXTAP3_38
  • RADP_DFE_FXTAP3_39
  • RADP_DFE_FXTAP3_3
  • RADP_DFE_FXTAP3_40
  • RADP_DFE_FXTAP3_41
  • RADP_DFE_FXTAP3_42
  • RADP_DFE_FXTAP3_43
  • RADP_DFE_FXTAP3_44
  • RADP_DFE_FXTAP3_45
  • RADP_DFE_FXTAP3_46
  • RADP_DFE_FXTAP3_47
  • RADP_DFE_FXTAP3_48
  • RADP_DFE_FXTAP3_49
  • RADP_DFE_FXTAP3_4
  • RADP_DFE_FXTAP3_50
  • RADP_DFE_FXTAP3_51
  • RADP_DFE_FXTAP3_52
  • RADP_DFE_FXTAP3_53
  • RADP_DFE_FXTAP3_54
  • RADP_DFE_FXTAP3_55
  • RADP_DFE_FXTAP3_56
  • RADP_DFE_FXTAP3_57
  • RADP_DFE_FXTAP3_58
  • RADP_DFE_FXTAP3_59
  • RADP_DFE_FXTAP3_5
  • RADP_DFE_FXTAP3_60
  • RADP_DFE_FXTAP3_61
  • RADP_DFE_FXTAP3_62
  • RADP_DFE_FXTAP3_63
  • RADP_DFE_FXTAP3_64
  • RADP_DFE_FXTAP3_65
  • RADP_DFE_FXTAP3_66
  • RADP_DFE_FXTAP3_67
  • RADP_DFE_FXTAP3_68
  • RADP_DFE_FXTAP3_69
  • RADP_DFE_FXTAP3_6
  • RADP_DFE_FXTAP3_70
  • RADP_DFE_FXTAP3_71
  • RADP_DFE_FXTAP3_72
  • RADP_DFE_FXTAP3_73
  • RADP_DFE_FXTAP3_74
  • RADP_DFE_FXTAP3_75
  • RADP_DFE_FXTAP3_76
  • RADP_DFE_FXTAP3_77
  • RADP_DFE_FXTAP3_78
  • RADP_DFE_FXTAP3_79
  • RADP_DFE_FXTAP3_7
  • RADP_DFE_FXTAP3_80
  • RADP_DFE_FXTAP3_81
  • RADP_DFE_FXTAP3_82
  • RADP_DFE_FXTAP3_83
  • RADP_DFE_FXTAP3_84
  • RADP_DFE_FXTAP3_85
  • RADP_DFE_FXTAP3_86
  • RADP_DFE_FXTAP3_87
  • RADP_DFE_FXTAP3_88
  • RADP_DFE_FXTAP3_89
  • RADP_DFE_FXTAP3_8
  • RADP_DFE_FXTAP3_90
  • RADP_DFE_FXTAP3_91
  • RADP_DFE_FXTAP3_92
  • RADP_DFE_FXTAP3_93
  • RADP_DFE_FXTAP3_94
  • RADP_DFE_FXTAP3_95
  • RADP_DFE_FXTAP3_96
  • RADP_DFE_FXTAP3_97
  • RADP_DFE_FXTAP3_98
  • RADP_DFE_FXTAP3_99
  • RADP_DFE_FXTAP3_9
  • RADP_DFE_FXTAP3_SGN_0
  • RADP_DFE_FXTAP3_SGN_1
  • RADP_DFE_FXTAP4_0
  • RADP_DFE_FXTAP4_10
  • RADP_DFE_FXTAP4_11
  • RADP_DFE_FXTAP4_12
  • RADP_DFE_FXTAP4_13
  • RADP_DFE_FXTAP4_14
  • RADP_DFE_FXTAP4_15
  • RADP_DFE_FXTAP4_16
  • RADP_DFE_FXTAP4_17
  • RADP_DFE_FXTAP4_18
  • RADP_DFE_FXTAP4_19
  • RADP_DFE_FXTAP4_1
  • RADP_DFE_FXTAP4_20
  • RADP_DFE_FXTAP4_21
  • RADP_DFE_FXTAP4_22
  • RADP_DFE_FXTAP4_23
  • RADP_DFE_FXTAP4_24
  • RADP_DFE_FXTAP4_25
  • RADP_DFE_FXTAP4_26
  • RADP_DFE_FXTAP4_27
  • RADP_DFE_FXTAP4_28
  • RADP_DFE_FXTAP4_29
  • RADP_DFE_FXTAP4_2
  • RADP_DFE_FXTAP4_30
  • RADP_DFE_FXTAP4_31
  • RADP_DFE_FXTAP4_32
  • RADP_DFE_FXTAP4_33
  • RADP_DFE_FXTAP4_34
  • RADP_DFE_FXTAP4_35
  • RADP_DFE_FXTAP4_36
  • RADP_DFE_FXTAP4_37
  • RADP_DFE_FXTAP4_38
  • RADP_DFE_FXTAP4_39
  • RADP_DFE_FXTAP4_3
  • RADP_DFE_FXTAP4_40
  • RADP_DFE_FXTAP4_41
  • RADP_DFE_FXTAP4_42
  • RADP_DFE_FXTAP4_43
  • RADP_DFE_FXTAP4_44
  • RADP_DFE_FXTAP4_45
  • RADP_DFE_FXTAP4_46
  • RADP_DFE_FXTAP4_47
  • RADP_DFE_FXTAP4_48
  • RADP_DFE_FXTAP4_49
  • RADP_DFE_FXTAP4_4
  • RADP_DFE_FXTAP4_50
  • RADP_DFE_FXTAP4_51
  • RADP_DFE_FXTAP4_52
  • RADP_DFE_FXTAP4_53
  • RADP_DFE_FXTAP4_54
  • RADP_DFE_FXTAP4_55
  • RADP_DFE_FXTAP4_56
  • RADP_DFE_FXTAP4_57
  • RADP_DFE_FXTAP4_58
  • RADP_DFE_FXTAP4_59
  • RADP_DFE_FXTAP4_5
  • RADP_DFE_FXTAP4_60
  • RADP_DFE_FXTAP4_61
  • RADP_DFE_FXTAP4_62
  • RADP_DFE_FXTAP4_63
  • RADP_DFE_FXTAP4_6
  • RADP_DFE_FXTAP4_7
  • RADP_DFE_FXTAP4_8
  • RADP_DFE_FXTAP4_9
  • RADP_DFE_FXTAP4_SGN_0
  • RADP_DFE_FXTAP4_SGN_1
  • RADP_DFE_FXTAP5_0
  • RADP_DFE_FXTAP5_10
  • RADP_DFE_FXTAP5_11
  • RADP_DFE_FXTAP5_12
  • RADP_DFE_FXTAP5_13
  • RADP_DFE_FXTAP5_14
  • RADP_DFE_FXTAP5_15
  • RADP_DFE_FXTAP5_16
  • RADP_DFE_FXTAP5_17
  • RADP_DFE_FXTAP5_18
  • RADP_DFE_FXTAP5_19
  • RADP_DFE_FXTAP5_1
  • RADP_DFE_FXTAP5_20
  • RADP_DFE_FXTAP5_21
  • RADP_DFE_FXTAP5_22
  • RADP_DFE_FXTAP5_23
  • RADP_DFE_FXTAP5_24
  • RADP_DFE_FXTAP5_25
  • RADP_DFE_FXTAP5_26
  • RADP_DFE_FXTAP5_27
  • RADP_DFE_FXTAP5_28
  • RADP_DFE_FXTAP5_29
  • RADP_DFE_FXTAP5_2
  • RADP_DFE_FXTAP5_30
  • RADP_DFE_FXTAP5_31
  • RADP_DFE_FXTAP5_32
  • RADP_DFE_FXTAP5_33
  • RADP_DFE_FXTAP5_34
  • RADP_DFE_FXTAP5_35
  • RADP_DFE_FXTAP5_36
  • RADP_DFE_FXTAP5_37
  • RADP_DFE_FXTAP5_38
  • RADP_DFE_FXTAP5_39
  • RADP_DFE_FXTAP5_3
  • RADP_DFE_FXTAP5_40
  • RADP_DFE_FXTAP5_41
  • RADP_DFE_FXTAP5_42
  • RADP_DFE_FXTAP5_43
  • RADP_DFE_FXTAP5_44
  • RADP_DFE_FXTAP5_45
  • RADP_DFE_FXTAP5_46
  • RADP_DFE_FXTAP5_47
  • RADP_DFE_FXTAP5_48
  • RADP_DFE_FXTAP5_49
  • RADP_DFE_FXTAP5_4
  • RADP_DFE_FXTAP5_50
  • RADP_DFE_FXTAP5_51
  • RADP_DFE_FXTAP5_52
  • RADP_DFE_FXTAP5_53
  • RADP_DFE_FXTAP5_54
  • RADP_DFE_FXTAP5_55
  • RADP_DFE_FXTAP5_56
  • RADP_DFE_FXTAP5_57
  • RADP_DFE_FXTAP5_58
  • RADP_DFE_FXTAP5_59
  • RADP_DFE_FXTAP5_5
  • RADP_DFE_FXTAP5_60
  • RADP_DFE_FXTAP5_61
  • RADP_DFE_FXTAP5_62
  • RADP_DFE_FXTAP5_63
  • RADP_DFE_FXTAP5_6
  • RADP_DFE_FXTAP5_7
  • RADP_DFE_FXTAP5_8
  • RADP_DFE_FXTAP5_9
  • RADP_DFE_FXTAP5_SGN_0
  • RADP_DFE_FXTAP5_SGN_1
  • RADP_DFE_FXTAP6_0
  • RADP_DFE_FXTAP6_10
  • RADP_DFE_FXTAP6_11
  • RADP_DFE_FXTAP6_12
  • RADP_DFE_FXTAP6_13
  • RADP_DFE_FXTAP6_14
  • RADP_DFE_FXTAP6_15
  • RADP_DFE_FXTAP6_16
  • RADP_DFE_FXTAP6_17
  • RADP_DFE_FXTAP6_18
  • RADP_DFE_FXTAP6_19
  • RADP_DFE_FXTAP6_1
  • RADP_DFE_FXTAP6_20
  • RADP_DFE_FXTAP6_21
  • RADP_DFE_FXTAP6_22
  • RADP_DFE_FXTAP6_23
  • RADP_DFE_FXTAP6_24
  • RADP_DFE_FXTAP6_25
  • RADP_DFE_FXTAP6_26
  • RADP_DFE_FXTAP6_27
  • RADP_DFE_FXTAP6_28
  • RADP_DFE_FXTAP6_29
  • RADP_DFE_FXTAP6_2
  • RADP_DFE_FXTAP6_30
  • RADP_DFE_FXTAP6_31
  • RADP_DFE_FXTAP6_3
  • RADP_DFE_FXTAP6_4
  • RADP_DFE_FXTAP6_5
  • RADP_DFE_FXTAP6_6
  • RADP_DFE_FXTAP6_7
  • RADP_DFE_FXTAP6_8
  • RADP_DFE_FXTAP6_9
  • RADP_DFE_FXTAP6_SGN_0
  • RADP_DFE_FXTAP6_SGN_1
  • RADP_DFE_FXTAP7_0
  • RADP_DFE_FXTAP7_10
  • RADP_DFE_FXTAP7_11
  • RADP_DFE_FXTAP7_12
  • RADP_DFE_FXTAP7_13
  • RADP_DFE_FXTAP7_14
  • RADP_DFE_FXTAP7_15
  • RADP_DFE_FXTAP7_16
  • RADP_DFE_FXTAP7_17
  • RADP_DFE_FXTAP7_18
  • RADP_DFE_FXTAP7_19
  • RADP_DFE_FXTAP7_1
  • RADP_DFE_FXTAP7_20
  • RADP_DFE_FXTAP7_21
  • RADP_DFE_FXTAP7_22
  • RADP_DFE_FXTAP7_23
  • RADP_DFE_FXTAP7_24
  • RADP_DFE_FXTAP7_25
  • RADP_DFE_FXTAP7_26
  • RADP_DFE_FXTAP7_27
  • RADP_DFE_FXTAP7_28
  • RADP_DFE_FXTAP7_29
  • RADP_DFE_FXTAP7_2
  • RADP_DFE_FXTAP7_30
  • RADP_DFE_FXTAP7_31
  • RADP_DFE_FXTAP7_3
  • RADP_DFE_FXTAP7_4
  • RADP_DFE_FXTAP7_5
  • RADP_DFE_FXTAP7_6
  • RADP_DFE_FXTAP7_7
  • RADP_DFE_FXTAP7_8
  • RADP_DFE_FXTAP7_9
  • RADP_DFE_FXTAP7_SGN_0
  • RADP_DFE_FXTAP7_SGN_1
  • RADP_DFE_FXTAP8_0
  • RADP_DFE_FXTAP8_10
  • RADP_DFE_FXTAP8_11
  • RADP_DFE_FXTAP8_12
  • RADP_DFE_FXTAP8_13
  • RADP_DFE_FXTAP8_14
  • RADP_DFE_FXTAP8_15
  • RADP_DFE_FXTAP8_16
  • RADP_DFE_FXTAP8_17
  • RADP_DFE_FXTAP8_18
  • RADP_DFE_FXTAP8_19
  • RADP_DFE_FXTAP8_1
  • RADP_DFE_FXTAP8_20
  • RADP_DFE_FXTAP8_21
  • RADP_DFE_FXTAP8_22
  • RADP_DFE_FXTAP8_23
  • RADP_DFE_FXTAP8_24
  • RADP_DFE_FXTAP8_25
  • RADP_DFE_FXTAP8_26
  • RADP_DFE_FXTAP8_27
  • RADP_DFE_FXTAP8_28
  • RADP_DFE_FXTAP8_29
  • RADP_DFE_FXTAP8_2
  • RADP_DFE_FXTAP8_30
  • RADP_DFE_FXTAP8_31
  • RADP_DFE_FXTAP8_32
  • RADP_DFE_FXTAP8_33
  • RADP_DFE_FXTAP8_34
  • RADP_DFE_FXTAP8_35
  • RADP_DFE_FXTAP8_36
  • RADP_DFE_FXTAP8_37
  • RADP_DFE_FXTAP8_38
  • RADP_DFE_FXTAP8_39
  • RADP_DFE_FXTAP8_3
  • RADP_DFE_FXTAP8_40
  • RADP_DFE_FXTAP8_41
  • RADP_DFE_FXTAP8_42
  • RADP_DFE_FXTAP8_43
  • RADP_DFE_FXTAP8_44
  • RADP_DFE_FXTAP8_45
  • RADP_DFE_FXTAP8_46
  • RADP_DFE_FXTAP8_47
  • RADP_DFE_FXTAP8_48
  • RADP_DFE_FXTAP8_49
  • RADP_DFE_FXTAP8_4
  • RADP_DFE_FXTAP8_50
  • RADP_DFE_FXTAP8_51
  • RADP_DFE_FXTAP8_52
  • RADP_DFE_FXTAP8_53
  • RADP_DFE_FXTAP8_54
  • RADP_DFE_FXTAP8_55
  • RADP_DFE_FXTAP8_56
  • RADP_DFE_FXTAP8_57
  • RADP_DFE_FXTAP8_58
  • RADP_DFE_FXTAP8_59
  • RADP_DFE_FXTAP8_5
  • RADP_DFE_FXTAP8_60
  • RADP_DFE_FXTAP8_61
  • RADP_DFE_FXTAP8_62
  • RADP_DFE_FXTAP8_63
  • RADP_DFE_FXTAP8_6
  • RADP_DFE_FXTAP8_7
  • RADP_DFE_FXTAP8_8
  • RADP_DFE_FXTAP8_9
  • RADP_DFE_FXTAP8_SGN_0
  • RADP_DFE_FXTAP8_SGN_1
  • RADP_DFE_FXTAP9_0
  • RADP_DFE_FXTAP9_10
  • RADP_DFE_FXTAP9_11
  • RADP_DFE_FXTAP9_12
  • RADP_DFE_FXTAP9_13
  • RADP_DFE_FXTAP9_14
  • RADP_DFE_FXTAP9_15
  • RADP_DFE_FXTAP9_16
  • RADP_DFE_FXTAP9_17
  • RADP_DFE_FXTAP9_18
  • RADP_DFE_FXTAP9_19
  • RADP_DFE_FXTAP9_1
  • RADP_DFE_FXTAP9_20
  • RADP_DFE_FXTAP9_21
  • RADP_DFE_FXTAP9_22
  • RADP_DFE_FXTAP9_23
  • RADP_DFE_FXTAP9_24
  • RADP_DFE_FXTAP9_25
  • RADP_DFE_FXTAP9_26
  • RADP_DFE_FXTAP9_27
  • RADP_DFE_FXTAP9_28
  • RADP_DFE_FXTAP9_29
  • RADP_DFE_FXTAP9_2
  • RADP_DFE_FXTAP9_30
  • RADP_DFE_FXTAP9_31
  • RADP_DFE_FXTAP9_32
  • RADP_DFE_FXTAP9_33
  • RADP_DFE_FXTAP9_34
  • RADP_DFE_FXTAP9_35
  • RADP_DFE_FXTAP9_36
  • RADP_DFE_FXTAP9_37
  • RADP_DFE_FXTAP9_38
  • RADP_DFE_FXTAP9_39
  • RADP_DFE_FXTAP9_3
  • RADP_DFE_FXTAP9_40
  • RADP_DFE_FXTAP9_41
  • RADP_DFE_FXTAP9_42
  • RADP_DFE_FXTAP9_43
  • RADP_DFE_FXTAP9_44
  • RADP_DFE_FXTAP9_45
  • RADP_DFE_FXTAP9_46
  • RADP_DFE_FXTAP9_47
  • RADP_DFE_FXTAP9_48
  • RADP_DFE_FXTAP9_49
  • RADP_DFE_FXTAP9_4
  • RADP_DFE_FXTAP9_50
  • RADP_DFE_FXTAP9_51
  • RADP_DFE_FXTAP9_52
  • RADP_DFE_FXTAP9_53
  • RADP_DFE_FXTAP9_54
  • RADP_DFE_FXTAP9_55
  • RADP_DFE_FXTAP9_56
  • RADP_DFE_FXTAP9_57
  • RADP_DFE_FXTAP9_58
  • RADP_DFE_FXTAP9_59
  • RADP_DFE_FXTAP9_5
  • RADP_DFE_FXTAP9_60
  • RADP_DFE_FXTAP9_61
  • RADP_DFE_FXTAP9_62
  • RADP_DFE_FXTAP9_63
  • RADP_DFE_FXTAP9_6
  • RADP_DFE_FXTAP9_7
  • RADP_DFE_FXTAP9_8
  • RADP_DFE_FXTAP9_9
  • RADP_DFE_FXTAP9_SGN_0
  • RADP_DFE_FXTAP9_SGN_1
  • RADP_LFEQ_FB_SEL_0
  • RADP_LFEQ_FB_SEL_1
  • RADP_LFEQ_FB_SEL_2
  • RADP_LFEQ_FB_SEL_3
  • RADP_LFEQ_FB_SEL_4
  • RADP_LFEQ_FB_SEL_5
  • RADP_LFEQ_FB_SEL_6
  • RADP_LFEQ_FB_SEL_7
  • RADP_ONETIME_DFE_0
  • RADP_ONETIME_DFE_1
  • RADP_VGA_SEL_0
  • RADP_VGA_SEL_1
  • RADP_VGA_SEL_2
  • RADP_VGA_SEL_3
  • RADP_VGA_SEL_4
  • RADP_VGA_SEL_5
  • RADP_VGA_SEL_6
  • RADP_VGA_SEL_7
  • RADP_VREF_SEL_0
  • RADP_VREF_SEL_10
  • RADP_VREF_SEL_11
  • RADP_VREF_SEL_12
  • RADP_VREF_SEL_13
  • RADP_VREF_SEL_14
  • RADP_VREF_SEL_15
  • RADP_VREF_SEL_16
  • RADP_VREF_SEL_17
  • RADP_VREF_SEL_18
  • RADP_VREF_SEL_19
  • RADP_VREF_SEL_1
  • RADP_VREF_SEL_20
  • RADP_VREF_SEL_21
  • RADP_VREF_SEL_22
  • RADP_VREF_SEL_23
  • RADP_VREF_SEL_24
  • RADP_VREF_SEL_25
  • RADP_VREF_SEL_26
  • RADP_VREF_SEL_27
  • RADP_VREF_SEL_28
  • RADP_VREF_SEL_29
  • RADP_VREF_SEL_2
  • RADP_VREF_SEL_30
  • RADP_VREF_SEL_31
  • RADP_VREF_SEL_3
  • RADP_VREF_SEL_4
  • RADP_VREF_SEL_5
  • RADP_VREF_SEL_6
  • RADP_VREF_SEL_7
  • RADP_VREF_SEL_8
  • RADP_VREF_SEL_9
  • RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
  • RAM_CTL
  • RAM_REGISTER_DUPLICATION
  • RAMSTYLE_ATTRIBUTE
  • RAM_USE_DCD
  • RANDOM
  • RANDOM_PIN
  • RANDOM_PIN_SEED
  • RAPID_RECOMPILE_ASSIGNMENT_CHECKING
  • RAPID_RECOMPILE_MODE
  • RAPID_RECOMPILE_SYNTHESIS_MODE
  • RAW_BINARY_FILE
  • RBCGEN_CRITICAL_WARNING_TO_ERROR
  • RBF_FILE_GENERATION_FOR_SUPR
  • RDYNBUSY_RESERVED
  • READ
  • READ_OR_WRITE_IN_BYTE_ADDRESS
  • REALISTIC
  • RECOMMENDED
  • RECOMPILE_QUESTION
  • RECONFIGURABLE
  • RECONFIGURABLE_REVISION
  • REFCLK_COUNTER_OUT
  • REFCLK_COUPLING_OCT
  • REGENERATE_IP_IF_HDL_QSYS_MISMATCH
  • REGIONAL_CLOCK
  • REGION_NAME
  • REGISTER_LOCATION_TYPE
  • REGISTER_PACKING_ARMSTRONG
  • REGISTER_PACKING
  • REGISTER_PACKING_TSUNAMI
  • REGISTERS_ONLY
  • RELATIVE_NEUTRON_FLUX
  • RELEASE_CLEARS_BEFORE_TRI
  • RELEASE_CLEARS_BEFORE_TRI_STATES
  • REMOTE
  • REMOVE_DUPLICATE_LOGIC
  • REMOVE_DUPLICATE_REGISTERS
  • REMOVE_FANOUT_FREE_REGISTERS
  • REMOVE
  • REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS
  • REMOVE_REDUNDANT_LOGIC_CELLS
  • REMOVE_REDUNDANT_USER_CELLS
  • REPLACE_CONFLICTING
  • REPORT_AS_DQS
  • REPORT_CONNECTIVITY_CHECKS
  • REPORT_DELAY
  • REPORT_IO_PATHS_SEPARATELY
  • REPORT_PARAMETER_SETTINGS
  • REPORT_PARAMETER_SETTINGS_PRO
  • REPORT_PR_INITIAL_VALUES_AS_ERROR
  • REPORT_SOURCE_ASSIGNMENTS
  • REPORT_SOURCE_ASSIGNMENTS_PRO
  • REQUIRED_DUTY_CYCLE
  • REQUIRED_FMAX
  • RESERVE_ALL_UNUSED_PINS
  • RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND
  • RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP
  • RESERVE_ASDO_AFTER_CONFIGURATION
  • RESERVE_AVST_CLK_AFTER_CONFIGURATION
  • RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION
  • RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
  • RESERVE_AVST_VALID_AFTER_CONFIGURATION
  • RESERVED1
  • RESERVED2
  • RESERVED3
  • RESERVED_ALL_UNUSED_PINS
  • RESERVED_ALL_UNUSED_PINS_NO_OUTPUT_GND
  • RESERVE_DATA0_AFTER_CONFIGURATION
  • RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION
  • RESERVE_DATA1_AFTER_CONFIGURATION
  • RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION
  • RESERVE_DCLK_AFTER_CONFIGURATION
  • RESERVED_CORE
  • RESERVED
  • RESERVED_PIN
  • RESERVE_FLASH_NCE_AFTER_CONFIGURATION
  • RESERVE_FLEXIBLE_CLOCK_NETWORK
  • RESERVE_NCEO_AFTER_CONFIGURATION
  • RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION
  • RESERVE_OTHER_APF_PINS_AFTER_CONFIGURATION
  • RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION
  • RESERVE_PIN
  • RESERVE_PLACE_REGION
  • RESERVE_PR_PINS
  • RESERVE_RDYNBUSY_AFTER_CONFIGURATION
  • RESERVE_ROUTE_REGION
  • RESERVE_ROUTING_OUTPUT_FLEXIBILITY
  • RESERVE_SDO_AFTER_CONFIGURATION
  • RESET_CAT
  • RESET_RULE_ALL
  • RESET_RULE_COMB_ASYNCH_RESET
  • RESET_RULE_IMSYNCH_ASYNCH_DOMAIN
  • RESET_RULE_IMSYNCH_EXRESET
  • RESET_RULE_INPINS_RESETNET
  • RESET_RULE_REG_ASNYCH
  • RESET_RULE_UNSYNCH_ASYNCH_DOMAIN
  • RESET_RULE_UNSYNCH_EXRESET
  • RESOLVE_FILENAME
  • RESOURCE_ALLOCATION
  • RESYNTHESIS_EXTRA_DEBUGGING_INFORMATION
  • RESYNTHESIS_OPTIMIZATION_EFFORT
  • RESYNTHESIS_PHYSICAL_SYNTHESIS
  • RESYNTHESIS_RETIMING
  • RETAIN_COMB_LOGIC_OUTSIDE_CLOUD
  • RETIMER_ASSIGNMENT
  • RETIMER_FAST_FORWARD_ASSIGNMENT
  • REVISION_BASED_FILE_NAME
  • REVISION_CONTROL_DIR
  • REVISION_CONTROL_SYSTEM
  • REVISION_CONTROL_TCL
  • REVISION_CONTROL_TCL_SCRIPT
  • REVISION_TYPE
  • R_EXT0
  • RISE
  • ROOT
  • ROUTER_CLOCKING_TOPOLOGY_ANALYSIS
  • ROUTER_EFFORT_MULTIPLIER
  • ROUTE_REGION
  • ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION
  • ROUTER_REGISTER_DUPLICATION
  • ROUTER_TIMING_OPTIMIZATION_LEVEL
  • ROUTING_BACK_ANNOTATE
  • ROUTING_BACK_ANNOTATION_FILE
  • ROUTING_BACK_ANNOTATION_MODE
  • ROW_GLOBAL
  • ROW_GLOBAL_SIGNAL
  • R_R1
  • R_R2
  • RR_HYBRID
  • RTERM_CODE0
  • RTERM_CODE10
  • RTERM_CODE11
  • RTERM_CODE12
  • RTERM_CODE13
  • RTERM_CODE14
  • RTERM_CODE15
  • RTERM_CODE1
  • RTERM_CODE2
  • RTERM_CODE3
  • RTERM_CODE4
  • RTERM_CODE5
  • RTERM_CODE6
  • RTERM_CODE7
  • RTERM_CODE8
  • RTERM_CODE9
  • RTLV_GROUP_COMB_LOGIC_IN_CLOUD
  • RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV
  • RTLV_GROUP_RELATED_NODES
  • RTLV_GROUP_RELATED_NODES_TMV
  • RTLV_PRESERVED_HANGING_NODES
  • RTLV_REMOVE_FANOUT_FREE_REGISTERS
  • RTLV_RETAIN_COMB_LOGIC_OUTSIDE_CLOUD
  • RTLV_SIMPLIFIED_LOGIC
  • RUN_ALL_TIMING_ANALYSES
  • RUN_CLOCK_TAN
  • RUN_COMPARISON_ON_EVERY_COMPILE
  • RUN_DRC_DURING_COMPILATION
  • RUN_FITTER_IN_SIGNALPROBE_MODE
  • RUN_FULL_COMPILE_ON_DEVICE_CHANGE
  • RUN_P2P_TAN
  • RUN_TAN
  • RUN_TIMING_ANALYSES
  • RUN_TIMING_ANALYSES_ONLY_FOR_TIMING_ASSIGNMENTS
  • RX_DET_OFF
  • RX_DET_ON
  • RX_DET_PCIE_OUT
  • RX_DET_QPI_OUT
  • RZQ_GROUP
  • S0H9
  • S1_MODE
  • SAFE_STATE_MACHINE
  • SAME_AS_MULTICYCLE
  • SAMPLE_AND_SUSTAIN
  • SAP_NAME
  • SATA1_I
  • SATA1_M
  • SATA1_X
  • SATA2_I
  • SATA2_M
  • SATA2_X
  • SAVE_DISK_SPACE
  • SAVE_INTERMEDIATE_FITTING_RESULTS
  • SAVE_MIGRATION_INFO_DURING_COMPILATION
  • SBI_FILE
  • SCE_PIN
  • SDC_ENTITY_FILE
  • SDC_ENTITY_HELPER_FILE
  • SDC_FILE
  • SDC_STATEMENT
  • SDC_UNIQUIFIED_STATEMENT
  • SDF_OUTPUT_FILE
  • SDI_1485_HD
  • SDI_270_SD
  • SDI_2970_3G
  • SDLV_0
  • SDLV_10
  • SDLV_11
  • SDLV_12
  • SDLV_13
  • SDLV_14
  • SDLV_15
  • SDLV_1
  • SDLV_2
  • SDLV_3
  • SDLV_4
  • SDLV_5
  • SDLV_6
  • SDLV_7
  • SDLV_8
  • SDLV_9
  • SDM_DIRECT_TO_FACTORY_IMAGE
  • SDM_PCIE_CALIB_START
  • SDM_PINS
  • SDO_PIN
  • SDO_RESERVED
  • SEARCH_PATH
  • SECTION_COLUMN
  • SECTION
  • SECURITY_BIT
  • SEED
  • SELECTED_EDGE
  • SEQUENTIAL
  • SERIAL_BITSTREAM_FILE
  • SERIAL_LITE_III_16400
  • SERIAL_LITE_III_17400
  • SERIAL_VECTOR_FILE
  • SERIES_25_OHMS
  • SERIES_25_OHMS_WITH_CALIBRATION
  • SERIES_25_OHMS_WITHOUT_CALIBRATION
  • SERIES_50_OHMS
  • SERIES_50_OHMS_WITH_CALIBRATION
  • SERIES_50_OHMS_WITHOUT_CALIBRATION
  • SERIES
  • SET_PULSE_WIDTH
  • SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
  • SETUP_HOLD_DETECTION
  • SETUP_HOLD_TIME_VIOLATION_DETECTION
  • SETUP_RELATIONSHIP
  • SEU_FIT_REPORT
  • SFCU
  • SFI_S_6250
  • SFIS
  • SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL
  • SHOW_ALL_TAN_PANELS
  • SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT
  • SHOW_REGISTRATION_MESSAGE
  • SHOW_TIMING_MODEL_CHANGE_MESSAGE
  • SIGNAL_INTEGRITY_ASSIGNMENT
  • SIGNAL_INTEGRITY_WILDCARDS
  • SIGNALPROBE_ALLOW_OVERUSE
  • SIGNALPROBE_ASSIGNMENT
  • SIGNALPROBE_CLOCK
  • SIGNALPROBE_DURING_NORMAL_COMPILATION
  • SIGNAL_PROBE_ENABLE
  • SIGNALPROBE_ENABLE
  • SIGNALPROBE
  • SIGNALPROBE_NUM_REGISTERS
  • SIGNAL_PROBE_SOURCE
  • SIGNALPROBE_SOURCE
  • SIGNALRACE_CAT
  • SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN
  • SIGNALRACE_RULE_CLK_PORT_RACE
  • SIGNALRACE_RULE_RESET_RACE
  • SIGNALRACE_RULE_SECOND_SIGNAL_RACE
  • SIGNALRACE_RULE_TRISTATE
  • SIGNALTAP_ASSIGNMENTS
  • SIGNALTAP_FILE
  • SIGNALTAP
  • SIGNALTAP_LOGIC_ANALYZER_PROJECT_FILES
  • SIGNALTAP_LOGIC_ANALYZER_SETTINGS
  • SIM_AUTO_USE_GLITCH_FILTERING
  • SIM_BEHAVIOR_SIMULATION
  • SIM_BUS_CHANNEL_GROUPING
  • SIM_CELL_DELAY_MODEL_TYPE
  • SIM_COMPARE_SIGNAL
  • SIM_COMPILE_HDL_FILES
  • SIM_DEFAULT_VECTOR_COMPARE_TOLERANCE
  • SIM_DELAY_MODEL_TYPE
  • SIM_ENABLE_SIMULATION_NETLIST_VIEWER
  • SIMGEN_ARBITRARY_BLACKBOX
  • SIMGEN_BLACKBOX_FILE
  • SIMGEN_PARAMETER
  • SIM_HDL_TOP_MODULE_NAME
  • SIM_INTERCONNECT_DELAY_MODEL_TYPE
  • SIM_NO_DELAYS
  • SIM_OUTPUT_POWERPLAY_VCD
  • SIM_OUTPUT_POWERPLAY_VCD_NAME
  • SIM_OUTPUT_SAF
  • SIM_OUTPUT_SAF_NAME
  • SIM_OVERWRITE_WAVEFORM_INPUTS
  • SIMPLE_18_BIT_MULTIPLIERS
  • SIMPLE_MULTIPLIERS
  • SIMPLE_MULT
  • SIMPLE_MULT_UPGRADE_WIDTH
  • SIMPLIFIED_LOGIC
  • SIM_POWERPLAY_VCD_END_TIME
  • SIM_POWERPLAY_VCD_START_TIME
  • SIM_PVT_TIMING_MODEL_TYPE
  • SIM_SET_NO_DELAYS_VIRTUAL_IO
  • SIM_SIGNAL_ACTIVITY_END_TIME
  • SIM_SIGNAL_ACTIVITY_START_TIME
  • SIM_SIGNAL_COMPARE_TOLERANCE
  • SIM_SIGNAL_TRIGGER_VECTOR_COMPARE
  • SIM_SIMULATION_DEBUGGER
  • SIM_TAP_REGISTER_D_Q_PORTS
  • SIMULATION_ASSIGNMENT
  • SIMULATION_BUS_CHANNEL_GROUPING
  • SIMULATION_CELL_DELAY_MODEL_TYPE
  • SIMULATION_COMPARE_SIGNAL
  • SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL
  • SIMULATION_COVERAGE
  • SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE
  • SIMULATION_DELAY_MODEL_TYPE
  • SIMULATION_INCREMENTAL_TIME_INPUT
  • SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE
  • SIMULATION
  • SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL
  • SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL
  • SIMULATION_MODE
  • SIMULATION_NETLIST_VIEWER
  • SIMULATION_SIGNAL_COMPARE_TOLERANCE
  • SIMULATION_TYPE
  • SIMULATION_VDB_RESULT_FLUSH
  • SIMULATION_VECTOR_COMPARE_BEGIN_TIME
  • SIMULATION_VECTOR_COMPARE_END_TIME
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_0
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_1
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_DC
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_H
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_L
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_U
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_W
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_X
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_Z
  • SIMULATION_WITH_AUTO_GLITCH_FILTERING
  • SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW
  • SIMULATION_WITH_GLITCH_FILTERING
  • SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF
  • SIMULATOR_ACTION_POINTS
  • SIMULATOR_GENERATE_POWERPLAY_VCD_FILE
  • SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE
  • SIMULATOR_POWERPLAY_VCD_FILE_END_TIME
  • SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION
  • SIMULATOR_POWERPLAY_VCD_FILE_START_TIME
  • SIMULATOR_PVT_TIMING_MODEL_TYPE
  • SIMULATOR_SETTINGS
  • SIMULATOR_SETTINGS_LIST
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME
  • SIMULATOR_TCL_SCRIPT_FILE
  • SIM_USE_FAST_TIMING_MODEL
  • SIM_USE_GLITCH_FILTERING
  • SIM_USE_GLITCH_FILTERING_WHEN_GENERATING_SAF
  • SIM_USE_PDB_NETLIST
  • SIM_VDB_RESULT_FLUSH
  • SIM_VECTOR_COMPARE_BEGIN_TIME
  • SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE
  • SIM_VECTOR_COMPARED_CLOCK_OFFSET
  • SIM_VECTOR_COMPARED_CLOCK_PERIOD
  • SIM_VECTOR_COMPARE_END_TIME
  • SIM_VECTOR_COMPARE_RULE_FOR_0
  • SIM_VECTOR_COMPARE_RULE_FOR_1
  • SIM_VECTOR_COMPARE_RULE_FOR_DC
  • SIM_VECTOR_COMPARE_RULE_FOR_H
  • SIM_VECTOR_COMPARE_RULE_FOR_L
  • SIM_VECTOR_COMPARE_RULE_FOR_U
  • SIM_VECTOR_COMPARE_RULE_FOR_W
  • SIM_VECTOR_COMPARE_RULE_FOR_X
  • SIM_VECTOR_COMPARE_RULE_FOR_Z
  • SIM_VECTOR_COMPARE_TRIGGER_CLOCK
  • SIM_VECTOR_COMPARE_TRIGGER_MODE
  • SIM_VECTOR_COMPARE_TRIGGER_SIGNAL
  • SIM_VECTOR_OUTPUT_FILE
  • SIM_VECTOR_OUTPUT_FORMAT
  • SINGLE_COMP_IMAGE
  • SINGLE_COMP_IMAGE_WITH_ERAM
  • SINGLE_IMAGE
  • SINGLE_IMAGE_WITH_ERAM
  • SINGLE_PIN
  • SIP_FILE
  • SIZE_OF_LATCH_REPORT
  • SIZE_OF_PR_INITIAL_CONDITIONS_REPORT
  • SKIP_ATOM_SWEEPER
  • SKIP_CONFLICTING
  • SKIP_CRC_CHECK_IN_HC
  • SKIP_REGENERATING_IP_IF_HDL_MODIFIED
  • SLD_BIDIR_PIN_CONNECT_FROM_PORT
  • SLD_FABRIC_PARTITION
  • SLD_FILE
  • SLD_INCR_NODE_CREATOR_ID
  • SLD_INCR_NODE_ENTITY_NAME
  • SLD_INCR_NODE_PARAMETER_ASSIGNMENT
  • SLD_INCR_NODE_SOURCE_FILE
  • SLD_INFO
  • SLD_NODE_CONNECT_FROM_PORT
  • SLD_NODE_CONNECT_TO_PORT
  • SLD_NODE_CREATOR_ID
  • SLD_NODE_ENTITY_NAME
  • SLD_NODE_PARAMETER_ASSIGNMENT
  • SLD_NODE_SOURCE_FILE
  • SLD_PARAMETER_ASSIGNMENT
  • SLD_PARAMETER_COMPATIBILITY_STRING
  • SLD_PIN_CONNECT_FROM_PORT
  • SLD_PIN_CONNECT_TO_PORT
  • SLD_PRE_SYN_COMPATIBILITY_STRING
  • SLEW_R0
  • SLEW_R1
  • SLEW_R2
  • SLEW_R3
  • SLEW_R4
  • SLEW_R5
  • SLEW_R6
  • SLEW_R7
  • SLEW_RATE
  • SLOW_POR_DELAY
  • SLOW_SLEW_RATE
  • SMALL
  • SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES
  • SMART_RECOMPILE
  • SMF_FILE
  • SMP_PROCESS_TYPE
  • SOFT
  • SOFTWARE_ACTION_POINTS
  • SOFTWARE_LIBRARY_FILE
  • SOFTWARE_SETTINGS
  • SOFTWARE_SETTINGS_LIST
  • SONET
  • SONET_OC12_622
  • SONET_OC192_9953
  • SONET_OC3_155
  • SONET_OC48_2488
  • SOPC_BUILDER_SIGNATURE_ID
  • SOPC_FILE
  • SOPCINFO_FILE
  • SOURCE_FILE
  • SOURCE
  • SOURCE_MULTICYCLE_HOLD
  • SOURCE_MULTICYCLE
  • SOURCES_PER_DESTINATION_INCLUDE_COUNT
  • SOURCE_SYNCHRONOUS
  • SOURCE_TCL_SCRIPT_FILE
  • SOURCE_TCL_SCRIPT
  • SPARSE_AUTO
  • SPARSE
  • SPAUI_6250
  • SPD_FILE
  • SPECTRAQ_PHYSICAL_SYNTHESIS
  • SPEED_DISK_USAGE_TRADEOFF
  • SPEED
  • SRAM_OBJECT_FILE
  • SRC_HOLD_MULTICYCLE
  • SRC_MULTICYCLE
  • SRECORDS_FILE
  • SRIO_1250_LR
  • SRIO_1250_SR
  • SRIO_2500_LR
  • SRIO_2500_SR
  • SRIO_3125_LR
  • SRIO_3125_SR
  • SRIO_5000_LR
  • SRIO_5000_MR
  • SRIO_5000_SR
  • SRIO_6250_LR
  • SRIO_6250_MR
  • SRIO_6250_SR
  • SRIO
  • STA_IGNORED_EMBEDDED_SDC_STATEMENT
  • STA_MODE
  • STANDARD_DELAY_FORMAT_OUTPUT_FILE
  • STANDARD_FIT
  • STANDARD
  • STANDARD_PARTITION
  • START_TIME
  • START_UP_CLOCK
  • STATE_MACHINE_PROCESSING
  • STD_ONLY
  • STG1_GAIN7
  • STG2_GAIN7
  • STG3_GAIN7
  • STG4_GAIN7
  • STOP
  • STP_FILE
  • STP_INCREMENTAL_SOURCE
  • STP_SIGNAL_PROBE_SOURCE
  • STP_SIGNALPROBE_SOURCE
  • STP_VIRTUAL_PIN_CLK_SOURCE
  • STP_VIRTUAL_PIN
  • STRATIX_CARRY_CHAIN_LENGTH
  • STRATIX_CONFIG_DEVICE_JTAG_USER_CODE
  • STRATIX_CONFIGURATION_DEVICE
  • STRATIX_CONFIGURATION_SCHEME
  • STRATIX_CRC_ERROR_CHECKING
  • STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • STRATIX_DEVICE_IO_STANDARD
  • STRATIX_FAST_PLL_INCREASE_LOCK_WINDOW
  • STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET
  • STRATIXGX_ALLOW_DEDICATED_CLOCK_FANOUT_WITH_ANALOG_RESET
  • STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE
  • STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
  • STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B
  • STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
  • STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_POST8B10B_LOOPBACK
  • STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK
  • STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS
  • STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
  • STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
  • STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT
  • STRATIXGX_OCT_VALUE
  • STRATIXGX_TERMINATION_VALUE
  • STRATIXII_ALLOW_DUAL_PORT_DUAL_CLOCK_MRAM_USAGE
  • STRATIXII_CARRY_CHAIN_LENGTH
  • STRATIX_II_CONFIGURATION_DEVICE
  • STRATIXII_CONFIGURATION_DEVICE
  • STRATIX_II_CONFIGURATION_SCHEME
  • STRATIXII_CONFIGURATION_SCHEME
  • STRATIXII_EP2S60ES_ALLOW_MRAM_USAGE
  • STRATIXIIGX_OCT_VALUE
  • STRATIXIIGX_TERMINATION_VALUE
  • STRATIXIII_CONFIGURATION_SCHEME
  • STRATIXIII_LUTAB_SLOWDOWN
  • STRATIXIII_MRAM_COMPATIBILITY
  • STRATIXIII_OUTPUT_DUTY_CYCLE_DELAY
  • STRATIXIII_UPDATE_MODE
  • STRATIXII_MRAM_COMPATIBILITY
  • STRATIXII_OPTIMIZATION_TECHNIQUE
  • STRATIXII_OUTPUT_DUTY_CYCLE_CONTROL
  • STRATIXII_SILICON_VERSION
  • STRATIXII_TERMINATION
  • STRATIXIV_CONFIGURATION_SCHEME
  • STRATIX_JTAG_USER_CODE
  • STRATIX_OPTIMIZATION_TECHNIQUE
  • STRATIX_TECHNOLOGY_MAPPER
  • STRATIX_UPDATE_MODE
  • STRATIXV_CONFIGURATION_SCHEME
  • STRICT_POST_FIT
  • STRICT_RAM_RECOGNITION
  • STRIPE_TO_PLD_BRIDGE_EPXA4_10
  • STRIPE_TO_PLD_INTERRUPTS_EPXA4_10
  • SUBCLIQUE_OF
  • SUPERIOR_PERFORMANCE
  • SUPERIOR_PERFORMANCE_WITH_MAXIMUM_PLACEMENT_EFFORT
  • SUPPRESS_DA_RULE_INTERNAL
  • SUPPRESS_REG_MINIMIZATION_MSG
  • SVF_FILE
  • SXL9
  • SYMBOL_FILE
  • SYM_FILE
  • SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
  • SYNCHRONIZER_IDENTIFICATION
  • SYNCHRONIZER_TOGGLE_RATE
  • SYNTH_CHECK_PORT_CONNECTIONS
  • SYNTH_CLOCK_MUX_PROTECTION
  • SYNTH_CRITICAL_CLOCK
  • SYNTH_CRITICAL_CLOCK_TO_OUTPUT
  • SYNTH_CRITICAL_ENABLE
  • SYNTH_CRITICAL_INPUT_TO_CLOCK
  • SYNTH_CRITICAL_PIN
  • SYNTHESIS_EFFORT
  • SYNTHESIS_FITTING_SETTINGS
  • SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
  • SYNTHESIS_ON_ATOMS
  • SYNTHESIS_ONLY
  • SYNTHESIS_ONLY_QIP
  • SYNTHESIS_S10_MIGRATION_CHECKS
  • SYNTHESIS_SEED
  • SYNTHESIS_WILDCARDS
  • SYNTHESIZE_LATCHES_AS_HIPIS
  • SYNTH_GATED_CLOCK_CONVERSION
  • SYNTH_MESSAGE_LEVEL
  • SYNTH_PROTECT_SDC_CONSTRAINT
  • SYNTH_REPORT_SOURCE_ASSIGNMENTS
  • SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM
  • SYNTH_RPT_SHOW_PARAMS_PER_ENTITY_INSTANCE
  • SYNTH_TIMING_DRIVEN_BALANCED_MAPPING
  • SYNTH_TIMING_DRIVEN_REGISTER_DUPLICATION
  • SYNTH_TIMING_DRIVEN_SYNTHESIS
  • SYSTEMVERILOG_2005
  • SYSTEMVERILOG_2009
  • SYSTEMVERILOG_FILE
  • T10_DELAY
  • T10_FINE_DELAY
  • T10_OCT_DELAY
  • T10_OE_DELAY
  • T10_OE_FINE_DELAY
  • T11_0_DELAY
  • T11_1_DELAY
  • T11_DELAY
  • T11_FINE_DELAY
  • T1_DELAY
  • T1_FINE_DELAY
  • T2_DELAY
  • T3_DELAY
  • T4_DELAY
  • T7_DELAY
  • T7_FINE_DELAY
  • T8_DELAY0
  • T8_DELAY1
  • T9_DELAY
  • T9_FINE_DELAY
  • T9_OCT_DELAY
  • T9_OE_DELAY
  • TAN_SCRIPT_FILE
  • TAO_FILE
  • TAO_FILE_NAME
  • TBFF_PULSE_WIDTH
  • TCL_ENTITY_FILE
  • TCL_FILE
  • TCL_SCRIPT_FILE
  • TCO_REQUIREMENT
  • TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT
  • TDC_CCPP_TRADEOFF_TOLERANCE
  • TDO_DUMP_FILE
  • TECH_MAPPER_APEX20K
  • TECH_MAPPER_DALI
  • TECH_MAPPER_FLEX10K
  • TECH_MAPPER_FLEX6K
  • TECH_MAPPER
  • TECH_MAPPER_MAX7000
  • TECH_MAPPER_YEAGER
  • TECHNOLOGY_MAPPER_DALI
  • TECHNOLOGY_MAPPER_FLEX6K
  • TECHNOLOGY_MAPPER
  • TEMPLATE_FILE
  • TENG_1588
  • TENG_BASER
  • TENG_KR_10312
  • TENG_SDI
  • TERMINATION_CONTROL_BLOCK
  • TERMINATION
  • TEST_BENCH_MODE
  • TESTING_BOOL
  • TESTING_ENUM
  • TESTING_FILE
  • TESTING_INT_GLOBAL_DISALLOWED_IN_QIP
  • TESTING_INT
  • TESTING_SINGLE_ABSOLUTE_NODE_ENTITY_INT
  • TESTING_SINGLE_BOOL
  • TESTING_SINGLE_ENUM
  • TESTING_SINGLE_INT
  • TESTING_SINGLE_RELATIVE_BOOL
  • TESTING_SINGLE_RELATIVE_ENTITY_INT
  • TESTING_SINGLE_RELATIVE_NODE_ENTITY_BOOL
  • TESTING_SINGLE_RELATIVE_NODE_ENTITY_INT
  • TESTING_SINGLE_RELATIVE_NODE_INT
  • TESTING_SINGLE_STRING
  • TESTING_STRING
  • TEXT_FILE
  • TEXT_FORMAT_REPORT_FILE
  • THIRD_PARTY_EDA_TOOLS
  • THREE
  • TH_REQUIREMENT
  • THR_THREAD_MAIN_ID
  • TIMEGROUP_EXCEPTION
  • TIMEGROUP_MEMBER
  • TIMEQUEST2
  • TIMEQUEST_CCPP_TRADEOFF_TOLERANCE
  • TIMEQUEST_DO_CCPP_REMOVAL
  • TIMEQUEST_DO_REPORT_CDC_VIEWER
  • TIMEQUEST_DO_REPORT_TIMING
  • TIMEQUEST_MULTICORNER_ANALYSIS
  • TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS
  • TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
  • TIMEQUEST_REPORT_SCRIPT
  • TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS
  • TIMEQUEST_SIMULTANEOUS_MULTICORNER_ANALYSIS
  • TIMEQUEST_SPECTRA_Q
  • TIMING_ANALYSIS_OUTPUT_FILE
  • TIMING_ANALYZER_CCPP_TRADEOFF_TOLERANCE
  • TIMING_ANALYZER_DO_CCPP_REMOVAL
  • TIMING_ANALYZER_DO_REPORT_CDC_VIEWER
  • TIMING_ANALYZER_DO_REPORT_TIMING
  • TIMING_ANALYZER_MULTICORNER_ANALYSIS
  • TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS
  • TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
  • TIMING_ANALYZER_REPORT_SCRIPT
  • TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS
  • TIMING_ANALYZER_SIMULTANEOUS_MULTICORNER_ANALYSIS
  • TIMING_ASSIGNMENT
  • TIMING_CAT
  • TIMING_DERATING_FILE
  • TIMING_DRIVEN_COMPILE
  • TIMING
  • TIMING_REQUIREMENTS
  • TIMING_RULE_COIN_CLKEDGE
  • TIMING_RULE_HIGH_FANOUTS
  • TIMING_RULE_SHIFT_REG
  • TIMING_USING_FAST_TIMING_MODEL
  • TOGGLE_RATE
  • TOOLSET
  • TOP_LEVEL_ENTITY
  • TOP_PARTITION_PIN
  • TPD_REQUIREMENT
  • TRANSPORT
  • TREAT_BIDIR_AS_OUTPUT
  • TRI_CONVERTED_FROM_DIRECTIONAL_BUFFER
  • TRIGGER_EQUATION
  • TRIGGER_VECTOR_COMPARE_ON_SIGNAL
  • TRISTATE1
  • TRISTATED1
  • TRI_STATE
  • TRISTATE
  • TRISTATE_OFF
  • TRISTATE_ON
  • TRI_STATE_SPI_PINS
  • TRUE
  • TRUE_WYSIWYG_FLOW
  • TSUNAMI_OPTIMIZATION_TECHNIQUE
  • TSU_REQUIREMENT
  • TURBO_BIT
  • TXPMA_SLEW_RATE
  • TYPICAL
  • U0H9
  • UC_DCD_CAL_OFF
  • UC_DCD_CAL_ON
  • UC_RO_CAL_OFF
  • UC_RO_CAL_ON
  • UC_RX_DFE_CAL_OFF
  • UC_RX_DFE_CAL_ON
  • UC_SKEW_CAL_OFF
  • UC_SKEW_CAL_ON
  • UC_TX_VOD_CAL_CONT_OFF
  • UC_TX_VOD_CAL_CONT_ON
  • UC_TX_VOD_CAL_OFF
  • UC_TX_VOD_CAL_ON
  • UI_DEFAULT_ASSEMBLER_SETTING
  • UI_DEFAULT_COMP_PROCESS_SETTING
  • UI_DEFAULT_EDA_NATIVELINK_SETTING
  • UI_DEFAULT_EDA_SIMULATION_SETTING
  • UI_DEFAULT_FITTER_SETTING
  • UI_DEFAULT_HYPERFLEX_SETTING
  • UI_DEFAULT_OPTIMIZATION_SETTING
  • UI_DEFAULT_SIMULATOR_SETTING
  • UI_DEFAULT_SYNTHESIS_SETTING
  • UI_DEFAULT_TIMING_SETTING
  • UNFORCE_MERGE_PLL
  • UNFORCE_MERGE_PLL_OUTPUT_COUNTER
  • UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE
  • UNIPHY_TEMP_VER_CODE
  • UNNAMED_POOL
  • UNSECURED
  • UNUSED_RXCLK_BTI_MITIGATION
  • UNUSED_RXTXCLK_BTI_MITIGATION
  • UNUSED_TSD_PINS_GND
  • UPCORE_TRANSACTION_MODEL_FILE
  • UPDATE_ASE_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_ASSIGNMENT_GROUP_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_CHIP_EDITOR_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_CONFLICTING
  • UPDATE_ECMC_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_FLOORPLAN_EDITOR_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_MODE_INTERNAL_FLASH
  • UPDATE_MODE_TITAN
  • UPDATE_MODE_YEAGER
  • UPDATE_PAT_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_PIN_PLANNER_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_SIM_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_SSN_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_TAN_FEATURE_TIME_WHEN_CHANGED
  • UPGRADE_WIDTH
  • USE_ADVANCED_DETAILED_LAB_LEGALITY
  • USE_AS_3V_GPIO
  • USE_AS_PROGRAMMING_PIN
  • USE_AS_REGULAR_IO
  • USE_CAP
  • USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT
  • USE_CHECKSUM_AS_USERCODE
  • USE_CHECKSUM_AS_USERCODE_MAX7000
  • USE_CLK_FOR_VIRTUAL_PIN
  • USE_CLOCK
  • USE_CLOCK_SETTINGS
  • USE_COMPILER_SETTINGS
  • USE_CONF_DONE
  • USE_CONFIGURATION_DEVICE
  • USE_CONFIGURATION_DEVICE_NAME_APEX20K
  • USE_CONFIGURATION_DEVICE_NAME_ARMSTRONG
  • USE_CONFIGURATION_DEVICE_NAME_CUDA
  • USE_CONFIGURATION_DEVICE_NAME_CYCLONE
  • USE_CONFIGURATION_DEVICE_NAME_DALI
  • USE_CONFIGURATION_DEVICE_NAME_EXCALIBUR
  • USE_CONFIGURATION_DEVICE_NAME_FLEX10K
  • USE_CONFIGURATION_DEVICE_NAME_FLEX6K
  • USE_CONFIGURATION_DEVICE_NAME
  • USE_CONFIGURATION_DEVICE_NAME_YEAGER
  • USE_CONFIGURATION_DEVICE_OPTIONS
  • USE_C_PREPROCESSOR_FOR_GNU_ASM_FILES
  • USE_CVP_CONFDONE
  • USE_DATA_UNLOCK
  • USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
  • USE_DMF
  • USE_GENERATED_PHYSICAL_CONSTRAINTS
  • USE_GLOBAL_SETTINGS
  • USE_HIGH_SPEED_ADDER
  • USE_HPS_COLD_RESET
  • USE_HPS_WARM_RESET
  • USE_INIT_DONE
  • USE_LOCAL_APEX20K
  • USE_LOCAL_FLEX6K
  • USE_LOCAL
  • USE_LOGIC_ANALYZER_INTERFACE_FILE
  • USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
  • USE_LPM_FOR_AHDL_OPERATORS
  • USE_MULTITAP_FILE
  • USE_NEW_TEXT_REPORT_TABLE_FORMAT
  • USE_PWRMGT_ALERT
  • USE_PWRMGT_PWM0
  • USE_PWRMGT_SCL
  • USE_PWRMGT_SDA
  • USER_CUSTOM
  • USER_ENABLED
  • USER_ENCODED
  • USER_FILES_NEW_EXTRACTOR
  • USER_JTAG_CODE_APEX20K
  • USER_JTAG_CODE_DALI
  • USER_JTAG_CODE_FLEX10K
  • USER_JTAG_CODE_FLEX6K
  • USER_JTAG_CODE
  • USER_JTAG_CODE_MAX7000
  • USER_JTAG_CODE_MAX7000S
  • USER_JTAG_CODE_YEAGER
  • USER_LIBRARIES
  • USER_MESSAGE
  • USER_START_UP_CLOCK
  • USER_VALUE
  • USE_SEU_ERROR
  • USE_SIGNALTAP_FILE
  • USE_TCL_PROC
  • USE_TIMEQUEST_TIMING_ANALYZER
  • USE_TIMING_DRIVEN_COMPILATION
  • USE_UIB_CATTRIP
  • USE_VPACK
  • USE_VPR
  • USE_VQM_INSTEAD_OF_SOURCE
  • V0P00
  • V0P58
  • V0P64
  • V0P67
  • V0P70
  • V0P75
  • V0P81
  • V0P86
  • V0P87
  • V0P93
  • V0P96
  • V1P00
  • V1P04
  • V1P13
  • V1P22
  • V1P30
  • V1P39
  • VALUE_IS_NODE
  • VARIABLE_VALUE_CANNOT_BE_CHANGED
  • VCCA_FPLL_USER_VOLTAGE
  • VCCA_GTBR_USER_VOLTAGE
  • VCCA_GTB_USER_VOLTAGE
  • VCCA_GXBL_USER_VOLTAGE
  • VCCA_GXBR_USER_VOLTAGE
  • VCCA_GXB_USER_VOLTAGE
  • VCCA_L_USER_VOLTAGE
  • VCCA_PLL_USER_VOLTAGE
  • VCCA_R_USER_VOLTAGE
  • VCCA_USER_VOLTAGE
  • VCCAUX_SHARED_USER_VOLTAGE
  • VCCAUX_USER_VOLTAGE
  • VCCBAT_USER_VOLTAGE
  • VCCCB_USER_VOLTAGE
  • VCCD_FPLL_USER_VOLTAGE
  • VCCD_PLL_USER_VOLTAGE
  • VCCD_USER_VOLTAGE
  • VCCE_GXBL_USER_VOLTAGE
  • VCCE_GXBR_USER_VOLTAGE
  • VCCE_GXB_USER_VOLTAGE
  • VCCEH_GXBL_USER_VOLTAGE
  • VCCEH_GXBR_USER_VOLTAGE
  • VCCEH_GXB_USER_VOLTAGE
  • VCCELA_0P85V
  • VCCELA_0P9V
  • VCCELA_1P0V
  • VCCELA_1P1V
  • VCCERAM_USER_VOLTAGE
  • VCCER
  • VCCE_USER_VOLTAGE
  • VCCH_GTBR_USER_VOLTAGE
  • VCCH_GTB_USER_VOLTAGE
  • VCCH_GXBL_USER_VOLTAGE
  • VCCH_GXBR_USER_VOLTAGE
  • VCCH_GXB_USER_VOLTAGE
  • VCCHIP_L_USER_VOLTAGE
  • VCCHIP_R_USER_VOLTAGE
  • VCCHIP_USER_VOLTAGE
  • VCCH_L_USER_VOLTAGE
  • VCC_HPS_USER_VOLTAGE
  • VCCH_R_USER_VOLTAGE
  • VCCHSSI_L_USER_VOLTAGE
  • VCCHSSI_R_USER_VOLTAGE
  • VCCINT_USER_VOLTAGE
  • VCCIO_45
  • VCCIO_50
  • VCCIO_55
  • VCCIO_65
  • VCCIO_70
  • VCCIO_75
  • VCCIO_CURRENT_1PT8V
  • VCCIO_CURRENT_2PT5V
  • VCCIO_CURRENT_GTL
  • VCCIO_CURRENT_GTL_PLUS
  • VCCIO_CURRENT_LVCMOS
  • VCCIO_CURRENT_LVTTL
  • VCCIO_CURRENT_PCI
  • VCCIO_CURRENT_SSTL2_CLASS1
  • VCCIO_CURRENT_SSTL2_CLASS2
  • VCCIO_CURRENT_SSTL3_CLASS1
  • VCCIO_CURRENT_SSTL3_CLASS2
  • VCCIO_HPS_USER_VOLTAGE
  • VCCIO_IOBANK1_MAX7000B
  • VCCIO_IOBANK2_MAX7000B
  • VCCIOREF_HPS_USER_VOLTAGE
  • VCCIO_USER_VOLTAGE
  • VCCL_GTBL_USER_VOLTAGE
  • VCCL_GTBR_USER_VOLTAGE
  • VCCL_GTB_USER_VOLTAGE
  • VCCL_GXBL_USER_VOLTAGE
  • VCCL_GXBR_USER_VOLTAGE
  • VCCL_GXB_USER_VOLTAGE
  • VCCL_HPS_USER_VOLTAGE
  • VCCL_USER_VOLTAGE
  • VCCPD_USER_VOLTAGE
  • VCCPD_VOLTAGE
  • VCCPGM_USER_VOLTAGE
  • VCCPLL_HPS_USER_VOLTAGE
  • VCCPT_USER_VOLTAGE
  • VCCP_USER_VOLTAGE
  • VCCR_GTBL_USER_VOLTAGE
  • VCCR_GTBR_USER_VOLTAGE
  • VCCR_GTB_USER_VOLTAGE
  • VCCR_GXBL_USER_VOLTAGE
  • VCCR_GXBR_USER_VOLTAGE
  • VCCR_GXB_USER_VOLTAGE
  • VCCR_L_USER_VOLTAGE
  • VCCR_R_USER_VOLTAGE
  • VCCRSTCLK_HPS_USER_VOLTAGE
  • VCCR_USER_VOLTAGE
  • VCC_SETTING0
  • VCC_SETTING1
  • VCC_SETTING2
  • VCC_SETTING3
  • VCCT_GTBL_USER_VOLTAGE
  • VCCT_GTBR_USER_VOLTAGE
  • VCCT_GTB_USER_VOLTAGE
  • VCCT_GXBL_USER_VOLTAGE
  • VCCT_GXBR_USER_VOLTAGE
  • VCCT_GXB_USER_VOLTAGE
  • VCCT_L_USER_VOLTAGE
  • VCCT_R_USER_VOLTAGE
  • VCCT_USER_VOLTAGE
  • VCC_USER_VOLTAGE
  • VCD_FILE
  • VCM_CURRENT_1
  • VCM_CURRENT_2
  • VCM_CURRENT_3
  • VCM_CURRENT_DEFAULT
  • VCM_SETTING_00
  • VCM_SETTING_01
  • VCM_SETTING_02
  • VCM_SETTING_03
  • VCM_SETTING_04
  • VCM_SETTING_05
  • VCM_SETTING_06
  • VCM_SETTING_07
  • VCM_SETTING_08
  • VCM_SETTING_09
  • VCM_SETTING_10
  • VCM_SETTING_11
  • VCM_SETTING_12
  • VCM_SETTING_13
  • VCM_SETTING_14
  • VCM_SETTING_15
  • VECTOR_CHANNEL_FILE
  • VECTOR_COMPARE_TRIGGER_MODE
  • VECTOR_FILE
  • VECTOR_INPUT_SOURCE
  • VECTOR_OUTPUT_DESTINATION
  • VECTOR_OUTPUT_FORMAT
  • VECTOR_SOURCE_FILE
  • VECTOR_TABLE_OUTPUT_FILE
  • VECTOR_TEXT_FILE
  • VECTOR_WAVEFORM_FILE
  • VER_COMPATIBLE_DB_DIR
  • VERILOG_1995
  • VERILOG_2001
  • VERILOG_CONSTANT_LOOP_LIMIT
  • VERILOG_CU_MODE
  • VERILOG_FILE
  • VERILOG_GLOBAL_COMPILER_MACRO_FILE
  • VERILOG_INCLUDE_FILE
  • VERILOG_INPUT_VERSION
  • VERILOG_LMF_FILE
  • VERILOG_MACRO
  • VERILOG_NON_CONSTANT_LOOP_LIMIT
  • VERILOG_OUTPUT_FILE
  • VERILOG_SHOW_LMF_MAPPING_MESSAGES
  • VERILOG_SHOW_LMF_MAPPING_MSGS
  • VERILOG_TEST_BENCH_FILE
  • VERILOG_VH_FILE
  • VHDL_1987
  • VHDL_1993
  • VHDL_2008
  • VHDL87
  • VHDL93
  • VHDL_FILE
  • VHDL_INPUT_LIBRARY
  • VHDL_INPUT_VERSION
  • VHDL_LMF_FILE
  • VHDL_OUTPUT_FILE
  • VHDL_SHOW_LMF_MAPPING_MESSAGES
  • VHDL_SHOW_LMF_MAPPING_MSGS
  • VHDL_TEST_BENCH_FILE
  • VID_OPERATION_MODE
  • VIRTUAL_CLOCK_REFERENCE
  • VIRTUAL_EFUSES
  • VIRTUAL_IO_DRIVES_CLOCK_PORT
  • VIRTUAL_PIN
  • VOLT_0MV
  • VOLT_0P35V
  • VOLT_0P50V
  • VOLT_0P55V
  • VOLT_0P60V
  • VOLT_0P65V
  • VOLT_0P70V
  • VOLT_0P75V
  • VOLT_0P80V
  • VOLTS
  • VPACK
  • VPACK_ONLY
  • VQM_FILE
  • VREF_MODE
  • VREF_VOLT_0
  • VREF_VOLT_0P5
  • VREF_VOLT_0P75
  • VREF_VOLT_1P0
  • VTT_0P35V
  • VTT_0P50V
  • VTT_0P55V
  • VTT_0P60V
  • VTT_0P65V
  • VTT_0P70V
  • VTT_0P75V
  • VTT_0P80V
  • VTT_PDN_STRONG
  • VTT_PDN_WEAK
  • VTT_PUP_STRONG
  • VTT_PUP_WEAK
  • VTT_VCMOFF0
  • VTT_VCMOFF1
  • VTT_VCMOFF2
  • VTT_VCMOFF3
  • VTT_VCMOFF4
  • VTT_VCMOFF5
  • VTT_VCMOFF6
  • VTT_VCMOFF7
  • WAIT_1_MS
  • WAIT_2_MS
  • WAIT_4_MS
  • WAIT_50_MS
  • WAIT_8_MS
  • WEAK_PULL_UP
  • WEAK_PULL_UP_RESISTOR
  • WHEN_REQUESTED_BY_FPGA
  • WHEN_TSU_AND_TPD_CONSTRAINTS_PERMIT
  • WIDTH_0
  • WIDTH_18_BIT_MULTIPLIERS
  • WIDTH_1
  • WIDTH_2
  • WIDTH_3
  • WIDTH
  • WRITE
  • X1_PLL_FREQUENCY
  • XACTO_INCREMENTAL_COMPILE_ASSIGNMENT
  • XACTO_INCREMENTAL_COMPILE_FILE
  • XACTO_REGION
  • XACTO_VQM_FILES
  • XAUI_3125
  • XAUI
  • XCVR_A10_CDR_PLL_ANALOG_MODE
  • XCVR_A10_CDR_PLL_POWER_MODE
  • XCVR_A10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • XCVR_A10_CDR_PLL_UC_RO_CAL
  • XCVR_A10_CMU_FPLL_ANALOG_MODE
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • XCVR_A10_CMU_FPLL_POWER_MODE
  • XCVR_A10_LC_PLL_ANALOG_MODE
  • XCVR_A10_LC_PLL_POWER_MODE
  • XCVR_A10_PM_UC_CLKDIV_SEL
  • XCVR_A10_PM_UC_CLKSEL_CORE
  • XCVR_A10_PM_UC_CLKSEL_OSC
  • XCVR_A10_REFCLK_TERM_TRISTATE
  • XCVR_A10_RX_ADAPT_DFE_CONTROL_SEL
  • XCVR_A10_RX_ADAPT_DFE_SEL
  • XCVR_A10_RX_ADAPT_VGA_SEL
  • XCVR_A10_RX_ADAPT_VREF_SEL
  • XCVR_A10_RX_ADP_CTLE_ACGAIN_4S
  • XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
  • XCVR_A10_RX_ADP_DFE_FLTAP_POSITION
  • XCVR_A10_RX_ADP_DFE_FXTAP10
  • XCVR_A10_RX_ADP_DFE_FXTAP10_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP11
  • XCVR_A10_RX_ADP_DFE_FXTAP11_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP1
  • XCVR_A10_RX_ADP_DFE_FXTAP2
  • XCVR_A10_RX_ADP_DFE_FXTAP2_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP3
  • XCVR_A10_RX_ADP_DFE_FXTAP3_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP4
  • XCVR_A10_RX_ADP_DFE_FXTAP4_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP5
  • XCVR_A10_RX_ADP_DFE_FXTAP5_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP6
  • XCVR_A10_RX_ADP_DFE_FXTAP6_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP7
  • XCVR_A10_RX_ADP_DFE_FXTAP7_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP8
  • XCVR_A10_RX_ADP_DFE_FXTAP8_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP9
  • XCVR_A10_RX_ADP_DFE_FXTAP9_SGN
  • XCVR_A10_RX_ADP_LFEQ_FB_SEL
  • XCVR_A10_RX_ADP_ONETIME_DFE
  • XCVR_A10_RX_ADP_VGA_SEL
  • XCVR_A10_RX_ADP_VREF_SEL
  • XCVR_A10_RX_BYPASS_EQZ_STAGES_234
  • XCVR_A10_RX_EQ_BW_SEL
  • XCVR_A10_RX_EQ_DC_GAIN_TRIM
  • XCVR_A10_RX_INPUT_VCM_SEL
  • XCVR_A10_RX_LINK
  • XCVR_A10_RX_OFFSET_CANCELLATION_CTRL
  • XCVR_A10_RX_ONE_STAGE_ENABLE
  • XCVR_A10_RX_POWER_MODE
  • XCVR_A10_RX_QPI_ENABLE
  • XCVR_A10_RX_RX_SEL_BIAS_SOURCE
  • XCVR_A10_RX_SD_OUTPUT_OFF
  • XCVR_A10_RX_SD_OUTPUT_ON
  • XCVR_A10_RX_SD_THRESHOLD
  • XCVR_A10_RX_TERM_SEL
  • XCVR_A10_RX_TERM_TRI_ENABLE
  • XCVR_A10_RX_UC_RX_DFE_CAL
  • XCVR_A10_RX_VCCELA_SUPPLY_VOLTAGE
  • XCVR_A10_RX_VCM_CURRENT_ADD
  • XCVR_A10_RX_VCM_SEL
  • XCVR_A10_RX_XRX_PATH_ANALOG_MODE
  • XCVR_A10_TX_COMPENSATION_EN
  • XCVR_A10_TX_DCD_DETECTION_EN
  • XCVR_A10_TX_DPRIO_CGB_VREG_BOOST
  • XCVR_A10_TX_LINK
  • XCVR_A10_TX_LOW_POWER_EN
  • XCVR_A10_TX_POWER_MODE
  • XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • XCVR_A10_TX_RES_CAL_LOCAL
  • XCVR_A10_TX_RX_DET
  • XCVR_A10_TX_RX_DET_OUTPUT_SEL
  • XCVR_A10_TX_RX_DET_PDB
  • XCVR_A10_TX_SLEW_RATE_CTRL
  • XCVR_A10_TX_TERM_CODE
  • XCVR_A10_TX_TERM_SEL
  • XCVR_A10_TX_UC_DCD_CAL
  • XCVR_A10_TX_UC_GEN3
  • XCVR_A10_TX_UC_GEN4
  • XCVR_A10_TX_UC_SKEW_CAL
  • XCVR_A10_TX_UC_TXVOD_CAL_CONT
  • XCVR_A10_TX_UC_TXVOD_CAL
  • XCVR_A10_TX_UC_VCC_SETTING
  • XCVR_A10_TX_USER_FIR_COEFF_CTRL_SEL
  • XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
  • XCVR_A10_TX_XTX_PATH_ANALOG_MODE
  • XCVR_ANALOG_SETTINGS_PROTOCOL
  • XCVR_C10_CDR_PLL_ANALOG_MODE
  • XCVR_C10_CDR_PLL_POWER_MODE
  • XCVR_C10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • XCVR_C10_CDR_PLL_UC_RO_CAL
  • XCVR_C10_CMU_FPLL_ANALOG_MODE
  • XCVR_C10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • XCVR_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • XCVR_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • XCVR_C10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • XCVR_C10_CMU_FPLL_POWER_MODE
  • XCVR_C10_LC_PLL_ANALOG_MODE
  • XCVR_C10_LC_PLL_POWER_MODE
  • XCVR_C10_PM_UC_CLKDIV_SEL
  • XCVR_C10_PM_UC_CLKSEL_CORE
  • XCVR_C10_PM_UC_CLKSEL_OSC
  • XCVR_C10_REFCLK_TERM_TRISTATE
  • XCVR_C10_RX_ADAPT_DFE_CONTROL_SEL
  • XCVR_C10_RX_ADAPT_DFE_SEL
  • XCVR_C10_RX_ADAPT_VGA_SEL
  • XCVR_C10_RX_ADAPT_VREF_SEL
  • XCVR_C10_RX_ADP_CTLE_ACGAIN_4S
  • XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL
  • XCVR_C10_RX_ADP_DFE_FLTAP_POSITION
  • XCVR_C10_RX_ADP_DFE_FXTAP10
  • XCVR_C10_RX_ADP_DFE_FXTAP10_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP11
  • XCVR_C10_RX_ADP_DFE_FXTAP11_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP1
  • XCVR_C10_RX_ADP_DFE_FXTAP2
  • XCVR_C10_RX_ADP_DFE_FXTAP2_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP3
  • XCVR_C10_RX_ADP_DFE_FXTAP3_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP4
  • XCVR_C10_RX_ADP_DFE_FXTAP4_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP5
  • XCVR_C10_RX_ADP_DFE_FXTAP5_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP6
  • XCVR_C10_RX_ADP_DFE_FXTAP6_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP7
  • XCVR_C10_RX_ADP_DFE_FXTAP7_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP8
  • XCVR_C10_RX_ADP_DFE_FXTAP8_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP9
  • XCVR_C10_RX_ADP_DFE_FXTAP9_SGN
  • XCVR_C10_RX_ADP_LFEQ_FB_SEL
  • XCVR_C10_RX_ADP_ONETIME_DFE
  • XCVR_C10_RX_ADP_VGA_SEL
  • XCVR_C10_RX_ADP_VREF_SEL
  • XCVR_C10_RX_BYPASS_EQZ_STAGES_234
  • XCVR_C10_RX_EQ_BW_SEL
  • XCVR_C10_RX_EQ_DC_GAIN_TRIM
  • XCVR_C10_RX_INPUT_VCM_SEL
  • XCVR_C10_RX_LINK
  • XCVR_C10_RX_OFFSET_CANCELLATION_CTRL
  • XCVR_C10_RX_ONE_STAGE_ENABLE
  • XCVR_C10_RX_POWER_MODE
  • XCVR_C10_RX_QPI_ENABLE
  • XCVR_C10_RX_RX_SEL_BIAS_SOURCE
  • XCVR_C10_RX_SD_OUTPUT_OFF
  • XCVR_C10_RX_SD_OUTPUT_ON
  • XCVR_C10_RX_SD_THRESHOLD
  • XCVR_C10_RX_TERM_SEL
  • XCVR_C10_RX_TERM_TRI_ENABLE
  • XCVR_C10_RX_UC_RX_DFE_CAL
  • XCVR_C10_RX_VCCELA_SUPPLY_VOLTAGE
  • XCVR_C10_RX_VCM_CURRENT_ADD
  • XCVR_C10_RX_VCM_SEL
  • XCVR_C10_RX_XRX_PATH_ANALOG_MODE
  • XCVR_C10_TX_COMPENSATION_EN
  • XCVR_C10_TX_DCD_DETECTION_EN
  • XCVR_C10_TX_DPRIO_CGB_VREG_BOOST
  • XCVR_C10_TX_LINK
  • XCVR_C10_TX_LOW_POWER_EN
  • XCVR_C10_TX_POWER_MODE
  • XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • XCVR_C10_TX_RES_CAL_LOCAL
  • XCVR_C10_TX_RX_DET
  • XCVR_C10_TX_RX_DET_OUTPUT_SEL
  • XCVR_C10_TX_RX_DET_PDB
  • XCVR_C10_TX_SLEW_RATE_CTRL
  • XCVR_C10_TX_TERM_CODE
  • XCVR_C10_TX_TERM_SEL
  • XCVR_C10_TX_UC_DCD_CAL
  • XCVR_C10_TX_UC_GEN3
  • XCVR_C10_TX_UC_GEN4
  • XCVR_C10_TX_UC_SKEW_CAL
  • XCVR_C10_TX_UC_TXVOD_CAL_CONT
  • XCVR_C10_TX_UC_TXVOD_CAL
  • XCVR_C10_TX_UC_VCC_SETTING
  • XCVR_C10_TX_USER_FIR_COEFF_CTRL_SEL
  • XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL
  • XCVR_C10_TX_XTX_PATH_ANALOG_MODE
  • XCVR_FAST_LOCK_MODE
  • XCVR_GT_IO_PIN_TERMINATION
  • XCVR_GT_RX_COMMON_MODE_VOLTAGE
  • XCVR_GT_RX_CTLE
  • XCVR_GT_RX_DC_GAIN
  • XCVR_GT_RX_FORCE_VCO_CONST
  • XCVR_GT_TX_COMMON_MODE_VOLTAGE
  • XCVR_GT_TX_PRE_EMP_1ST_POST_TAP
  • XCVR_GT_TX_PRE_EMP_INV_PRE_TAP
  • XCVR_GT_TX_PRE_EMP_PRE_TAP
  • XCVR_GT_TX_VOD_MAIN_TAP
  • XCVR_IO_PIN_TERMINATION
  • XCVR_RECONFIG_AVMM_GROUP
  • XCVR_RECONFIG_GROUP
  • XCVR_REFCLK_PIN_TERMINATION
  • XCVR_RX_ACGAIN_A
  • XCVR_RX_ACGAIN_V
  • XCVR_RX_ADCE_HSF_HFBW
  • XCVR_RX_ADCE_RGEN_BW
  • XCVR_RX_ADCE_RGEN_MODE
  • XCVR_RX_BYPASS_EQ_STAGES_234
  • XCVR_RX_COMMON_MODE_VOLTAGE
  • XCVR_RX_DC_GAIN
  • XCVR_RX_DFE_PI_BW
  • XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
  • XCVR_RX_EQ_BW_SEL
  • XCVR_RX_EYEQ_BANDWIDTH
  • XCVR_RX_INPUT_VCM_SEL
  • XCVR_RX_LINEAR_EQUALIZER_CONTROL
  • XCVR_RX_PMOS_GAIN_PEAK
  • XCVR_RX_QPI_ENABLE
  • XCVR_RX_SD_ENABLE
  • XCVR_RX_SD_OFF
  • XCVR_RX_SD_ON
  • XCVR_RX_SD_THRESHOLD
  • XCVR_RX_SEL_BIAS_SOURCE
  • XCVR_RX_SEL_HALF_BW
  • XCVR_RX_VCM_DRIVE_STRENGTH
  • XCVR_S10_REFCLK_TERM_TRISTATE
  • XCVR_TX_COMMON_MODE_VOLTAGE
  • XCVR_TX_DRIVER_RESOLUTION_CTRL
  • XCVR_TX_LOCAL_IB_CTL
  • XCVR_TX_PLL_RECONFIG_GROUP
  • XCVR_TX_PRE_EMP_1ST_POST_TAP
  • XCVR_TX_PRE_EMP_2ND_POST_TAP
  • XCVR_TX_PRE_EMP_2ND_POST_TAP_USER
  • XCVR_TX_PRE_EMP_INV_2ND_TAP
  • XCVR_TX_PRE_EMP_INV_PRE_TAP
  • XCVR_TX_PRE_EMP_PRE_TAP
  • XCVR_TX_PRE_EMP_PRE_TAP_USER
  • XCVR_TX_QPI_EN
  • XCVR_TX_RX_DET_ENABLE
  • XCVR_TX_RX_DET_MODE
  • XCVR_TX_RX_DET_OUTPUT_SEL
  • XCVR_TX_SLEW_RATE_CTRL
  • XCVR_TX_SWING_BOOST
  • XCVR_TX_VCM_CTRL_SRC
  • XCVR_TX_VCM_DRIVE_STRENGTH
  • XCVR_TX_VOD_BOOST
  • XCVR_TX_VOD
  • XCVR_TX_VOD_PRE_EMP_CTRL_SRC
  • XCVR_USE_HQ_REFCLK
  • XCVR_USE_SKEW_BALANCED
  • XCVR_VCCA_VOLTAGE
  • XCVR_VCCR_VCCT_VOLTAGE
  • X_ON_VIOLATION_OPTION
  • XOR_SYNTHESIS
  • XR_AUTO_SIZE
  • XR_CORE_ONLY
  • XR_EXCLUDE
  • XR_HEIGHT
  • XR_MEMBER_OF
  • XR_MEMBER_OPTION
  • XR_MEMBER_RESOURCE_EXCLUDE
  • XR_MEMBER_STATE
  • XR_NODE_LOCATION
  • XR_ORIGIN
  • XR_PARENT
  • XR_PATH_EXCLUDE
  • XR_PATH_INCLUDE
  • XR_PRIORITY
  • XR_RESERVE
  • XR_ROOT_REGION
  • XR_ROUGH
  • XR_SOFT
  • XR_STATE
  • XR_WIDTH
  • XSTL_INPUT_ALLOW_SE_BUFFER
  • YEAGER_CONFIGURATION_DEVICE
  • YEAGER_CRC_ERROR_CHECKING
  • YEAGER_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • YEAGER_DEVICE_IO_STANDARD
  • YEAGER_OCT_AND_IMPEDANCE_MATCHING
  • YEAGER_OPTIMIZATION_TECHNIQUE
  • YEAGER_TECHNOLOGY_MAPPER
  • YEAGER_UPDATE_MODE
  • ZBT_OE_FALLING_EDGE_DELAY
  • ZERO_DELAY_BUFFER
  • ZERO
  • ZIP_VECTOR_CHANNEL_FILE
  • ZIP_VECTOR_WAVEFORM_FILE

Quartus 17.1 (non-pro): List of QSF parameter names

Due to rather peculiar reasons described in this post, I found myself looking for all QSF parameter names that Quartus recognizes. I ended up searching a binary file in Quartus’ installation directory. So this is by no means an authoritative list, but since I made it, I thought I should post it. Just in case someone else is in the business of guesswork.

So this was done with non-Pro Quartus 17.1 running Linux. For Quartus Pro 19.2, refer to this post.

This is plain text search, so quite clearly not all items appearing here are legal QSF parameters, and neither is it clear if this list is complete. Or otherwise useful, for that matter.

$ strings ./quartus/linux64/libdb_acf.so | perl -ne '/^[A-Z][A-Z0-9_]+\n*$/ && print' | sort -u
  • ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS
  • ACCEPTS_NEGATIVE
  • ACCEPTS_OPEN
  • ACCEPTS_SHORT
  • ACCEPTS_TRACK_VCCIO
  • ACCEPTS_WILDCARDS
  • ACCEPTS_ZERO
  • AC_COUPLING
  • ACF_ASSIGNMENT_USE_STRING_POOL
  • ACF_NOTIFY_ACF_MANAGER_ASSIGNMENTS_CHANGED
  • ACF_STRING_POOL_MASSIVE_DUMP
  • ACF_VARIABLE_TRAIT_TYPE_MAX_TRAIT_TYPE
  • ACF_VARIABLE_TYPE_ACF_ACF_LAST_VARIABLE
  • ACLK_CAT
  • ACLK_RULE_IMSZER_ADOMAIN
  • ACLK_RULE_NO_SZER_ACLK_DOMAIN
  • ACLK_RULE_SZER_BTW_ACLK_DOMAIN
  • ACTIVE_PARALLEL
  • ACTIVE_SERIAL_CLOCK
  • ACTIVE_SERIAL
  • ACTIVE_SERIAL_X1
  • ACTIVE_SERIAL_X4
  • ADCE_ENABLED
  • ADCE_FULL_BW
  • ADCE_HALF_BW
  • ADCE_HIGH_BW
  • ADCE_HIGH_FREQ_MODE
  • ADCE_LOW_BW
  • ADCE_LOW_FREQ_MODE
  • ADCE_MED_HIGH_BW
  • ADCE_MED_HIGH_MODE
  • ADCE_MED_LOW_BW
  • ADCE_MED_LOW_MODE
  • ADD_DEFAULT_PINS_TO_OUTPUT_VECTOR_FILE
  • ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS
  • ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
  • ADD_TO_SIMULATION_OUTPUT_WAVEFORMS
  • ADVANCED_CLOCK_OPTIMIZATION
  • ADVANCED
  • ADVANCED_PHYSICAL_OPTIMIZATION
  • ADVANCED_PHYSICAL_RETIMING
  • ADVANCED_PHYSICAL_SYNTHESIS
  • ADV_NETLIST_OPT_ALLOWED
  • ADV_NETLIST_OPT_DONT_TOUCH
  • ADV_NETLIST_OPT_FIT_LE_DUPLICATION
  • ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTHESIS
  • ADV_NETLIST_OPT_FIT_LE_RETIME
  • ADV_NETLIST_OPT_METASTABLE_REGS
  • ADV_NETLIST_OPT_RETIME_CORE_AND_IO
  • ADV_NETLIST_OPT_STRING
  • ADV_NETLIST_OPT_SYNTH_ALLOW_IP_WYS_UNMAPPING
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME_1
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME_2
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME
  • ADV_NETLIST_OPT_SYNTH_REMAP_1
  • ADV_NETLIST_OPT_SYNTH_REMAP_2
  • ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO
  • ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
  • ADV_NETLIST_OPT_TEST
  • AGGREGATE
  • AGGREGATE_REVISION
  • AGGRESSIVE_AREA
  • AGGRESSIVE
  • AGGRESSIVE_PERFORMANCE
  • AGGRESSIVE_POWER
  • AHDL_FILE
  • AHDL_INCLUDE_FILE
  • AHDL_LIMIT_INT_TO_32
  • AHDL_TEXT_DESIGN_OUTPUT_FILE
  • AHDL_USE_LPM_FOR_OPERATORS
  • ALIAS
  • ALL_EDGE
  • ALL_EXCEPT_COMBINATIONAL_LOGIC_ELEMENT_OUTPUTS
  • ALL_NODES
  • ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION
  • ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
  • ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
  • ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
  • ALLOW_CASCADE_GPLL_TO_LVDS_TX
  • ALLOW_CHILD_PARTITIONS
  • ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER
  • ALLOW_MULTIPLE_PERSONAS
  • ALLOW_PARALLEL_TERMINATION
  • ALLOW_POWER_UP_DONT_CARE
  • ALLOW_REGISTER_DUPLICATION
  • ALLOW_REGISTER_MERGING
  • ALLOW_REGISTER_RETIMING
  • ALLOW_SERIES_TERMINATION
  • ALLOW_SERIES_WITH_CALIBRATION_TERMINATION
  • ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
  • ALLOW_SYNCH_CTRL_USAGE
  • ALLOW_XOR_GATE_USAGE
  • ALL_PATHS
  • ALL_STAGES_ENABLED
  • ALM_REGISTER
  • ALM_REGISTER_PACKING_EFFORT
  • ALTERA_A10_IOPLL_BOOTSTRAP
  • ALTERA_INTERNAL_FIB
  • ALTERA
  • ALWAYS_ALLOW
  • ALWAYS_ENABLE_INPUT_BUFFERS
  • ALWAYS
  • ALWAYS_REGENERATE_IP
  • ALWAYS_WRITE_TO_FILE
  • ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS
  • ANALYZE_LATCHES
  • ANALYZE_METASTABILITY
  • APEX20K_CLIQUE_TYPE
  • APEX20K_CONFIG_DEVICE_JTAG_USER_CODE
  • APEX20K_CONFIGURATION_DEVICE
  • APEX20K_CONFIGURATION_SCHEME
  • APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • APEX20K_DEVICE_IO_STANDARD
  • APEX20KE_DEVICE_IO_STANDARD
  • APEX20KF_DEVICE_IO_STANDARD
  • APEX20K_JTAG_USER_CODE
  • APEX20K_LOCAL_ROUTING_SOURCE
  • APEX20K_OPTIMIZATION_TECHNIQUE
  • APEX20K_TECHNOLOGY_MAPPER
  • APEX_FITTER_TYPE
  • APEXII_1_8V_HSTL
  • APEX_II_CONFIGURATION_SCHEME
  • APEXII_CONFIGURATION_SCHEME
  • APEXII_DEVICE_IO_STANDARD
  • AREF_VOLT_0
  • AREF_VOLT_0P5
  • AREF_VOLT_0P75
  • AREF_VOLT_1P0
  • ARMSTRONG_CARRY_CHAIN_LENGTH
  • ARMSTRONG_OPTIMIZATION_TECHNIQUE
  • ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE
  • AS_BIDIRECTIONAL
  • ASCII_REPORT_FILE
  • AS_FREQ_100MHZ
  • AS_FREQ_25MHZ
  • AS_FREQ_50MHZ
  • AS_INPUT_TRI_STATED
  • AS_INPUT_TRI_STATED_WITH_BUS_HOLD
  • AS_INPUT_TRI_STATED_WITH_WEAK_PULL_UP
  • ASM_FILE
  • ASM_OPTIONS_FILE_KEYWORD
  • AS_OUTPUT_DRIVING_AN_UNSPECIFIED_SIGNAL
  • AS_OUTPUT_DRIVING_GROUND
  • AS_OUTPUT_DRIVING_VCC
  • ASP_ASM_COMMAND_LINE
  • ASP_CPP_COMMAND_LINE
  • ASP_LINK_COMMAND_LINE
  • ASSEMBLER_ASSIGNMENT
  • ASSG_CAT
  • ASSG_RULE_MISSING_FMAX
  • ASSG_RULE_MISSING_TIMING
  • AS_SIGNALPROBE_OUTPUT
  • ASSIGNMENT_GROUP_ASSIGNMENT
  • ASSIGNMENT_GROUP_EXCEPTION
  • ASSIGNMENT_GROUP_MEMBER
  • AS_VREFA
  • AS_VREFB
  • AS_VREF
  • ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK
  • ASYNC_PIPELINE_REG_REACH
  • ATUH
  • ATUSH
  • ATUS
  • AUATA
  • AUATI
  • AUATL
  • AUATUD
  • AUATUH
  • AUATU
  • AUATUSH
  • AUATUS
  • AUTO_C3_M9K_BIT_SKIP
  • AUTO_CARRY_CHAINS
  • AUTO_CARRY
  • AUTO_CASCADE_CHAINS
  • AUTO_CASCADE
  • AUTO_CLOCK_ENABLE_RECOGNITION
  • AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS
  • AUTO_DELAY_CHAINS
  • AUTO_DISCOVER_AND_SORT
  • AUTO_DISCOVERY
  • AUTO_DSP_RECOGNITION
  • AUTO_ENABLE_SMART_COMPILE
  • AUTO_EXPORT_INCREMENTAL_COMPILATION
  • AUTO_EXPORT_VER_COMPATIBLE_DB
  • AUTO_FAST_INPUT_REGISTERS
  • AUTO_FAST_OUTPUT_ENABLE_REGISTERS
  • AUTO_FAST_OUTPUT_REGISTERS
  • AUTO_FIT
  • AUTO_GLOBAL_CLOCK
  • AUTO_GLOBAL_CLOCK_MAX
  • AUTO_GLOBAL_MEM_CTRL
  • AUTO_GLOBAL_MEMORY_CONTROLS
  • AUTO_GLOBAL_OE
  • AUTO_GLOBAL_OE_MAX
  • AUTO_GLOBAL_REG_CTRL
  • AUTO_GLOBAL_REG_CTRL_MAX
  • AUTO_GLOBAL_REGISTER_CONTROLS
  • AUTO_IMPLEMENT_IN_ROM
  • AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE
  • AUTO_INCREMENT_EPROM_JTAG_CODE
  • AUTO_INCREMENT_USER_JTAG_CODE
  • AUTO_INPUT_REGISTER
  • AUTO_INPUT_REGISTERS
  • AUTO_INSERT_SLD_HUB_ENTITY
  • AUTO_INSERT_SLD_INCR_NODE_ENTITY
  • AUTO_INSERT_SLD_NODE_ENTITY
  • AUTO_LCELL_INSERTION
  • AUTOMATIC
  • AUTO_MERGE_PLLS
  • AUTO_MODIFIED_PACKED_REGISTERS
  • AUTO_OPEN_DRAIN
  • AUTO_OPEN_DRAIN_PINS
  • AUTO_OUTPUT_ENABLE_REGISTER
  • AUTO_OUTPUT_REGISTER
  • AUTO_OUTPUT_REGISTERS
  • AUTO_PACKED_REG_CYCLONE
  • AUTO_PACKED_REGISTERS_ARMSTRONG
  • AUTO_PACKED_REGISTERS_CYCLONE
  • AUTO_PACKED_REGISTERS_MAXII
  • AUTO_PACKED_REGISTERS_MAX
  • AUTO_PACKED_REGISTERS_STRATIXII
  • AUTO_PACKED_REGISTERS_STRATIX
  • AUTO_PACKED_REGISTERS_TSUNAMI
  • AUTO_PARALLEL_EXPANDERS
  • AUTO_PARALLEL_SYNTHESIS
  • AUTO_PERIPH
  • AUTO_PEXP
  • AUTO_QIC_EXPORT
  • AUTO_QXP_PARTITION
  • AUTO_RAM_BLOCK_BALANCING
  • AUTO_RAM_RECOGNITION
  • AUTO_RAM_TO_LCELL_CONVERSION
  • AUTO_RESERVE_CLKUSR_FOR_CALIBRATION
  • AUTO_RESOURCE_SHARING
  • AUTO_RESTART_CONFIGURATION
  • AUTO_RESTART
  • AUTO_ROM
  • AUTO_ROM_RECOGNITION
  • AUTO_SHIFT_REGISTER_RECOGNITION
  • AUTO_SLD_HUB_ENTITY
  • AUTO_TURBO_BIT
  • AUTO_USE_SIMULATION_PDB_NETLIST
  • AVAUA
  • AVAUATI
  • AVAUATUH
  • AVAUATUSD
  • AVAUATUSH
  • AVAUI
  • AVST_CLK_RESERVED
  • AVST_DATA15_0_RESERVED
  • AVST_DATA31_16_RESERVED
  • AVST_VALID_RESERVED
  • AVST_X16
  • AVST_X32
  • AVST_X8
  • AWAVA
  • AWAVAUA
  • AWAVAUATA
  • AWAVAUATE
  • AWAVAUATI
  • AWAVAUATL
  • AWAVAUATUH
  • AWAVAUATUSH
  • AWAVAUI
  • AWAVE
  • AWAVI
  • AWAVL
  • AWAVM
  • BAK_AUTO_EXPORT
  • BAK_EXPORT_DIR
  • BALANCED
  • BASED_ON_CLOCK_SETTINGS
  • BASEO
  • BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
  • BASE_REVISION
  • BASE_REVISION_PROJECT_OUTPUT_DIRECTORY
  • BASIC
  • BDF_FILE
  • BEST
  • BIAS_INT
  • BIAS_VCMDRV
  • BLOCK_DESIGN_NAMING
  • BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
  • BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS
  • BLOCK_RAM_TO_MLAB_CELL_CONVERSION
  • BOARD
  • BOARD_MODEL_CUSTOM
  • BOARD_MODEL_EBD_FAR_END
  • BOARD_MODEL_EBD_FILE_NAME
  • BOARD_MODEL_EBD_SIGNAL_NAME
  • BOARD_MODEL_FAR_C
  • BOARD_MODEL_FAR_DIFFERENTIAL_R
  • BOARD_MODEL_FAR_PULLDOWN_R
  • BOARD_MODEL_FAR_PULLUP_R
  • BOARD_MODEL_FAR_SERIES_R
  • BOARD_MODEL_NEAR_C
  • BOARD_MODEL_NEAR_DIFFERENTIAL_R
  • BOARD_MODEL_NEAR_PULLDOWN_R
  • BOARD_MODEL_NEAR_PULLUP_R
  • BOARD_MODEL_NEAR_SERIES_C
  • BOARD_MODEL_NEAR_SERIES_R
  • BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
  • BOARD_MODEL_NEAR_TLINE_LENGTH
  • BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
  • BOARD_MODEL_TERMINATION_V
  • BOARD_MODEL_TLINE_C_PER_LENGTH
  • BOARD_MODEL_TLINE_LENGTH
  • BOARD_MODEL_TLINE_L_PER_LENGTH
  • BOTH_EDGES
  • BREAKPOINT_FILE
  • BREAKPOINT
  • BREAKPOINT_LINE_NUMBER
  • BREAKPOINT_STATE
  • BSF_FILE
  • BW_FULL_12P5
  • BW_HALF_6P5
  • BYPASS_ERROR_RELEASE_CLEARS_BEFORE_TRISTATES_1S25
  • BYPASS
  • BYPASS_OFF
  • BYPASS_STAGES_234
  • BYTE_ORDER
  • BYYPASS_STAGES_234
  • CALIBRATED
  • CALIBRATED_SSTL
  • CAL_SIM_ACTIVATOR
  • CAP_NAME
  • CARRY_CHAIN_LENGTH_ARMSTRONG
  • CARRY_CHAIN_LENGTH_DALI
  • CARRY_CHAIN_LENGTH_FLEX10K
  • CARRY_CHAIN_LENGTH_FLEX6K
  • CARRY_CHAIN_LENGTH_TSUNAMI
  • CARRY_CHAIN_LENGTH_YEAGER
  • CARRY_OUT_PINS_LCELL_INSERT
  • CASCADE_CHAIN_LENGTH
  • CASE_SENSITIVE
  • CAT_ASSEMBLER
  • CAT_ASSIGNMENT_GROUP
  • CAT_DESIGN_ASSISTANT
  • CAT_FITTER
  • CAT_INCREMENTAL_COMPILATION
  • CAT_LOCATION_PIN
  • CAT_LOGICLOCK
  • CAT_MAPPER_SYNTHESIS
  • CAT_NETO
  • CAT_PARAMETERS
  • CAT_POWER_ESTIMATION
  • CAT_PROGRAMMER
  • CAT_SIGNALPROBE
  • CAT_SIGNALTAP
  • CAT_SIMULATION
  • CAT_SOFTWARE_BUILDER
  • CAT_TIMEGROUP
  • CAT_TIMING_ANALYSIS
  • CAT_TIMING
  • CB_CLKUSR
  • CB_INTOSC
  • CDF_FILE
  • CDR_BANDWIDTH_PRESET
  • CEI_11100_LR
  • CEI_11100_SR
  • CEI_4976_LR
  • CEI_4976_SR
  • CEI_6375_LR
  • CEI_6375_SR
  • CEI_9950_LR
  • CEI_9950_SR
  • CE_OPTION
  • CHAIN_FILE
  • CHECK_AGAINST_TSM_DELAY
  • CHECK_OUTPUTS
  • CHIP
  • CKN_CK_PAIR
  • CLAMPING_DIODE
  • CLIQUE_TYPE_APEX20K
  • CLIQUE_TYPE_DALI
  • CLIQUE_TYPE_FLEX10K
  • CLIQUE_TYPE_FLEX6K
  • CLIQUE_TYPE_MAX7K
  • CLK_FPLL_VREG_BOOST_1_STEP
  • CLK_FPLL_VREG_BOOST_2_STEP
  • CLK_FPLL_VREG_BOOST_3_STEP
  • CLK_FPLL_VREG_BOOST_4_STEP
  • CLK_FPLL_VREG_BOOST_5_STEP
  • CLK_FPLL_VREG_BOOST_6_STEP
  • CLK_FPLL_VREG_BOOST_7_STEP
  • CLK_FPLL_VREG_NO_VOLTAGE_BOOST
  • CLKLOCKX1_INPUT_FREQ
  • CLK_RULE_ALL
  • CLK_RULE_CLKNET_CLKSPINES
  • CLK_RULE_CLKNET_CLKSPINES_THRESHOLD
  • CLK_RULE_COMB_CLOCK
  • CLK_RULE_GATED_CLK_FANOUT
  • CLK_RULE_GATING_SCHEME
  • CLK_RULE_INPINS_CLKNET
  • CLK_RULE_INV_CLOCK
  • CLK_RULE_MIX_EDGES
  • CLOCK_ANALYSIS_ONLY
  • CLOCK_ENABLE_MULTICYCLE_HOLD
  • CLOCK_ENABLE_MULTICYCLE
  • CLOCK_ENABLE_ROUTING
  • CLOCK_ENABLE_SOURCE_MULTICYCLE_HOLD
  • CLOCK_ENABLE_SOURCE_MULTICYCLE
  • CLOCK_HOLD_UNCERTAINTY
  • CLOCK_SETUP_UNCERTAINTY
  • CLOCK_SOURCE
  • CLOCK_SPINE
  • CLOCK_TO_OUTPUT_DELAY
  • CLOUD_NOTIFY_COMPILE_ID
  • CLOUD_NOTIFY_ENABLE
  • CLOUD_NOTIFY_ENABLE_LOGGING
  • CLOUD_NOTIFY_GROUP_ID
  • CLOUD_NOTIFY_LOGGING
  • CLOUD_NOTIFY_PROXY
  • CLOUD_NOTIFY_SEND_CRIT_WARNINGS
  • CLOUD_NOTIFY_SEND_ERRORS
  • CLOUD_NOTIFY_SEND_JSON_REPORTS
  • CLOUD_NOTIFY_SERVER
  • CLOUD_NOTIFY_TOKEN
  • COMMAND_MACRO_FILE
  • COMMAND_MACRO_MODE
  • COMPANION_REVISION_NAME
  • COMPARED_CLOCK
  • COMPATIBLE_PLACEMENT_AND_ROUTING
  • COMPATIBLE_PLACEMENT
  • COMPILATION_LEVEL
  • COMPILE_NEW_PROJECT
  • COMPILER_ACTION_POINTS
  • COMPILER_ASSIGNMENT
  • COMPILER_CONFIGURED
  • COMPILER_SETTINGS_LIST
  • COMPILER_SIGNATURE_ID
  • COMPRESSION_MODE
  • CONBINATION10
  • CONBINATION11
  • CONBINATION1
  • CONBINATION2
  • CONBINATION3
  • CONBINATION4
  • CONBINATION5
  • CONBINATION6
  • CONBINATION7
  • CONBINATION8
  • CONBINATION9
  • CONFIG_DEVICE_JTAG_USER_CODE_DALI
  • CONFIG_DEVICE_JTAG_USER_CODE_FLEX6K
  • CONFIG_DEVICE_JTAG_USER_CODE
  • CONFIGURATION_CLOCK_DIVISOR
  • CONFIGURATION_CLOCK_FREQUENCY
  • CONFIGURATION_DEVICE_DALI
  • CONFIGURATION_DEVICE_FLEX6K
  • CONFIGURATION_SCHEME_DALI
  • CONFIGURATION_SCHEME_FLEX6K
  • CONFIGURATION_VCCIO_LEVEL
  • CONNECT_BIDIR_PIN_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_BIDIR_PIN_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_PIN_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_PIN_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_PIN_TO_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_PIN_TO_SLD_NODE_ENTITY_PORT
  • CONNECT_TO
  • CONNECT_TO_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_TO_SLD_NODE_ENTITY_PORT
  • CONTAINS_FAMILY_SPECIFIC_DATA
  • CONVERT_ALOAD_TO_CLEAR_PRESET
  • CONVERT_PR_WARNINGS_TO_ERRORS
  • COPY_IF_NODE_IS_DUPLICATED
  • COPY_VARIABLE_TYPE_IN_PIN_PLANNER
  • CORE_INITIALIZATION_AND_UPDATE
  • CORE_INITIALIZATION
  • CORE_ONLY_PLACE_REGION
  • CORE_UPDATE
  • COVERAGE_COMPLETE_PANEL_ENABLED
  • COVERAGE_MISSING_0_VALUE_PANEL_ENABLED
  • COVERAGE_MISSING_1_VALUE_PANEL_ENABLED
  • CPP_FILE
  • CPP_INCLUDE_FILE
  • CPRI_12500
  • CPRI_E12HV
  • CPRI_E12LVIII
  • CPRI_E12LVII
  • CPRI_E12LV
  • CPRI_E24LVIII
  • CPRI_E24LVII
  • CPRI_E24LV
  • CPRI_E30LVIII
  • CPRI_E30LVII
  • CPRI_E30LV
  • CPRI_E48LVIII
  • CPRI_E48LVII
  • CPRI_E60LVIII
  • CPRI_E60LVII
  • CPRI_E6HV
  • CPRI_E6LVIII
  • CPRI_E6LVII
  • CPRI_E6LV
  • CPRI_E96LVIII
  • CPRI_E99LVIII
  • CPRI
  • CRC_ERROR_CHECKING_YEAGER
  • CRC_ERROR_OPEN_DRAIN
  • CREATED_BY
  • CREATED_FROM
  • CROSS_BOUNDARY_OPTIMIZATIONS
  • CURRENT_STRENGTH
  • CURRENT_STRENGTH_NEW
  • CUSP_FILE
  • CUSTOM_BUILD_COMMAND_LINE
  • CUSTOM_CLOCK_TREE
  • CUT_OFF_CLEAR_AND_PRESET_PATHS
  • CUT_OFF_IO_PIN_FEEDBACK
  • CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS
  • CUT_OFF_READ_DURING_WRITE_PATH
  • CUT_OFF_READ_DURING_WRITE_PATHS
  • CVPCIE_CONFDONE_OPEN_DRAIN
  • CVPCIE_MODE
  • CVP_CONFDONE_OPEN_DRAIN
  • CVP_MODE
  • CVP_REVISION
  • CVWF
  • CYCLONE_CONFIGURATION_DEVICE
  • CYCLONE_CONFIGURATION_SCHEME
  • CYCLONEII_CONFIGURATION_SCHEME
  • CYCLONEIII_CONFIGURATION_DEVICE
  • CYCLONEIII_CONFIGURATION_SCHEME
  • CYCLONEII_M4K_COMPATIBILITY
  • CYCLONEII_OPTIMIZATION_TECHNIQUE
  • CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION
  • CYCLONEII_TERMINATION
  • CYCLONE_OPTIMIZATION_TECHNIQUE
  • D1_DELAY
  • D1_FINE_DELAY
  • D2_DELAY
  • D3_DELAY
  • D4_DELAY
  • D4_FINE_DELAY
  • D5_DELAY
  • D5_FINE_DELAY
  • D5_OCT_DELAY
  • D5_OE_DELAY
  • D6_DELAY
  • D6_FINE_DELAY
  • D6_OCT_DELAY
  • D6_OE_DELAY
  • D6_OE_FINE_DELAY
  • DA_CUSTOM_RULE_FILE
  • DATA0_PIN
  • DATA0_RESERVED
  • DATA15_8_RESERVED
  • DATA1_RESERVED
  • DATA7_1_RESERVED
  • DATA7_2_RESERVED
  • DATA7_5_RESERVED
  • DC_COUPLING_EXTERNAL_RESISTOR
  • DC_COUPLING_EXTERNAL_TERMINATION
  • DC_COUPLING_INTERNAL_100_OHMS
  • DC_CURRENT_FOR_ELECTROMIGRATION_CHECK
  • DCLK_PIN
  • DCLK_RESERVED
  • DDIO_INPUT_REGISTER
  • DDIO_OUTPUT_REGISTER_DISTANCE
  • DDIO_OUTPUT_REGISTER
  • DEBUG_BOUNDARY
  • DEBUG_TRACE
  • DECREASE_INPUT_DELAY_TO_INPUT_REGISTER
  • DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER
  • DEFAULT_DESIGN_ASSISTANT_SETTINGS
  • DEFAULT_DEVICE_OPTIONS
  • DEFAULT_EQUIVALENCE_CHECKER_SETTINGS
  • DEFAULT_HARDCOPY_SETTINGS
  • DEFAULT_HOLD_MULTICYCLE
  • DEFAULT_LOGIC_OPTIONS
  • DEFAULT_NETLIST_VIEWER_SETTINGS
  • DEFAULT_PARAMETERS
  • DEFAULT_SDC_FILE
  • DEFAULT_TIMING_REQUIREMENTS
  • DEFAULT_VALUE
  • DELAY_SETTING_FROM_CORE_TO_CE_INPUT_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_IO_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_OE_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_OUTPUT_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_OUTPUT_REGISTER
  • DELAY_SETTING_FROM_VIO_TO_CORE
  • DELAY_SETTING_TO_CORE_APEX20K
  • DELAY_SETTING_TO_CORE_DALI
  • DELAY_SETTING_TO_CORE_FLEX10K
  • DELAY_SETTING_TO_CORE_FLEX6K
  • DELAY_SETTING_TO_CORE_TO_OUTPUT_REGISTER
  • DELAY_SETTING_TO_CORE_TSUNAMI
  • DELAY_SETTING_TO_CORE_YEAGER
  • DELAY_SETTING_TO_INPUT_REGISTER
  • DELAY_SETTING_TO_OUTPUT_ENABLE
  • DELAY_SETTING_TO_OUTPUT
  • DELAY_SETTING_TO_ZBT
  • DEPENDENCY_FILE
  • DESIGN_ASSISTANT_ASSIGNMENT
  • DEV_FAMILY_ACEX1K
  • DEV_FAMILY_APEX20KC
  • DEV_FAMILY_APEX20KE
  • DEV_FAMILY_APEX20K
  • DEV_FAMILY_APEXII
  • DEV_FAMILY_ARMSTRONG
  • DEV_FAMILY_ARRIAIIGZ
  • DEV_FAMILY_ARRIAVGZ
  • DEV_FAMILY_ARRIAV
  • DEV_FAMILY_ASC
  • DEV_FAMILY_AURORA
  • DEV_FAMILY_BEDROCK
  • DEV_FAMILY_BS
  • DEV_FAMILY_CUDA
  • DEV_FAMILY_CYCLONE10LP
  • DEV_FAMILY_CYCLONEII
  • DEV_FAMILY_CYCLONEIVE
  • DEV_FAMILY_CYCLONEV
  • DEV_FAMILY_DALI
  • DEV_FAMILY_EMBEDDED_PROCESSOR
  • DEV_FAMILY_EPC1
  • DEV_FAMILY_EPC2
  • DEV_FAMILY_EXCALIBUR_ARM
  • DEV_FAMILY_FLASH_LOGIC
  • DEV_FAMILY_FLEX10KA
  • DEV_FAMILY_FLEX10KB
  • DEV_FAMILY_FLEX10KE
  • DEV_FAMILY_FLEX10K
  • DEV_FAMILY_FLEX6K
  • DEV_FAMILY_FLEX8000
  • DEV_FAMILY_FUSION
  • DEV_FAMILY_HCXIV
  • DEV_FAMILY_HCX
  • DEV_FAMILY_INTEL_CFI
  • DEV_FAMILY_MAX3000A
  • DEV_FAMILY_MAX7000AE
  • DEV_FAMILY_MAX7000A
  • DEV_FAMILY_MAX7000B
  • DEV_FAMILY_MAX7000S
  • DEV_FAMILY_MAX9000
  • DEV_FAMILY_MAXV
  • DEV_FAMILY_NADDER_EMULATOR
  • DEV_FAMILY_NADDER
  • DEV_FAMILY_NIGHTFURY
  • DEV_FAMILY_PIRANHA
  • DEV_FAMILY_SOC_SERIES_V
  • DEV_FAMILY_STINGRAY
  • DEV_FAMILY_STRATIXHC
  • DEV_FAMILY_STRATIXIIGX
  • DEV_FAMILY_STRATIXIIGXLITE
  • DEV_FAMILY_STRATIXV
  • DEV_FAMILY_SYN
  • DEV_FAMILY_TARPON
  • DEV_FAMILY_TGX
  • DEV_FAMILY_TITAN
  • DEV_FAMILY_TORNADO
  • DEV_FAMILY_TSUNAMI
  • DEV_FAMILY_VERMEER
  • DEV_FAMILY_VIRTUAL_JTAG_TAP
  • DEV_FAMILY_YEAGER
  • DEV_FAMILY_ZIPPLEBACK
  • DEVICE_FILTER_PACKAGE
  • DEVICE_FILTER_PIN_COUNT
  • DEVICE_FILTER_SPEED_GRADE
  • DEVICE_FILTER_VOLTAGE
  • DEVICE_INITIALIZATION_CLOCK
  • DEVICE_IO_STANDARD_APEX20KE
  • DEVICE_IO_STANDARD_APEX20KF
  • DEVICE_IO_STANDARD_APEX20K
  • DEVICE_IO_STANDARD_DALI
  • DEVICE_IO_STANDARD_FLEX10K
  • DEVICE_IO_STANDARD_FLEX6K
  • DEVICE_IO_STANDARD_MAX7000
  • DEVICE_IO_STANDARD_YEAGER
  • DEVICE_MIGRATION_LIST
  • DEVICE_TECHNOLOGY_MIGRATION_LIST
  • DEV_PART_GENERIC
  • DEV_PART_INVALID
  • DEV_PART_MAX
  • DFE_PI_BW_0P5GHZ
  • DFE_PI_BW_10GHZ
  • DFE_PI_BW_2P5GHZ
  • DFE_PI_BW_5GHZ
  • DIFFERENTIAL
  • DIRECT_FORMAT
  • DIRECT
  • DISABLE_CONF_DONE_AND_NSTATUS_ON_EPROM
  • DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE
  • DISABLE_CORE_CLK
  • DISABLE_DA_GX_RULE
  • DISABLE_DA_RULE
  • DISABLED
  • DISABLE_DSP_NEGATE_INFERENCING
  • DISABLE_EMBEDDED_TIMING_CONSTRAINT
  • DISABLE_MLAB_RAM_USE
  • DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE
  • DISABLE_OCP_HW_EVAL
  • DISABLE_PLL_COMPENSATION_DELAY_CHANGE_WARNING
  • DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
  • DISABLE_TRI
  • DISALLOW_GLOBAL_ASSIGNMENT_IN_QIP
  • DIV2
  • DIV4
  • DIVIDE_BASE_CLOCK_BY
  • DIVIDE_BASE_CLOCK_PERIOD_BY
  • DM_PIN
  • DO_COMBINED_ANALYSIS
  • DO_MIN_ANALYSIS
  • DO_MINMAX_ANALYSIS_USING_RISEFALL_DELAYS
  • DO_MIN_TIMING
  • DONT_AUTODISCOVER_CPP_FILES
  • DONT_CONVERT_TO_USER_FRIENDLY_STRING
  • DONT_COPY_TO_CREATED_COMPANION_REVISION
  • DONT_COPY_TO_NEW_FILE_FORMAT
  • DONT_COPY_TO_NEW_REVISION
  • DONT_MERGE_REGISTER
  • DONT_REUSE_REMOVED_ASSIGNMENT
  • DONT_TOUCH_USER_CELL
  • DO_POST_BUILD_COMMAND_LINE
  • DO_SYSTEM_FMAX
  • DP_1620
  • DP_2700
  • DP_5400
  • DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1
  • DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_DEEP_MODE_INPUT_EPXA4_10
  • DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_DEEP_MODE_OUTPUT_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_INPUT_EPXA1
  • DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10
  • DPRAM_INPUT_EPXA4_10
  • DPRAM_OTHER_SIGNALS_EPXA4_10
  • DPRAM_OUTPUT_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10
  • DPRAM_WIDE_MODE_INPUT_EPXA4_10
  • DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_WIDE_MODE_OUTPUT_EPXA4_10
  • DPRIO_CHANNEL_NUM
  • DPRIO_CRUCLK_NUM
  • DPRIO_INTERFACE_REG
  • DPRIO_NORMAL_STATUS
  • DPRIO_QUAD_NUM
  • DPRIO_QUAD_PLL_NUM
  • DPRIO_TX_PLL0_REFCLK_NUM
  • DPRIO_TX_PLL1_REFCLK_NUM
  • DPRIO_TX_PLL_NUM
  • DQ_GROUP
  • DQ_PIN
  • DQSB_DQS_PAIR
  • DQS_DELAY
  • DQS_ENABLE_DELAY_CHAIN
  • DQS_FREQUENCY
  • DQSOUT_DELAY_CHAIN
  • DQS_SHIFT
  • DQS_SYSTEM_CLOCK
  • DRC_DEADLOCK_STATE_LIMIT
  • DRC_DETAIL_MESSAGE_LIMIT
  • DRC_FANOUT_EXCEEDING
  • DRC_GATED_CLOCK_FEED
  • DRC_MAX_TOP_FANOUT
  • DRC_REPORT_FANOUT_EXCEEDING
  • DRC_REPORT_MAX_TOP_FANOUT
  • DRC_REPORT_TOP_FANOUT
  • DRC_TOP_FANOUT
  • DRC_VIOLATION_MESSAGE_LIMIT
  • DSE_SEND_REPORT_PANEL
  • DSE_SERVER_SEND_REPORTS
  • DSE_SERVER_URL
  • DSE_SYNTH_EXTRA_EFFORT_MODE
  • DSE_WORKER_ID
  • DSM_DFT_OUT
  • DSM_LSB_OUT
  • DSM_MSB_OUT
  • DSP_BLOCK_BALANCING_IMPLEMENTATION
  • DSP_BLOCK_BALANCING
  • DSPBUILDER_FILE
  • DUAL_FAST_REGIONAL_CLOCK
  • DUAL_IMAGES
  • DUAL_PURPOSE_CLOCK_PIN_DELAY
  • DUAL_REGIONAL_CLOCK
  • DUPLICATE_ATOM
  • DUPLICATE_LOGIC_EXTRACTION
  • DUPLICATE_REGISTER_EXTRACTION
  • DUP_LOGIC_EXTRACTION
  • DUP_REG_EXTRACTION
  • DYNAMIC_ATOM_CONNECTION
  • DYNAMIC_CTL
  • DYNAMIC_OCT_CONTROL_GROUP
  • E8H9
  • EARLY_CLOCK_LATENCY
  • ECO_ALLOW_ROUTING_CHANGES
  • ECO_OPTIMIZE_TIMING
  • ECO_REGENERATE_REPORT
  • ECO_TIMING_DRIVEN_COMPILE
  • EDA_BOARD_BOUNDARY_SCAN_OPERATION
  • EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL
  • EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL
  • EDA_BOARD_DESIGN_SYMBOL_TOOL
  • EDA_BOARD_DESIGN_TIMING_TOOL
  • EDA_BOARD_DESIGN_TOOL
  • EDA_DATA_FORMAT
  • EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
  • EDA_DESIGN_EXTRA_ALTERA_SIM_LIB
  • EDA_DESIGN_INSTANCE_NAME
  • EDA_ENABLE_GLITCH_FILTERING
  • EDA_ENABLE_IPUTF_MODE
  • EDA_ENABLE_OCV_TIMING_ANALYSIS
  • EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE
  • EDA_EXCALIBUR_SINGLE_SLICE
  • EDA_EXTRA_ELAB_OPTION
  • EDA_FLATTEN_BUSES
  • EDA_FORMAL_VERIFICATION_ALLOW_RETIMING
  • EDA_FORMAL_VERIFICATION_TOOL
  • EDA_FV_HIERARCHY
  • EDA_GENERATE_FUNCTIONAL_NETLIST
  • EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT
  • EDA_GENERATE_POWER_INPUT_FILE
  • EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT
  • EDA_GENERATE_SDF_OUTPUT_FILE
  • EDA_GENERATE_TIMING_CLOSURE_DATA
  • EDA_IBIS_EXTENDED_MODEL_SELECTOR
  • EDA_IBIS_MODEL_SELECTOR
  • EDA_IBIS_MUTUAL_COUPLING
  • EDA_IBIS_SPECIFICATION_VERSION
  • EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION
  • EDA_INPUT_DATA_FORMAT
  • EDA_INPUT_GND
  • EDA_INPUT_GND_NAME
  • EDA_INPUT_VCC
  • EDA_INPUT_VCC_NAME
  • EDA_IPFS_FILE
  • EDA_LAUNCH_CMD_LINE_TOOL
  • EDA_LAUNCH_TOOL
  • EDA_LMF_FILE
  • EDA_MAINTAIN_DESIGN_HIERARCHY
  • EDA_MAP_ILLEGAL_CHARACTERS
  • EDA_MAP_ILLEGAL
  • EDA_NATIVELINK_GENERATE_SCRIPT_ONLY
  • EDA_NATIVELINK_PORTABLE_FILE_PATHS
  • EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT
  • EDA_NATIVELINK_SIMULATION_TEST_BENCH
  • EDA_NETLIST_TYPE
  • EDA_NETLIST_WRITER_OUTPUT_DIR
  • EDA_OCV_CORE_DERATING_FACTOR
  • EDA_OCV_IO_DERATING_FACTOR
  • EDA_OUTPUT_DATA_FORMAT
  • EDA_RESYNTHESIS_TOOL
  • EDA_RTL_SIM_MODE
  • EDA_RTL_SIMULATION_RUN_SCRIPT
  • EDA_RTL_TEST_BENCH_FILE_NAME
  • EDA_RTL_TEST_BENCH_NAME
  • EDA_RTL_TEST_BENCH_RUN_FOR
  • EDA_RUN_TOOL_AUTOMATICALLY
  • EDA_SDC_FILE_NAME
  • EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
  • EDA_SHOW_LMF_MAPPING_MESSAGES
  • EDA_SHOW_LMF_MAPPING_MSGS
  • EDA_SIMULATION_RUN_SCRIPT
  • EDA_SIMULATION_TOOL
  • EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE
  • EDA_SIMULATION_VCD_OUTPUT_TCL_FILE
  • EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME
  • EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
  • EDA_TEST_BENCH_ENABLE_STATUS
  • EDA_TEST_BENCH_ENTITY_MODULE_NAME
  • EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB
  • EDA_TEST_BENCH_FILE
  • EDA_TEST_BENCH_FILE_NAME
  • EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY
  • EDA_TEST_BENCH_MODULE_NAME
  • EDA_TEST_BENCH_NAME
  • EDA_TEST_BENCH_RUN_FOR
  • EDA_TEST_BENCH_RUN_SIM_FOR
  • EDA_TEST_BENCH_SETTINGS
  • EDA_TIME_SCALE
  • EDA_TIMESCALE
  • EDA_TIMING_ANALYSIS_TOOL
  • EDA_TOOL_SETTINGS
  • EDA_TRUNCATE_HPATH
  • EDA_TRUNCATE_LONG_HIERARCHY_PATHS
  • EDA_USE_IBIS_RLC_TYPE
  • EDA_USE_LMF
  • EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY
  • EDA_USE_RISE_FALL_DELAYS
  • EDA_VHDL_ARCH_NAME
  • EDA_VHDL_LIBRARY
  • EDA_WAIT_FOR_GUI_TOOL_COMPLETION
  • EDA_WRITE_CONFIG
  • EDA_WRITE_DEVICE_CONTROL_PORTS
  • EDA_WRITE_NODES_FOR_POWER_ESTIMATION
  • EDA_WRITER_DONT_WRITE_TOP_ENTITY
  • EDIF_FILE
  • ELA_FILE
  • ELEMENT_INDEX
  • ELF_FILE
  • EMIF
  • EMIF_SOC_PHYCLK_ADVANCE_MODELING
  • EMPTY
  • ENABLE_ACCELERATED_INCREMENTAL_COMPILE
  • ENABLE_ADVANCED_IO_ANALYSIS
  • ENABLE_ADVANCED_IO_DELAY_CHAIN_OPTIMIZATION
  • ENABLE_ADVANCED_IO_TIMING
  • ENABLE_ADV_SEU_DETECTION
  • ENABLE_ALT2GXB_CONFIGURATION
  • ENABLE_APEX_FITTER_CHOICE
  • ENABLE_ASMI_FOR_FLASH_LOADER
  • ENABLE_ASM_OPTIONS_FILE
  • ENABLE_ATTEMPT_SIMILAR_PLACEMENT
  • ENABLE_AUTONOMOUS_PCIE_HIP
  • ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS
  • ENABLE_BENEFICIAL_SKEW_OPTIMIZATION
  • ENABLE_BOOT_SEL_PIN
  • ENABLE_BUS_HOLD_CIRCUITRY
  • ENABLE_BUS_HOLD
  • ENABLE_CHIP_WIDE_OE
  • ENABLE_CHIP_WIDE_RESET
  • ENABLE_CLOCK_LATENCY
  • ENABLE_COMPACT_REPORT_TABLE
  • ENABLE_CONFIGURATION_PINS
  • ENABLE_CORE_CLK
  • ENABLE_CRC_ERROR_PIN
  • ENABLE_CVPCIE_CONFDONE
  • ENABLE_CVP_CONFDONE
  • ENABLE_DA_RULE
  • ENABLE_DEVICE_WIDE_OE
  • ENABLE_DEVICE_WIDE_RESET
  • ENABLE_DISABLED_STRATIX_LVDS_MODES
  • ENABLE_DRC
  • ENABLE_DRC_SETTINGS
  • ENABLE_ED_CRC_CHECK
  • ENABLE_EXTRA_DQ_DELAY
  • ENABLE_FALLBACK_TO_EXTERNAL_FLASH
  • ENABLE_HOLD_BACK_OFF
  • ENABLE_HOLD_MULTICYCLE
  • ENABLE_HPS_INTERNAL_TIMING
  • ENABLE_INCREMENTAL_DESIGN
  • ENABLE_INCREMENTAL_REUSE
  • ENABLE_INCREMENTAL_SYNTHESIS
  • ENABLE_INIT_DONE_OUTPUT
  • ENABLE_IP_DEBUG
  • ENABLE_JTAG_BST_SUPPORT
  • ENABLE_JTAG_PIN_SHARING
  • ENABLE_LAB_SHARING_WITH_PARENT_PARTITION
  • ENABLE_LLIS
  • ENABLE_LOGIC_ANALYZER_INTERFACE
  • ENABLE_LOW_VOLT_MODE_FLEX10K
  • ENABLE_LOW_VOLT_MODE_FLEX6K
  • ENABLE_LOW_VOLT_MODE
  • ENABLE_M512
  • ENABLE_MERCURY_CDR
  • ENABLE_MIXED_PORT_RDW_OLD_DATA_FOR_RAM_WITH_TWO_CLOCKS
  • ENABLE_MULTITAP
  • ENABLE_NCEO_OUTPUT
  • ENABLE_NCE_PIN
  • ENABLE_NCONFIG_FROM_CORE
  • ENABLE_OCT_DONE
  • ENABLE_OCTDONE
  • ENABLE_PR_PINS
  • ENABLE_RAPID_RECOMPILE
  • ENABLE_RECOVERY_REMOVAL_ANALYSIS
  • ENABLE_REDUCED_MEMORY_MODE
  • ENABLE_SIGNALTAP
  • ENABLE_SMART_VOLTAGE_ID
  • ENABLE_SOURCE_MULTICYCLE_HOLD
  • ENABLE_SOURCE_MULTICYCLE
  • ENABLE_SPI_MODE_CHECK
  • ENABLE_SRC_HOLD_MULTICYCLE
  • ENABLE_SRC_MULTICYCLE
  • ENABLE_STATE_MACHINE_INFERENCE
  • ENABLE_STRATIX_II_DPA_DEBUG
  • ENABLE_STRATIXII_DPA_DEBUG
  • ENABLE_STRATIX_II_LVDS_LOOPBACK
  • ENABLE_STRATIXII_LVDS_LOOPBACK
  • ENABLE_STRICT_PRESERVATION
  • ENABLE_SYNCH_INPUT_REGISTER_1S25
  • ENABLE_TRI
  • ENABLE_UNUSED_RX_CLOCK_WORKAROUND
  • ENABLE_VREFA_PIN
  • ENABLE_VREFB_PIN
  • ENCRYPTED_LUTMASK
  • ENFORCE_CONFIGURATION_VCCIO
  • EN_SPI_IO_WEAK_PULLUP
  • EN_USER_IO_WEAK_PULLUP
  • EPROM_JTAG_CODE_APEX20K
  • EPROM_JTAG_CODE_DALI
  • EPROM_JTAG_CODE_FLEX10K
  • EPROM_JTAG_CODE_FLEX6K
  • EPROM_JTAG_CODE
  • EPROM_JTAG_CODE_YEAGER
  • EPROM_USE_CHECKSUM_AS_USERCODE
  • EQ_BW_1
  • EQ_BW_2
  • EQ_BW_3
  • EQ_BW_4
  • EQC_AUTO_BREAK_CONE
  • EQC_AUTO_COMP_LOOP_CUT
  • EQC_AUTO_INVERSION
  • EQC_AUTO_PORTSWAP
  • EQC_AUTO_TERMINATE
  • EQC_BBOX_MERGE
  • EQC_CONSTANT_DFF_DETECTION
  • EQC_DETECT_DONT_CARES
  • EQC_DFF_SS_EMULATION
  • EQC_DUPLICATE_DFF_DETECTION
  • EQC_ENUM_AUTO_BREAK_CONE
  • EQC_ENUM_AUTO_COMP_LOOP_CUT
  • EQC_ENUM_AUTO_INVERSION
  • EQC_ENUM_AUTO_PORTSWAP
  • EQC_ENUM_AUTO_TERMINATE
  • EQC_ENUM_BBOX_MERGE
  • EQC_ENUM_CONSTANT_DFF_DETECTION
  • EQC_ENUM_DETECT_DONT_CARES
  • EQC_ENUM_DFF_SS_EMULATION
  • EQC_ENUM_DUPLICATE_DFF_DETECTION
  • EQC_ENUM_IO_BUFFER_CONVERSION
  • EQC_ENUM_LVDS_MERGE
  • EQC_ENUM_MAC_REGISTER_UNPACK
  • EQC_ENUM_MANUAL_MAP_LIST
  • EQC_ENUM_MAX_BDD_NODES
  • EQC_ENUM_PARAMETER_CHECK
  • EQC_ENUM_POWER_UP_COMPARE
  • EQC_ENUM_RAM_REGISTER_UNPACK
  • EQC_ENUM_RAM_UNMERGING
  • EQC_ENUM_RENAMING_RULES
  • EQC_ENUM_RENAMING_RULES_LIST
  • EQC_ENUM_SET_PARTITION_BB_TO_VCC_GND
  • EQC_ENUM_SHOW_ALL_MAPPED_POINTS
  • EQC_ENUM_STRUCTURE_MATCHING
  • EQC_ENUM_SUB_CONE_REPORT
  • EQC_LVDS_MERGE
  • EQC_MAC_REGISTER_UNPACK
  • EQC_PARAMETER_CHECK
  • EQC_POWER_UP_COMPARE
  • EQC_RAM_REGISTER_UNPACK
  • EQC_RAM_UNMERGING
  • EQC_RENAMING_RULES
  • EQC_RENAMING_RULES_LIST
  • EQC_SET_PARTITION_BB_TO_VCC_GND
  • EQC_SHOW_ALL_MAPPED_POINTS
  • EQC_STRUCTURE_MATCHING
  • EQC_SUB_CONE_REPORT
  • EQUATION_FILE
  • EQUIVALENCE_CHECKER_ASSIGNMENT
  • EQZP_DIS_PEAKING
  • EQZP_EN_PEAKING
  • ERROR_CHECK_FREQUENCY_DIVISOR
  • ESTIMATE_POWER_CONSUMPTION
  • EXCALIBUR_CONFIGURATION_DEVICE
  • EXCALIBUR_CONFIGURATION_SCHEME
  • EXC_BUSTRANS_SIM_FILE
  • EXCLUDE_FMAX_PATHS_GREATER_THAN
  • EXCLUDE_SLACK_PATHS_GREATER_THAN
  • EXCLUDE_TCO_PATHS_LESS_THAN
  • EXCLUDE_TH_PATHS_LESS_THAN
  • EXCLUDE_TPD_PATHS_LESS_THAN
  • EXCLUDE_TSU_PATHS_LESS_THAN
  • EXCLUSIVE_IO_GROUP
  • EXPANDED
  • EXTENDS_TOP_BLOCK
  • EXTERNAL_FEEDBACK
  • EXTERNAL_FLASH_FALLBACK_ADDRESS
  • EXTERNAL_INPUT_DELAY
  • EXTERNAL
  • EXTERNAL_LVDS_RX_USES_DPA
  • EXTERNAL_OUTPUT_DELAY
  • EXTERNAL_PIN_CONNECTION
  • EXTRACT_AND_OPTIMIZE_BUS_MUXES
  • EXTRACT_VERILOG_STATE_MACHINES
  • EXTRACT_VHDL_STATE_MACHINES
  • EXTRA_EFFORT
  • EXTRA
  • EYEQ_BW_1G_TO_2P5G
  • EYEQ_BW_2P5G_TO_7P5G
  • EYEQ_BW_GREATER_THAN_7P5G
  • EYEQ_BW_LESS_THAN_1G
  • F10K_ACEX1K_PCI_LOW_CAP
  • FALLBACK_TO_EXTERNAL_FLASH
  • FALL
  • FALSE
  • FANIN_PER_CELL_MAX7000
  • FAP_NAME
  • FAR_GLOBAL_CLOCK
  • FAR_REGIONAL_CLOCK
  • FAST_FIT_COMPILATION
  • FAST_FIT
  • FAST_INPUT_REGISTER
  • FAST_IO
  • FAST
  • FAST_OCT_REGISTER
  • FAST_OUTPUT_ENABLE_REGISTER
  • FAST_OUTPUT_REGISTER
  • FAST_PASSIVE_PARALLEL
  • FAST_POR_DELAY
  • FASTROW_INTERCONNECT
  • FAST_VIO
  • FBCLK_COUNTER_OUT
  • FFFFFFFF
  • FINAL_PLACEMENT_OPTIMIZATION
  • FIR_POST_1T_NEG
  • FIR_POST_1T_POS
  • FIR_POST_2T_NEG
  • FIR_POST_2T_POS
  • FIR_PRE_1T_NEG
  • FIR_PRE_1T_POS
  • FIR_PRE_2T_NEG
  • FIR_PRE_2T_POS
  • FIT_ATTEMPTS_TO_SKIP
  • FIT_INI_VARS
  • FIT_ONLY_ONE_ATTEMPT
  • FIT_SCRIPT_FILE
  • FIT_SEED
  • FIT_SMART_IO
  • FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND
  • FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION
  • FITTER_ASSIGNMENT
  • FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN
  • FITTER_EARLY_TIMING_ESTIMATE_MODE
  • FITTER_EFFORT
  • FITTER_ONLY
  • FITTER_OPTIMIZED
  • FITTER_PLL_SCAN_CHAIN_RECONFIG_FILE
  • FITTER_TCL_CALLBACK_FILE
  • FITTER_WILDARDS
  • FITTER_WILDCARDS
  • FIT_WYSIWYG_PIA
  • FLASH_NCE_RESERVED
  • FLASH_PROGRAMMING_FILE_NAME
  • FLEX10K_CARRY_CHAIN_LENGTH
  • FLEX10K_CLIQUE_TYPE
  • FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE
  • FLEX10K_CONFIGURATION_DEVICE
  • FLEX10K_CONFIGURATION_SCHEME
  • FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • FLEX10K_DEVICE_IO_STANDARD
  • FLEX10K_ENABLE_LOCK_OUTPUT
  • FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
  • FLEX10KE_PCI_LOW_CAP_ADJUST
  • FLEX10K_JTAG_USER_CODE
  • FLEX10K_MAX_PERIPHERAL_OE
  • FLEX10K_OPTIMIZATION_TECHNIQUE
  • FLEX10K_TECHNOLOGY_MAPPER
  • FLEX6000
  • FLEX6K_CARRY_CHAIN_LENGTH
  • FLEX6K_CLIQUE_TYPE
  • FLEX6K_CONFIG_DEVICE_JTAG_USER_CODE
  • FLEX6K_CONFIGURATION_DEVICE
  • FLEX6K_CONFIGURATION_SCHEME
  • FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • FLEX6K_DEVICE_IO_STANDARD
  • FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
  • FLEX6K_JTAG_USER_CODE
  • FLEX6K_LOCAL_ROUTING_DESTINATION
  • FLEX6K_LOCAL_ROUTING_SOURCE
  • FLEX6K_OPTIMIZATION_TECHNIQUE
  • FLEX6K_TECHNOLOGY_MAPPER
  • FLEXIBLE_TIMING
  • FLOATING
  • FLOW_DISABLE_ASSEMBLER
  • FLOW_ENABLE_HC_COMPARE
  • FLOW_ENABLE_HCII_COMPARE
  • FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD
  • FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS
  • FLOW_ENABLE_PARALLEL_MODULES
  • FLOW_ENABLE_POWER_ANALYZER
  • FLOW_ENABLE_RTL_VIEWER
  • FLOW_ENABLE_TIMING_CONSTRAINT_CHECK
  • FLOW_HARDCOPY_DESIGN_READINESS_CHECK
  • FMAX_REQUIREMENT
  • FOCUS_ENTITY_NAME
  • FORCE_ALL_TILES_WITH_FAILING_TIMING_PATHS_TO_HIGH_SPEED
  • FORCE_ALL_USED_TILES_TO_HIGH_SPEED
  • FORCED_IF_ASYNCHRONOUS
  • FORCED
  • FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS
  • FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION
  • FORCE_MERGE_PLL_FANOUTS
  • FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION
  • FORCE_POINT_TO_POINT
  • FORCE_RECOMPILE
  • FORCE_SLACK
  • FORCE_SSMCLK_TO_ISMCLK
  • FORCE_SYNCH_CLEAR
  • FORM_DDR_CLUSTERING_CLIQUE
  • FPLL
  • FPLL_VREG1_BOOST_1_STEP
  • FPLL_VREG1_BOOST_2_STEP
  • FPLL_VREG1_BOOST_3_STEP
  • FPLL_VREG1_BOOST_4_STEP
  • FPLL_VREG1_BOOST_5_STEP
  • FPLL_VREG1_BOOST_6_STEP
  • FPLL_VREG1_BOOST_7_STEP
  • FPLL_VREG1_NO_VOLTAGE_BOOST
  • FPLL_VREG_NO_VOLTAGE_BOOST
  • FREQ_12_5MHZ
  • FREQ_20MHZ
  • FREQ_40MHZ
  • FSDA_LEVEL_AUTO
  • FSDA_LEVEL_C1
  • FSDA_LEVEL_C2
  • FSDA_LEVEL_U
  • FSM_CAT
  • FSM_RULE_DEADLOCK_STATE
  • FSM_RULE_NO_RESET_STATE
  • FSM_RULE_NO_SZER_ACLK_DOMAIN
  • FSM_RULE_UNREACHABLE_STATE
  • FSM_RULE_UNUSED_TRANSITION
  • FSYN_AND_ICP_REGTEST_MODE
  • FULL_COMPILATION
  • FULL_INCREMENTAL_COMPILATION
  • FULL_INCREMENTAL_DESIGN
  • FULL_VPACK
  • FULL_VPR
  • FUNCTIONAL
  • FV_BLACKBOX
  • G8A94
  • G8H9
  • GBE_1250
  • GDF_FILE
  • GEN3_OFF
  • GEN3_ON
  • GEN4_OFF
  • GEN4_ON
  • GENERAL_POOL
  • GENERATE_CONFIG_HEXOUT_FILE
  • GENERATE_CONFIG_ISC_FILE
  • GENERATE_CONFIG_JAM_FILE
  • GENERATE_CONFIG_JBC_FILE_COMPRESSED
  • GENERATE_CONFIG_JBC_FILE
  • GENERATE_CONFIG_SVF_FILE
  • GENERATE_GXB_RECONFIG_MIF
  • GENERATE_GXB_RECONFIG_MIF_WITH_PLL
  • GENERATE_HEX_FILE
  • GENERATE_ISC_FILE
  • GENERATE_JAM_FILE
  • GENERATE_JBC_FILE_COMPRESSED
  • GENERATE_JBC_FILE
  • GENERATE_PMSF_FILES
  • GENERATE_RBF_FILE
  • GENERATE_SVF_FILE
  • GENERATE_TTF_FILE
  • GENERATION_DIRECTORY
  • GENERIC_TRAIT
  • GIGE
  • GIVE_ERROR
  • GIVE_INFO
  • GIVE_WARNING
  • GLITCH_DETECTION
  • GLITCH_DETECTION_PULSE
  • GLITCH_INTERVAL
  • GLOBAL_SIGNAL_CLKCTRL_LOCATION
  • GNDIO_CURRENT_1PT8V
  • GNDIO_CURRENT_2PT5V
  • GNDIO_CURRENT_GTL
  • GNDIO_CURRENT_GTL_PLUS
  • GNDIO_CURRENT_LVCMOS
  • GNDIO_CURRENT_LVTTL
  • GNDIO_CURRENT_PCI
  • GNDIO_CURRENT_SSTL2_CLASS1
  • GNDIO_CURRENT_SSTL2_CLASS2
  • GNDIO_CURRENT_SSTL3_CLASS1
  • GNDIO_CURRENT_SSTL3_CLASS2
  • GNU_ASM_COMMAND_LINE
  • GNU_CPP_COMMAND_LINE
  • GNU_CSP_ASM_COMMAND_LINE
  • GNU_CSP_CPP_COMMAND_LINE
  • GNU_CSP_LINK_COMMAND_LINE
  • GNU_LINK_COMMAND_LINE
  • GNUPRO_ARM_ASM_COMMAND_LINE
  • GNUPRO_ARM_CPP_COMMAND_LINE
  • GNUPRO_ARM_LINK_COMMAND_LINE
  • GNUPRO_MIPS_ASM_COMMAND_LINE
  • GNUPRO_MIPS_CPP_COMMAND_LINE
  • GNUPRO_MIPS_LINK_COMMAND_LINE
  • GNUPRO_NIOS_ASM_COMMAND_LINE
  • GNUPRO_NIOS_CPP_COMMAND_LINE
  • GNUPRO_NIOS_LINK_COMMAND_LINE
  • GPH9
  • GPON_1244
  • GPON_155
  • GPON_2488
  • GPON_622
  • GROUNDED
  • GROUP_COMB_LOGIC_IN_CLOUD
  • GROUP_COMB_LOGIC_IN_CLOUD_TMV
  • GROUP_NODES
  • GROUP_NODES_TMV
  • GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME
  • GXB_0PPM_CLOCK_GROUP_DRIVER
  • GXB_0PPM_CLOCK_GROUP
  • GXB_0PPM_CORECLK
  • GXB_0PPM_CORE_CLOCK
  • GXB_CLOCK_GROUP_DRIVER
  • GXB_CLOCK_GROUP
  • GXB_IO_PIN_TERMINATION
  • GXB_RECONFIG_GROUP
  • GXB_RECONFIG_MIF_PLL
  • GXB_REFCLK_COUPLING_TERMINATION_SETTING
  • GXB_REFCLK_PIN_TERMINATION
  • GXB_RESERVED_TRANSMIT_CHANNEL
  • GXB_TX_PLL_RECONFIG_GROUP
  • GXB_VCCA_VOLTAGE
  • GXB_VCCR_VCCT_VOLTAGE
  • HALF
  • HALF_MEGALAB_COLUMN
  • HALF_RESOLUTION
  • HALF_ROW
  • HARD_BLOCK_PARTITION
  • HARDCOPY_DEVICE_IDENTIFIER
  • HARDCOPY_EXTERNAL_CLOCK_JITTER
  • HARDCOPY_FLOW_AUTOMATION
  • HARDCOPYII_COMPANION_REVISION_NAME
  • HARDCOPYII_POWER_ON_EXTRA_DELAY
  • HARDCOPYII_RUN_COMPARISON_ON_EVERY_COMPILE
  • HARDCOPYII_SAVE_MIGRATION_INFO_DURING_COMPILATION
  • HARDCOPY_INDIVIDUAL_SETTINGS
  • HARDCOPY_INPUT_TRANSITION_CLOCK_PIN
  • HARDCOPY_INPUT_TRANSITION_DATA_PIN
  • HARDCOPY_NEW_PROJECT_PATH
  • HARD_POST_FIT
  • HCII_OUTPUT_DIR
  • HC_OUTPUT_DIR
  • HCPY_ALOAD_SIGNALS
  • HCPY_ASYN_RAM
  • HCPY_CAT
  • HCPY_EXCEED_RAM_USAGE
  • HCPY_EXCEED_USER_IO_USAGE
  • HCPY_EXT_CLK_JITTER_CHECK
  • HCPY_EXT_CLK_JITTER_EDGE
  • HCPY_EXT_CLK_JITTER
  • HCPY_ILLEGAL_HC_DEV_PKG
  • HCPY_INPUT_TRANS_CLK_PIN
  • HCPY_INPUT_TRANS_DATA_PIN
  • HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES
  • HCPY_TRANS_CONDITION_CLK_PIN
  • HCPY_TRANS_CONDITION_DATA_PIN
  • HCPY_TRANS_EDGE_CLK_PIN
  • HCPY_TRANS_EDGE_DATA_PIN
  • HCPY_VREF_PINS
  • HDL_INITIAL_FANOUT_LIMIT
  • HDL_INTERFACE_INSTANCE_ENTITY
  • HDL_INTERFACE_INSTANCE_NAME
  • HDL_INTERFACE_INSTANCE_PARAMETERS
  • HDL_INTERFACE_OUTPUT_PATH
  • HDL_MESSAGE_LEVEL
  • HDL_MESSAGE_OFF
  • HDL_MESSAGE_ON
  • HDL_SETTINGS
  • HDL_VERSION
  • HEX_FILE_COUNT_UP_DOWN
  • HEX_FILE_COUNT_UP_OR_DOWN
  • HEX_FILE_START_ADDRESS
  • HEXOUT_FILE_COUNT_DIRECTION
  • HEXOUT_FILE_START_ADDRESS
  • HEX_OUTPUT_FILE
  • HIDE_RCF_WARNINGS
  • HIERARCHICAL_COMPILE
  • HIERARCHY_BLACKBOX_FILE
  • HIGH_PERF
  • HIGH_PERFORMANCE_EFFORT
  • HIGH_POWER_EFFORT
  • HIGH_VCM
  • HIGIG_4062
  • HIGIG_5000
  • HIGIG_6250
  • HIGIG_6562
  • HOLD_MULTICYCLE_DEFAULT
  • HOLD_RELATIONSHIP
  • HPS_AUTO_PARTITION
  • HPS_EARLY_IO_RELEASE
  • HPS_IO
  • HPS_ISW_FILE
  • HPS_LOCATION
  • HPS_PARTITION
  • HSSI_A10_CDR_PLL_ANALOG_MODE
  • HSSI_A10_CDR_PLL_POWER_MODE
  • HSSI_A10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • HSSI_A10_CDR_PLL_UC_RO_CAL
  • HSSI_A10_CMU_FPLL_ANALOG_MODE
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • HSSI_A10_CMU_FPLL_POWER_MODE
  • HSSI_A10_LC_PLL_ANALOG_MODE
  • HSSI_A10_LC_PLL_POWER_MODE
  • HSSI_A10_PM_UC_CLKDIV_SEL
  • HSSI_A10_PM_UC_CLKSEL_CORE
  • HSSI_A10_PM_UC_CLKSEL_OSC
  • HSSI_A10_REFCLK_TERM_TRISTATE
  • HSSI_A10_RX_ADAPT_DFE_CONTROL_SEL
  • HSSI_A10_RX_ADAPT_DFE_SEL
  • HSSI_A10_RX_ADAPT_VGA_SEL
  • HSSI_A10_RX_ADAPT_VREF_SEL
  • HSSI_A10_RX_ADP_CTLE_ACGAIN_4S
  • HSSI_A10_RX_ADP_CTLE_EQZ_1S_SEL
  • HSSI_A10_RX_ADP_DFE_FLTAP_POSITION
  • HSSI_A10_RX_ADP_DFE_FXTAP10
  • HSSI_A10_RX_ADP_DFE_FXTAP10_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP11
  • HSSI_A10_RX_ADP_DFE_FXTAP11_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP1
  • HSSI_A10_RX_ADP_DFE_FXTAP2
  • HSSI_A10_RX_ADP_DFE_FXTAP2_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP3
  • HSSI_A10_RX_ADP_DFE_FXTAP3_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP4
  • HSSI_A10_RX_ADP_DFE_FXTAP4_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP5
  • HSSI_A10_RX_ADP_DFE_FXTAP5_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP6
  • HSSI_A10_RX_ADP_DFE_FXTAP6_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP7
  • HSSI_A10_RX_ADP_DFE_FXTAP7_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP8
  • HSSI_A10_RX_ADP_DFE_FXTAP8_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP9
  • HSSI_A10_RX_ADP_DFE_FXTAP9_SGN
  • HSSI_A10_RX_ADP_LFEQ_FB_SEL
  • HSSI_A10_RX_ADP_ONETIME_DFE
  • HSSI_A10_RX_ADP_VGA_SEL
  • HSSI_A10_RX_ADP_VREF_SEL
  • HSSI_A10_RX_BYPASS_EQZ_STAGES_234
  • HSSI_A10_RX_EQ_BW_SEL
  • HSSI_A10_RX_EQ_DC_GAIN_TRIM
  • HSSI_A10_RX_INPUT_VCM_SEL
  • HSSI_A10_RX_LINK
  • HSSI_A10_RX_OFFSET_CANCELLATION_CTRL
  • HSSI_A10_RX_ONE_STAGE_ENABLE
  • HSSI_A10_RX_POWER_MODE
  • HSSI_A10_RX_QPI_ENABLE
  • HSSI_A10_RX_RX_SEL_BIAS_SOURCE
  • HSSI_A10_RX_SD_OUTPUT_OFF
  • HSSI_A10_RX_SD_OUTPUT_ON
  • HSSI_A10_RX_SD_THRESHOLD
  • HSSI_A10_RX_TERM_SEL
  • HSSI_A10_RX_TERM_TRI_ENABLE
  • HSSI_A10_RX_UC_RX_DFE_CAL
  • HSSI_A10_RX_VCCELA_SUPPLY_VOLTAGE
  • HSSI_A10_RX_VCM_CURRENT_ADD
  • HSSI_A10_RX_VCM_SEL
  • HSSI_A10_RX_XRX_PATH_ANALOG_MODE
  • HSSI_A10_TX_COMPENSATION_EN
  • HSSI_A10_TX_DCD_DETECTION_EN
  • HSSI_A10_TX_DPRIO_CGB_VREG_BOOST
  • HSSI_A10_TX_LINK
  • HSSI_A10_TX_LOW_POWER_EN
  • HSSI_A10_TX_POWER_MODE
  • HSSI_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • HSSI_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • HSSI_A10_TX_RES_CAL_LOCAL
  • HSSI_A10_TX_RX_DET
  • HSSI_A10_TX_RX_DET_OUTPUT_SEL
  • HSSI_A10_TX_RX_DET_PDB
  • HSSI_A10_TX_SLEW_RATE_CTRL
  • HSSI_A10_TX_TERM_CODE
  • HSSI_A10_TX_TERM_SEL
  • HSSI_A10_TX_UC_DCD_CAL
  • HSSI_A10_TX_UC_GEN3
  • HSSI_A10_TX_UC_GEN4
  • HSSI_A10_TX_UC_SKEW_CAL
  • HSSI_A10_TX_UC_TXVOD_CAL_CONT
  • HSSI_A10_TX_UC_TXVOD_CAL
  • HSSI_A10_TX_UC_VCC_SETTING
  • HSSI_A10_TX_USER_FIR_COEFF_CTRL_SEL
  • HSSI_A10_TX_VOD_OUTPUT_SWING_CTRL
  • HSSI_A10_TX_XTX_PATH_ANALOG_MODE
  • HSSI_ADCE_RGEN_MODE
  • HSSI_ANALOG_SETTINGS_PROTOCOL
  • HSSI_FAST_LOCK_MODE
  • HSSI_GT_FORCE_VCO_CONST
  • HSSI_GT_RX_CTLE
  • HSSI_GT_RX_RX_DC_GAIN
  • HSSI_GT_RX_VCM_SEL
  • HSSI_GT_TERMINATION
  • HSSI_GT_TX_COMMON_MODE_DRIVER_SEL
  • HSSI_GT_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_GT_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP
  • HSSI_GT_TX_SIG_INV_PRE_TAP
  • HSSI_GT_TX_VOD_SWITCHING_CTRL_MAIN_TAP
  • HSSI_ODI_EYE_MONITOR_BW_SEL
  • HSSI_PARAMETER
  • HSSI_REFCLK_TERMINATION
  • HSSI_RX_ACGAIN_A
  • HSSI_RX_ACGAIN_V
  • HSSI_RX_ADCE_HSF_HFBW
  • HSSI_RX_ADCE_RGEN_BW
  • HSSI_RX_BYPASS_EQZ_STAGES_234
  • HSSI_RX_CT_EQUALIZER_SETTING
  • HSSI_RX_DFE_PI_BW
  • HSSI_RX_ENABLE_RX_GAINCTRL_PCIEMODE
  • HSSI_RX_EQ_BW_SEL
  • HSSI_RX_INPUT_VCM_SEL
  • HSSI_RX_PDB_SD
  • HSSI_RX_PMOS_GAIN_PEAK
  • HSSI_RX_QPI_ENABLE
  • HSSI_RX_RX_DC_GAIN
  • HSSI_RX_RX_SEL_BIAS_SOURCE
  • HSSI_RX_SD_OFF
  • HSSI_RX_SD_ON
  • HSSI_RX_SD_THRESHOLD
  • HSSI_RX_SEL_HALF_BW
  • HSSI_RX_VCCELA_SUPPLY_VOLTAGE
  • HSSI_RX_VCM_CURRENT_ADD
  • HSSI_RX_VCM_SEL
  • HSSI_TERMINATION
  • HSSI_TX_COMMON_MODE_DRIVER_SEL
  • HSSI_TX_DRIVER_RESOLUTION_CTRL
  • HSSI_TX_FIR_COEFF_CTRL_SEL
  • HSSI_TX_LOCAL_IB_CTL
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP_USER
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_USER
  • HSSI_TX_QPI_EN
  • HSSI_TX_RX_DET
  • HSSI_TX_RX_DET_OUTPUT_SEL
  • HSSI_TX_RX_DET_PDB
  • HSSI_TX_SIG_INV_2ND_TAP
  • HSSI_TX_SIG_INV_PRE_TAP
  • HSSI_TX_SLEW_RATE_CTRL
  • HSSI_TX_SWING_BOOST
  • HSSI_TX_VCM_CTRL_SEL
  • HSSI_TX_VCM_CURRENT_ADDL
  • HSSI_TX_VOD_BOOST
  • HSSI_TX_VOD_SWITCHING_CTRL_MAIN_TAP
  • HSSI_VCCEH_VOLTAGE
  • HSSI_VCCER_VCCET_VOLTAGE
  • HTML_FILE
  • HTML_REPORT_FILE
  • HUB_AUTO_INSERT
  • HUB_ENTITY_NAME
  • HUB_INSTANCE_NAME
  • HUB_SOURCE_FILE
  • HYBRID_FLOW_NEW_EXTRACTOR
  • HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS
  • HYPER_AWARE_OPTIMIZE_SHORT_PATHS
  • HYPER_AWARE_OPTIMIZE_TIMING
  • HYPER_AWARE_REGISTER_PLACEMENT
  • HYPER_AWARE_SET_REGISTER_BYPASS
  • HYPER_AWARE_SET_REGISTER_INITIAL_STATE
  • HYPER_EARLY_RETIMER
  • HYPER_REGISTER
  • HYPER_RETIMER_ADD_PIPELINING
  • HYPER_RETIMER_FALSE_PATH_RESTRICTION
  • HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING
  • HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX
  • HYPER_RETIMER_FAST_FORWARD_AGGRESSIVE_EXPLORATION
  • HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR
  • HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_ADD_PIPELINING
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_AGGRESSIVE_EXPLORATION
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_ASYNCH_CLEAR
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_USER_PRESERVE_RESTRICTION
  • HYPER_RETIMER_FAST_FORWARD
  • HYPER_RETIMER_FAST_FORWARD_OFF_DESCRIPTION
  • HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS
  • HYPER_RETIMER_FAST_FORWARD_TARGET_MAX_PERFORMANCE
  • HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION
  • HYPER_RETIMER
  • HYPER_RETIMER_REGISTERS_REMOVED
  • IB_22OHM
  • IB_29OHM
  • IB_42OHM
  • IB_49OHM
  • IEEE_10G_BASE_CR_10312
  • IEEE_10G_KR_10312
  • IEEE_40G_BASE_KR_10312
  • IGNORE_CARRY_BUFFERS
  • IGNORE_CARRY
  • IGNORE_CASCADE_BUFFERS
  • IGNORE_CASCADE
  • IGNORE_CLOCK_SETTINGS
  • IGNORE_DUPLICATE_DESIGN_ENTITY
  • IGNORE_GLOBAL_BUFFERS
  • IGNORE_GLOBAL
  • IGNORE_HSSI_COLUMN_POWER_FOR_BTI_MITIGATION
  • IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS
  • IGNORE_LCELL
  • IGNORE_LCELL_MAX7000
  • IGNORE_MAX_FANOUT_ASSIGNMENTS
  • IGNORE_MODE_FOR_MERGE
  • IGNORE_PARTITIONS
  • IGNORE_ROW_GLOBAL_BUFFERS
  • IGNORE_ROW_GLOBAL
  • IGNORE_SOFT
  • IGNORE_SOFT_MAX7000
  • IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
  • IGNORE_TRANSLATE_OFF
  • IGNORE_VERILOG_INITIAL_CONSTRUCTS
  • IGNORE_VREF_RESTRICTION
  • IMMEDIATE_ASSERTION_FAIL_ACTION
  • IMMEDIATE_ASSERTION_FAIL_MESSAGE
  • IMMEDIATE_ASSERTION
  • IMMEDIATE_ASSERTION_PASS_MESSAGE
  • IMMEDIATE_ASSERTION_STATE
  • IMMEDIATE_ASSERTION_TEST_CONDITION
  • IMPLEMENT_AS_CLOCK_ENABLE
  • IMPLEMENT_AS_LCELL
  • IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL
  • IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE
  • IMPORT_BASED_POST_FIT
  • IMPORT_BLOCK
  • IMPORTED
  • IMPORT
  • INCLUDED_IN_OLD_CHIP_SECTION
  • INCLUDED_IN_OLD_PROJECT_INFO_SECTION
  • INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
  • INCLUDE_IN_ALL_TB2
  • INCLUDE_IN_COMPILER_REPORT
  • INCLUDE_IN_FITTER_TB2
  • INCLUDE_IN_POWER_TB2
  • INCLUDE_IN_SIMULATOR_REPORT
  • INCLUDE_IN_SYNTHESIS_REPORT
  • INCLUDE_IN_SYNTHESIS_TB2
  • INCLUDE_IN_TIMING_TB2
  • INCLUDE_PATHS_GREATER_THAN_TCO
  • INCLUDE_PATHS_GREATER_THAN_TH
  • INCLUDE_PATHS_GREATER_THAN_TPD
  • INCLUDE_PATHS_GREATER_THAN_TSU
  • INCLUDE_PATHS_LESS_THAN_FMAX
  • INCLUDE_PATHS_LESS_THAN_SLACK
  • INCLUDE_PIN_DELAYS_IN_CALCULATIONS
  • INC_PLACE_PREF_LOCATION
  • INC_PLC_MODE
  • INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN
  • INCREASE_DELAY_TO_OUTPUT_PIN
  • INCREASE_INPUT_CLOCK_ENABLE_DELAY
  • INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER
  • INCREASE_OUTPUT_CLOCK_ENABLE_DELAY
  • INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY
  • INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAYR
  • INCREASE_TZX_DELAY_TO_OUTPUT_PIN
  • INCREMENTAL_COMPILATION_EXPORT_FILE
  • INCREMENTAL_COMPILATION_EXPORT_FLATTEN
  • INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE
  • INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME
  • INCREMENTAL_COMPILATION_EXPORT_POST_FIT
  • INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH
  • INCREMENTAL_COMPILATION_EXPORT_ROUTING
  • INCREMENTAL_DESIGN_PARTITION
  • INCREMENTAL_INPUT_VECTOR_FILE
  • INCREMENTAL_SYNTHESIS_FULL
  • INCREMENTAL_SYNTHESIS_PARTITION
  • INCREMENTAL_SYNTHESIS_TOP
  • INCREMENTAL_TIME_INPUT
  • INCREMENTAL_VECTOR_INPUT_SOURCE
  • INCR_SIGNALTAP_PARTITION
  • INCR_TAP
  • INDIRECT_PORT_ASSIGNMENT
  • INERTIAL
  • INFER_RAMS_FROM_RAW_LOGIC
  • INIT_CLKUSR
  • INIT_DCLK
  • INIT_DONE_OPEN_DRAIN
  • INITIAL_PLACEMENT_CONFIGURATION
  • INIT_INTOSC
  • INNER_NUM
  • INPUT_DELAY_CHAIN
  • INPUT_EDGE
  • INPUT_MAX_DELAY
  • INPUT_MIN_DELAY
  • INPUT_OCT_VALUE
  • INPUT_PERSONA
  • INPUT_REFERENCE
  • INPUT_TERMINATION
  • INPUT_TRANSITION_TIME
  • INSERT_ADDITIONAL_LOGIC_CELL
  • INSERT_BOUNDARY_WIRE_LUTS
  • INSTANT_ON
  • INTERFACE_ROLE
  • INTERFACES
  • INTERFACE_TYPE
  • INTERLAKEN_11100
  • INTERLAKEN_12500
  • INTERLAKEN_3125
  • INTERLAKEN_6375
  • INTERLAKEN
  • INTERNAL_CONFIGURATION
  • INTERNAL_FLASH_UPDATE_MODE
  • INTERNAL_OSCILLATOR_DIVIDE_DOWN
  • INTERNAL_SCRUBBING
  • INTERNAL_VREF_MODE
  • INVERT_BASE_CLOCK
  • INVERTED_CLOCK
  • IO_12_LANE_INPUT_DATA_DELAY_CHAIN
  • IO_12_LANE_INPUT_DATA_DELAY
  • IO_12_LANE_INPUT_STROBE_DELAY_CHAIN
  • IO_12_LANE_INPUT_STROBE_DELAY
  • IOBANK
  • IOBANK_VCCIO
  • IO_MAXIMUM_TOGGLE_RATE
  • IO_PATHS_AND_MINIMUM_TPD_PATHS
  • IO_PLACEMENT_OPTIMIZATION
  • IOPLL
  • IO_SSO_CHECKING
  • IP_ADVISOR_FILE
  • IPA_FILE
  • IP_COMPONENT_AUTHOR
  • IP_COMPONENT_DESCRIPTION
  • IP_COMPONENT_DISPLAY_NAME
  • IP_COMPONENT_DOCUMENTATION_LINK
  • IP_COMPONENT_GROUP
  • IP_COMPONENT_INTERNAL
  • IP_COMPONENT_NAME
  • IP_COMPONENT_PARAMETER
  • IP_COMPONENT_REPORT_HIERARCHY
  • IP_COMPONENT_SETTING
  • IP_COMPONENT_VERSION
  • IP_DEBUG_VISIBLE
  • IP_GENERATED_DEVICE_FAMILY
  • IP_QSYS_MODE
  • IP_SHOW_ANALYSIS_MESSAGES
  • IP_SHOW_ELABORATION_MESSAGES
  • IP_TARGETED_DEVICE_FAMILY
  • IP_TARGETED_PART_TRAIT
  • IP_TOOL_ENV
  • IP_TOOL_HIERARCHY_LEVELS
  • IP_TOOL_NAME
  • IP_TOOL_VERSION
  • IPX_FILE
  • IS_DEBUG
  • IS_FREEFORM
  • ISP_CLAMP_STATE_DEFAULT
  • ISP_CLAMP_STATE
  • JESD204_A_B_12500
  • JESD204_A_B_6375
  • JOHNSON
  • JTAG_BST_SUPPORT_MAX7000
  • JTAG_USER_CODE_DALI
  • JTAG_USER_CODE_FLEX6K
  • KEEP_LCELL_FOLLOWING_PLL
  • L3HH
  • LARGE_PERIPHERY_CLOCK
  • LAST_QUARTUS_VERSION
  • LATE_CLOCK_LATENCY
  • LEVEL1
  • LEVEL2
  • LEVEL3
  • LIBRARY_SEARCH_ORDER
  • LICENSE_FILE
  • LIMIT_AHDL_INTEGERS_TO_32_BITS
  • LINEAR_FORMAT
  • LL_AUTO_SIZE
  • LL_COLOR
  • LL_CORE_ONLY
  • LL_ENABLED
  • LL_EXCLUDE
  • LL_FSDA_LEVEL
  • LL_FSDA_ROUTING_INTERFACE
  • LL_HEIGHT
  • LL_HORIZONTAL_FLIP
  • LL_IGNORE_IO_BANK_FSDA_CONSTRAINT
  • LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT
  • LL_IGNORE_IO_PIN_FSDA_CONSTRAINT
  • LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT
  • LL_IMPORT_FILE
  • LL_MEMBER_EXCEPTIONS
  • LL_MEMBER_OF_FSDA_ROUTING_INTERFACE
  • LL_MEMBER_OF
  • LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE
  • LL_MEMBER_OPTION
  • LL_MEMBER_RESOURCE_EXCLUDE
  • LL_MEMBER_STATE
  • LL_NODE_LOCATION
  • LL_OLD_BEHAVIOR
  • LL_ORIGIN
  • LL_OUTPUT_SIGNAL_FSDA_LEVEL
  • LL_PARENT
  • LL_PATH_EXCLUDE
  • LL_PATH_INCLUDE
  • LL_PRIORITY
  • LL_PR_REGION
  • LL_RCF_IMPORT_FILE
  • LL_RECT
  • LL_REGION_SECURITY_LEVEL
  • LL_RESERVED_IS_LIMITED
  • LL_RESERVED
  • LL_RESERVED_MEMBERS_OF_IMMEDIATE_PARENT_REGION_HIERARCHY_ONLY
  • LL_RESERVE
  • LL_ROOT_REGION
  • LL_ROUGH
  • LL_ROUTING_REGION_EXPANSION_SIZE
  • LL_ROUTING_REGION
  • LL_SECURITY_ROUTING_INTERFACE
  • LL_SIGNAL_SECURITY_LEVEL
  • LL_SOFT
  • LL_SOURCE_PARTITION_HIERARCHY
  • LL_SOURCE_PARTITION
  • LL_SOURCE_REGION
  • LL_STATE
  • LL_WIDTH
  • LOCAL_LINE_DELAY_CHAIN
  • LOCATION_PIN_ASSIGNMENT
  • LOCKED
  • LOGIC_ANALYZER_INTERFACE_FILE
  • LOGIC_ELEMENTS
  • LOGICLOCK_ASSIGNMENT
  • LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT
  • LOGICLOCK_INCREMENTAL_COMPILE_FILE
  • LOGICLOCK_REGION
  • LOGIC_MINIMIZATION_SCRIPT
  • LOW_CAP_ADJUST_FLEX10KE
  • LOW_POWER
  • LOW_VCM
  • LVDS_CLOCK_DATA_DESKEW_ADJUST
  • LVDS_DESKEW
  • LVDS_DIRECT_LOOPBACK_MODE
  • LVDS_FIXED_CLOCK_DATA_PHASE
  • LVDS
  • LVDS_RX_REGISTER
  • M10K
  • M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
  • M144K
  • M144K_USE_DCD
  • M20K
  • MACRO_HEAD
  • MACRO_MEMBER
  • MACRO_TIMING
  • MAP_FILE
  • MAPPER_SYNTHESIS_ASSIGNMENT
  • MASK_REVISION
  • MATCH_PLL_COMPENSATION_CLOCK
  • MAX10FPGA_CONFIGURATION_SCHEME
  • MAX15301
  • MAX7000B_VCCIO_IOBANK1
  • MAX7000B_VCCIO_IOBANK2
  • MAX7000_DEVICE_IO_STANDARD
  • MAX7000_ENABLE_JTAG_BST_SUPPORT
  • MAX7000_FANIN_PER_CELL
  • MAX7000_IGNORE_LCELL_BUFFERS
  • MAX7000_IGNORE_SOFT_BUFFERS
  • MAX7000_INDIVIDUAL_TURBO_BIT
  • MAX7000_JTAG_USER_CODE
  • MAX7000_OPTIMIZATION_TECHNIQUE
  • MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH
  • MAX7000S_JTAG_USER_CODE
  • MAX7000_TECHNOLOGY_MAPPER
  • MAX7000_USE_CHECKSUM_AS_USERCODE
  • MAX7K_CLIQUE_TYPE
  • MAX_AUTO_GLOBAL_REGISTER_CONTROLS
  • MAX_BALANCING_DSP_BLOCKS
  • MAX_CLOCK_ARRIVAL_SKEW
  • MAX_CLOCKS_ALLOWED
  • MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION
  • MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION
  • MAX_CORE_JUNCTION_TEMP
  • MAX_CORE_SUPPLY_VOLTAGE
  • MAX_CURRENT_FOR_ELECTROMIGRATION
  • MAX_CURRENT_FOR_VIO_ELECTROMIGRATION
  • MAX_DATA_ARRIVAL_SKEW
  • MAX_DELAY_FOR_CORE_PERIPHERY_TRANSFER
  • MAX_DELAY_FOR_PERIPHERY_CORE_TRANSFER
  • MAX_FANOUT
  • MAX_GLOBAL_CLOCKS_ALLOWED
  • MAXII_CARRY_CHAIN_LENGTH
  • MAXII_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • MAXII_OPTIMIZATION_TECHNIQUE
  • MAXIMUM
  • MAX_LABS
  • MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED
  • MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS
  • MAX_PERIPHERY_CLOCKS_ALLOWED
  • MAXPLUSII
  • MAX_PROCESSORS_USED_FOR_MULTITHREADING
  • MAX_RAM_BLOCKS_M4K
  • MAX_RAM_BLOCKS_M512
  • MAX_RAM_BLOCKS_MRAM
  • MAX_REGIONAL_CLOCKS_ALLOWED
  • MAX_SCC_SIZE
  • MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER
  • MAX_WIRES_FOR_PERIPHERY_CORE_TRANSFER
  • MEDIUM
  • MEGAFUNCTION_GENERATED_TRI
  • MEGALAB
  • MEGARAM
  • MEM_INTERFACE_DELAY_CHAIN_CONFIG
  • MEMORY_INTERFACE_DATA_PIN_GROUP
  • MERCURY_CARRY_CHAIN_LENGTH
  • MERCURY_CLIQUE_TYPE
  • MERCURY_CONFIG_DEVICE_JTAG_USER_CODE
  • MERCURY_CONFIGURATION_DEVICE
  • MERCURY_CONFIGURATION_SCHEME
  • MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • MERCURY_DEVICE_IO_STANDARD
  • MERCURY_FITTER_TYPE
  • MERCURY_JTAG_USER_CODE
  • MERCURY_OPTIMIZATION_TECHNIQUE
  • MERCURY_TECHNOLOGY_MAPPER
  • MERGE_EQUIVALENT_BIDIRS
  • MERGE_EQUIVALENT_INPUTS
  • MERGE_HEX_FILE
  • MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR
  • MESSAGE_DISABLE
  • MESSAGE_ENABLE
  • MESSAGE_SUPPRESSION_RULE_FILE
  • MFCU
  • MID_POWER
  • MIF_FILE
  • MIGRATION_ASSIGNMENT
  • MIGRATION_AUTO_PACKED_REGISTERS
  • MIGRATION_AUTO_PORT_SWAP
  • MIGRATION_CONSTRAIN_CORE_RESOURCES
  • MIGRATION_DIFFERENT_SOURCE_FILE
  • MIGRATION_ONLY
  • MIGRATION_PORT_SWAPPING
  • MIGRATION_RAM_INFORMATION
  • MIGRATION_RAM_PACKING_INFORMATION
  • MIGRATION_REGISTER_PACKING
  • MIN_CORE_JUNCTION_TEMP
  • MIN_CORE_SUPPLY_VOLTAGE
  • MIN_DELAY_FOR_CORE_PERIPHERY_TRANSFER
  • MIN_DELAY_FOR_PERIPHERY_CORE_TRANSFER
  • MINIMAL_BITS
  • MINIMIZE_AREA
  • MINIMIZE_AREA_WITH_CHAINS
  • MINIMIZE_POWER_ONLY
  • MINIMUM_DELAY_REQUIREMENT
  • MINIMUM
  • MINIMUM_TPD_REQUIREMENT
  • MINIMUM_WIDTH_CLOCK_ENABLE
  • MINIMUM_WIDTH_SLOAD_SCLEAR
  • MIN_TCO_REQUIREMENT
  • MIN_TPD_REQUIREMENT
  • MINUS_DELTA10
  • MINUS_DELTA11
  • MINUS_DELTA12
  • MINUS_DELTA13
  • MINUS_DELTA14
  • MINUS_DELTA15
  • MINUS_DELTA1
  • MINUS_DELTA2
  • MINUS_DELTA3
  • MINUS_DELTA4
  • MINUS_DELTA5
  • MINUS_DELTA6
  • MINUS_DELTA7
  • MINUS_DELTA8
  • MINUS_DELTA9
  • MIN_WIRES_FOR_CORE_PERIPHERY_TRANSFER
  • MIN_WIRES_FOR_PERIPHERY_CORE_TRANSFER
  • MISC_FILE
  • MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE
  • MLAB
  • MLAB_TIMING_CONSTRAINTS_IN_FEED_THROUGH_DONT_CARE_MODE
  • MODE_0
  • MODE_10
  • MODE_11
  • MODE_12
  • MODE_13
  • MODE_14
  • MODE_15
  • MODE_1
  • MODE_2
  • MODE_3
  • MODE_4
  • MODE_5
  • MODE_6
  • MODE_7
  • MODE_8
  • MODE_9
  • MODE_DEFAULT
  • MODEL_1
  • MODEL_2
  • MODEL_3
  • MOVE_TO_TOP_IO
  • MP2_EXPORT_FILE
  • MULTIPLY_BASE_CLOCK_BY
  • MULTIPLY_BASE_CLOCK_PERIOD_BY
  • MUX_RESTRUCTURE
  • MUX_USE_ROUTING_ASSIGNMENT
  • NAVAUATI
  • NCEO_OPEN_DRAIN
  • NCEO_RESERVED_CYCLONEII
  • NCEO_RESERVED
  • NDQS_LOCAL_CLOCK_DELAY_CHAIN
  • NEAR_END
  • NEAR_GLOBAL_CLOCK
  • NEAR_REGIONAL_CLOCK
  • NEGATIVE_180
  • NEGATIVE_90
  • NEGATIVE_EDGE
  • NETLIST_ONLY
  • NETLIST_VIEWER_ASSIGNMENT
  • NETO_ASSIGNMENT
  • NEVER_ALLOW
  • NEVER
  • NEVER_REGENERATE_IP
  • NO_AUTO_INST_DISCOVERY
  • NO_BACK_ANNOTATION
  • NO_BYTE_ENABLE
  • NO_COMBINATIONAL_OUTPUT
  • NO_DC_GAIN
  • NO_FILE
  • NO_GLOBAL_ROUTE
  • NOMINAL_CORE_SUPPLY_VOLTAGE
  • NONDEFAULT_LIBS
  • NON_LOCAL
  • NON_QPI_MODE
  • NON_S1_MODE
  • NONSYNCHSTRUCT_CAT
  • NONSYNCHSTRUCT_RULE_ASYN_RAM
  • NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE
  • NONSYNCHSTRUCT_RULE_COMBLOOP
  • NONSYNCHSTRUCT_RULE_DELAY_CHAIN
  • NONSYNCHSTRUCT_RULE_DLATCH
  • NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN
  • NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED
  • NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR
  • NONSYNCHSTRUCT_RULE_REG_LOOP
  • NONSYNCHSTRUCT_RULE_RIPPLE_CLK
  • NONSYNCHSTRUCT_RULE_SRLATCH
  • NORMAL_COMPILATION
  • NORMAL_LCELL_INSERT
  • NORMAL
  • NO_SDC_PROMOTION
  • NOT_A_CLOCK
  • NOT_BOOST
  • NOT_CLOCK
  • NOT_GATE_PUSH_BACK
  • NOT_USED
  • NTFQ_MSG_ACF_ASSIGNMENTS_CHANGED
  • NUMBER_OF_DESTINATION_TO_REPORT
  • NUMBER_OF_INVERTED_REGISTERS_REPORTED
  • NUMBER_OF_PATHS_TO_REPORT
  • NUMBER_OF_PROTECTED_REGISTERS_REPORTED
  • NUMBER_OF_REMOVED_REGISTERS_REPORTED
  • NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT
  • NUMBER_OF_SWEPT_NODES_REPORTED
  • NUMBER_OF_SYNTHESIS_MIGRATION_ROWS
  • NUM_PARALLEL_PROCESSORS
  • NWS_NRS_NCS_CS_RESERVED
  • OBSAI_1536
  • OBSAI_3072
  • OBSAI_6144
  • OBSAI_768
  • OBSERVABLE
  • OCP_AUTO_PARTITION
  • OCP_FILE
  • OCP_PARTITION
  • OCP_TIMEOUT_PARTITION
  • OCT_100_OHMS
  • OCT_120_OHMS
  • OCT_150_OHMS
  • OCT_AND_IMPEDANCE_MATCHING_CYCLONEII
  • OCT_AND_IMPEDANCE_MATCHING
  • OCT_AND_IMPEDANCE_MATCHING_STRATIXII
  • OCT_CONTROL_BLOCK
  • OE_DELAY_CHAIN
  • OE_OPTION
  • OFFSET_FROM_BASE_CLOCK
  • OFFSET_MAIN
  • OFFSET_PO1
  • OFFSET_PRE
  • ON_CHIP_BITSTREAM_DECOMPRESSION
  • ONE_HOT
  • OPTIMISTIC
  • OPTIMIZATION_MODE
  • OPTIMIZATION_TECHNIQUE_APEX20K
  • OPTIMIZATION_TECHNIQUE_ARMSTRONG
  • OPTIMIZATION_TECHNIQUE_CYCLONEII
  • OPTIMIZATION_TECHNIQUE_CYCLONE
  • OPTIMIZATION_TECHNIQUE_DALI
  • OPTIMIZATION_TECHNIQUE_FLEX10K
  • OPTIMIZATION_TECHNIQUE_FLEX6K
  • OPTIMIZATION_TECHNIQUE_MAX7000
  • OPTIMIZATION_TECHNIQUE_TSUNAMI
  • OPTIMIZATION_TECHNIQUE_YEAGER
  • OPTIMIZE_FAST_CORNER_TIMING
  • OPTIMIZE_FOR_METASTABILITY
  • OPTIMIZE_HOLD_TIMING
  • OPTIMIZE_INTERNAL_TIMING
  • OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING
  • OPTIMIZE_IO_TIMING
  • OPTIMIZE_MULTI_CORNER_TIMING
  • OPTIMIZE_POWER_DURING_FITTING
  • OPTIMIZE_POWER_DURING_SYNTHESIS
  • OPTIMIZE_SIGNAL_INTEGRITY
  • OPTIMIZE_SSN
  • OPTIONS_FOR_ENTITIES_ONLY
  • OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
  • OPTIONS_FOR_NODES_AND_ENTITIES
  • ORIGINAL_INTERFACE_PORT_NAME
  • ORIGINAL_QUARTUS_VERSION
  • ORIGINATING_COMPANION_REVISION
  • OSC_CLK_1_100MHZ
  • OSC_CLK_1_125MHZ
  • OSC_CLK_1_25MHZ
  • OTHER_APF_RESERVED
  • OTHER
  • OTP_AUTO_PARTITION
  • OTP_PARTITION
  • OUTPUT_BUFFER_DELAY_CONTROL
  • OUTPUT_BUFFER_DELAY
  • OUTPUT_DELAY_CHAIN
  • OUTPUT_ENABLE_DELAY
  • OUTPUT_ENABLE_GROUP
  • OUTPUT_ENABLE_REGISTER_DUPLICATION
  • OUTPUT_ENABLE_ROUTING
  • OUTPUT_FILE_NAME
  • OUTPUT_IO_TIMING_ENDPOINT
  • OUTPUT_IO_TIMING_FAR_END_VMEAS
  • OUTPUT_IO_TIMING_NEAR_END_VMEAS
  • OUTPUT_MAX_DELAY
  • OUTPUT_MIN_DELAY
  • OUTPUT_OCT_VALUE
  • OUTPUT_PIN_C_FAR
  • OUTPUT_PIN_C_NEAR
  • OUTPUT_PIN_C_PER_LENGTH
  • OUTPUT_PIN_LENGTH
  • OUTPUT_PIN_LOAD
  • OUTPUT_PIN_L_PER_LENGTH
  • OUTPUT_PIN_R_FAR_HIGH
  • OUTPUT_PIN_R_FAR_LOW
  • OUTPUT_PIN_R_FAR_SERIES
  • OUTPUT_PIN_R_NEAR_HIGH
  • OUTPUT_PIN_R_NEAR_LOW
  • OUTPUT_PIN_R_NEAR_SERIES
  • OUTPUT_PIN_V_TERMINATION
  • OUTPUT_TERMINATION
  • OUTPUT_TYPE
  • OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS
  • OXUSA
  • PACKAGE_SKEW_COMPENSATION
  • PACK_ALL_IO_REGISTERS
  • PAD_TO_CORE_DELAY
  • PAD_TO_DDIO_REGISTER_DELAY
  • PAD_TO_INPUT_REGISTER_DELAY
  • PARALLEL_50_OHMS_WITH_CALIBRATION
  • PARAMETER_ARRAY
  • PARAMETER_BOOL
  • PARAMETER_CHAR
  • PARAMETER_ENUM
  • PARAMETER_PHYSICAL
  • PARAMETER_SIGNED_BIN
  • PARAMETER_SIGNED_DEC
  • PARAMETER_SIGNED_FLOAT
  • PARAMETER_SIGNED_HEX
  • PARAMETER_SIGNED_OCT
  • PARAMETER_STRING
  • PARAMETER_UNKNOWN
  • PARAMETER_UNSIGNED_BIN
  • PARAMETER_UNSIGNED_DEC
  • PARAMETER_UNSIGNED_FLOAT
  • PARAMETER_UNSIGNED_HEX
  • PARAMETER_UNSIGNED_OCT
  • PARAMETER_UNSIZED_BIT_LITERAL
  • PARTIAL_RECONFIGURATION_PARTITION
  • PARTIAL_SRAM_OBJECT_FILE
  • PARTITION_ALWAYS_USE_QXP_NETLIST
  • PARTITION_ASD_REGION_ID
  • PARTITION_ASD_REGION
  • PARTITION_BACK_ANNOTATION
  • PARTITION_COLOR
  • PARTITION_COLOUR
  • PARTITION_ENABLE_STRICT_PRESERVATION
  • PARTITION_EXTRACT_HARD_BLOCK_NODES
  • PARTITION_FITTER_PRESERVATION_LEVEL
  • PARTITION_IGNORE_SOURCE_FILE_CHANGES
  • PARTITION_IMPORT_ASSIGNMENTS
  • PARTITION_IMPORT_EXISTING_ASSIGNMENTS
  • PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS
  • PARTITION_IMPORT_FILE
  • PARTITION_IMPORT_NEW_ASSIGNMENTS
  • PARTITION_IMPORT_PIN_ASSIGNMENTS
  • PARTITION_IMPORT_PROMOTE_ASSIGNMENTS
  • PARTITION_LAST_IMPORTED_FILE
  • PARTITION_NETLIST_TYPE
  • PARTITION_ONLY
  • PARTITION_PRESERVE_HIGH_SPEED_TILES
  • PARTITION_SOURCE
  • PARTITION_TYPE
  • PASSIVE_PARALLEL_ASYNCHRONOUS
  • PASSIVE_PARALLEL_SYNCHRONOUS
  • PASSIVE_PARALLEL_X16
  • PASSIVE_PARALLEL_X32
  • PASSIVE_PARALLEL_X8
  • PASSIVE_PROGRAMMING_FILE_NAME
  • PASSIVE_RESISTOR
  • PASSIVE_SERIAL_ASYNCHRONOUS
  • PASSIVE_SERIAL
  • PBIP_FILE
  • PCB_LAYER
  • PCB_LAYERS
  • PCB_LAYER_THICKNESS
  • PCIE_CABLE
  • PCIE_GEN1_3P5DB
  • PCIE_GEN1
  • PCIE_GEN2_3P5DB
  • PCIE_GEN2_6DB
  • PCIE_GEN2
  • PCIE_GEN3
  • PCIE_PRE_EMPH_GEN1
  • PCIE_PRE_EMPH_GEN2_3_5DB_DEEMPH
  • PCIE_PRE_EMPH_GEN2_6DB_DEEMPH
  • PCIE_PRE_EMPH_GEN2_LOW_MARGIN
  • PCIE_PRE_EMPH_GEN2_LOW_SWING
  • PCIE_VOD_GEN1
  • PCIE_VOD_GEN2_3_5DB_DEEMPH
  • PCIE_VOD_GEN2_6DB_DEEMPH
  • PCIE_VOD_GEN2_LOW_MARGIN
  • PCIE_VOD_GEN2_LOW_SWING
  • PCI_IO
  • PDC_FILE
  • PERIPHERAL
  • PERIPHERY_SEED
  • PERIPHERY_TO_CORE_HIPI_LOCKDOWN
  • PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION
  • PERIPH_FITTER_SCRIPT
  • PERIPH_REPORT_SCRIPT
  • PERSONA_FILE
  • PESSIMISTIC
  • PEXP_LENGTH
  • PEXP_LENGTH_MAX7000
  • PHASE_FROM_BASE_CLOCK
  • PHASE_OF_0_DEGREES
  • PHASE_OF_72_DEGREES
  • PHASE_OF_90_DEGREES
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING_DISABLE_DESTINATION_CHECK
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING_REG_REACH
  • PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
  • PHYSICAL_SYNTHESIS_COMBO_LOGIC
  • PHYSICAL_SYNTHESIS_EFFORT
  • PHYSICAL_SYNTHESIS_EXTRA_EFFORT
  • PHYSICAL_SYNTHESIS_LOG_FILE
  • PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA
  • PHYSICAL_SYNTHESIS_PIPELINE
  • PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
  • PHYSICAL_SYNTHESIS_REGISTER_RETIMING
  • PIN_CONNECT_FROM_NODE
  • PIN_FILE
  • PIN_PLANNER_DISPLAY_ASSIGNMENT_VALUE_FROM_POSITIVE_PIN_TO_NEGATIVE_PIN
  • PIN_PLANNER_FILE
  • PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILE
  • PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILES
  • PLACEMENT_AND_ROUTING_AND_TILE
  • PLACEMENT_AND_ROUTING
  • PLACEMENT_EFFORT_MULTIPLIER
  • PLD_TO_STRIPE_INTERRUPTS_EPXA4_10
  • PLL_APLLY_PFD_ISSUE_WORKAROUND
  • PLL_AUTO_RESET
  • PLL_BANDWIDTH_PRESET
  • PLL_C_COUNTER_DELAY_CHAIN
  • PLL_CHANNEL_SPACING
  • PLL_COMPENSATE
  • PLL_COMPENSATION_MODE
  • PLL_DISABLE_COUNTER_SETTINGS_OPTIMIZATION
  • PLL_ENFORCE_USER_PHASE_SHIFT
  • PLL_EXTERNAL_FEEDBACK_BOARD_DELAY
  • PLL_FEEDBACK_CLOCK_SIGNAL
  • PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY
  • PLL_FORCE_OUTPUT_COUNTER
  • PLL_IGNORE_MIGRATION_DEVICES
  • PLL_LOCK_10K
  • PLL_LOCK
  • PLL_LVDS_DELAY_CHAIN
  • PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING
  • PLL_OUTPUT_CLOCK_FREQUENCY
  • PLL_PFD_CLOCK_FREQUENCY
  • PLL_PHASE_RECONFIG_COUNTER_REMAP_LCELL
  • PLL_PRE_C_COUNTER_DELAY_CHAIN
  • PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL
  • PLL_TYPE
  • PLL_VCO_CLOCK_FREQUENCY
  • PLUS_DELTA10
  • PLUS_DELTA11
  • PLUS_DELTA12
  • PLUS_DELTA13
  • PLUS_DELTA14
  • PLUS_DELTA15
  • PLUS_DELTA1
  • PLUS_DELTA2
  • PLUS_DELTA3
  • PLUS_DELTA4
  • PLUS_DELTA5
  • PLUS_DELTA6
  • PLUS_DELTA7
  • PLUS_DELTA8
  • PLUS_DELTA9
  • PMBUS_MASTER
  • PMBUS_SLAVE
  • POF_VERIFY_PROTECT
  • POR_SCHEME
  • POSITIVE_180
  • POSITIVE_90
  • POSITIVE_EDGE
  • POST_CONFIG
  • POST_FIT_CONNECT_FROM_SLD_NODE_ENTITY_PORT
  • POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT
  • POST_FIT_WITH_ROUTING
  • POST_FLOW_SCRIPT_FILE
  • POST_MAPPING_RESYNTHESIS
  • POST_MODULE_SCRIPT_FILE
  • POST_SYNTH
  • POWER_AUTO_COMPUTE_TJ
  • POWER_BOARD_TEMPERATURE
  • POWER_BOARD_THERMAL_MODEL
  • POWER_DEFAULT_INPUT_IO_TOGGLE_RATE
  • POWER_DEFAULT_TOGGLE_RATE
  • POWER_ESTIMATION_ASSIGNMENT
  • POWER_ESTIMATION_END_TIME
  • POWER_ESTIMATION_START_TIME
  • POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR
  • POWER_GLITCH_FACTOR
  • POWER_HPS_DYNAMIC_POWER_DUAL
  • POWER_HPS_DYNAMIC_POWER_SINGLE
  • POWER_HPS_ENABLE
  • POWER_HPS_JUNCTION_TEMPERATURE
  • POWER_HPS_PROC_FREQ
  • POWER_HPS_STATIC_POWER
  • POWER_HPS_TOTAL_POWER
  • POWER_HSSI_LEFT
  • POWER_HSSI
  • POWER_HSSI_RIGHT
  • POWER_HSSI_VCCHIP_LEFT
  • POWER_HSSI_VCCHIP_RIGHT
  • POWER_INPUT_FILE_NAME
  • POWER_INPUT_FILE_SETTINGS
  • POWER_INPUT_FILE_TYPE
  • POWER_INPUT_SAF_NAME
  • POWER_INPUT_VCD_FILE_NAME
  • POWER_OCS_VALUE
  • POWER_OJB_VALUE
  • POWER_OJC_VALUE
  • POWER_OSA_VALUE
  • POWER_OUTPUT_SAF_NAME
  • POWER_PRESET_COOLING_SOLUTION
  • POWER_READ_INPUT_FILE
  • POWER_REPORT_POWER_DISSIPATION
  • POWER_REPORT_SIGNAL_ACTIVITY
  • POWER_SIGNAL_ACTIVITY_END_TIME
  • POWER_SIGNAL_ACTIVITY_START_TIME
  • POWER_STATIC_PROBABILITY
  • POWER_STATIC_TOGGLE_RATE
  • POWER_TJ_VALUE
  • POWER_TOGGLE_RATE
  • POWER_TOGGLE_RATE_PERCENTAGE
  • POWER_UP_HIGH
  • POWER_UP_LEVEL
  • POWER_USE_CUSTOM_COOLING_SOLUTION
  • POWER_USE_DEVICE_CHARACTERISTICS
  • POWER_USE_INPUT_FILE
  • POWER_USE_INPUT_FILES
  • POWER_USE_PVA
  • POWER_USE_TA_VALUE
  • POWER_USE_VOLTAGE
  • POWER_VCCA_FPLL_USER_VOLTAGE
  • POWER_VCCA_GTBR_USER_VOLTAGE
  • POWER_VCCA_GTB_USER_VOLTAGE
  • POWER_VCCA_GXBL_USER_OPTION
  • POWER_VCCA_GXBL_USER_VOLTAGE
  • POWER_VCCA_GXBR_USER_OPTION
  • POWER_VCCA_GXBR_USER_VOLTAGE
  • POWER_VCCA_GXB_USER_OPTION
  • POWER_VCCA_GXB_USER_VOLTAGE
  • POWER_VCCA_L_USER_OPTION
  • POWER_VCCA_L_USER_VOLTAGE
  • POWER_VCCA_PLL_USER_VOLTAGE
  • POWER_VCCA_R_USER_OPTION
  • POWER_VCCA_R_USER_VOLTAGE
  • POWER_VCCA_USER_VOLTAGE
  • POWER_VCCAUX_SHARED_USER_VOLTAGE
  • POWER_VCCAUX_USER_OPTION
  • POWER_VCCAUX_USER_VOLTAGE
  • POWER_VCCBAT_USER_VOLTAGE
  • POWER_VCCCB_USER_OPTION
  • POWER_VCCCB_USER_VOLTAGE
  • POWER_VCCD_FPLL_USER_VOLTAGE
  • POWER_VCCD_PLL_USER_VOLTAGE
  • POWER_VCCD_USER_VOLTAGE
  • POWER_VCCE_GXBL_USER_VOLTAGE
  • POWER_VCCE_GXBR_USER_VOLTAGE
  • POWER_VCCE_GXB_USER_VOLTAGE
  • POWER_VCCEH_GXBL_USER_VOLTAGE
  • POWER_VCCEH_GXBR_USER_VOLTAGE
  • POWER_VCCEH_GXB_USER_VOLTAGE
  • POWER_VCCERAM_USER_VOLTAGE
  • POWER_VCCE_USER_VOLTAGE
  • POWER_VCCH_GTBR_USER_VOLTAGE
  • POWER_VCCH_GTB_USER_VOLTAGE
  • POWER_VCCH_GXBL_USER_OPTION
  • POWER_VCCH_GXBL_USER_VOLTAGE
  • POWER_VCCH_GXBR_USER_OPTION
  • POWER_VCCH_GXBR_USER_VOLTAGE
  • POWER_VCCH_GXB_USER_OPTION
  • POWER_VCCH_GXB_USER_VOLTAGE
  • POWER_VCCHIP_L_USER_VOLTAGE
  • POWER_VCCHIP_R_USER_VOLTAGE
  • POWER_VCCHIP_USER_VOLTAGE
  • POWER_VCCH_L_USER_VOLTAGE
  • POWER_VCC_HPS_USER_VOLTAGE
  • POWER_VCCH_R_USER_VOLTAGE
  • POWER_VCCHSSI_L_USER_VOLTAGE
  • POWER_VCCHSSI_R_USER_VOLTAGE
  • POWER_VCCINT_USER_VOLTAGE
  • POWER_VCCIO_HPS_USER_VOLTAGE
  • POWER_VCCIOREF_HPS_USER_VOLTAGE
  • POWER_VCCIO_USER_OPTION
  • POWER_VCCIO_USER_VOLTAGE
  • POWER_VCCL_GTBL_USER_VOLTAGE
  • POWER_VCCL_GTBR_USER_VOLTAGE
  • POWER_VCCL_GTB_USER_VOLTAGE
  • POWER_VCCL_GXBL_USER_VOLTAGE
  • POWER_VCCL_GXBR_USER_VOLTAGE
  • POWER_VCCL_GXB_USER_OPTION
  • POWER_VCCL_GXB_USER_VOLTAGE
  • POWER_VCCL_HPS_USER_VOLTAGE
  • POWER_VCCL_USER_VOLTAGE
  • POWER_VCCPD_USER_OPTION
  • POWER_VCCPD_USER_VOLTAGE
  • POWER_VCCPGM_USER_VOLTAGE
  • POWER_VCCPLL_HPS_USER_VOLTAGE
  • POWER_VCCPT_USER_VOLTAGE
  • POWER_VCCP_USER_VOLTAGE
  • POWER_VCCR_GTBL_USER_VOLTAGE
  • POWER_VCCR_GTBR_USER_VOLTAGE
  • POWER_VCCR_GTB_USER_VOLTAGE
  • POWER_VCCR_GXBL_USER_OPTION
  • POWER_VCCR_GXBL_USER_VOLTAGE
  • POWER_VCCR_GXBR_USER_OPTION
  • POWER_VCCR_GXBR_USER_VOLTAGE
  • POWER_VCCR_GXB_USER_OPTION
  • POWER_VCCR_GXB_USER_VOLTAGE
  • POWER_VCCR_L_USER_VOLTAGE
  • POWER_VCCR_R_USER_VOLTAGE
  • POWER_VCCRSTCLK_HPS_USER_VOLTAGE
  • POWER_VCCR_USER_VOLTAGE
  • POWER_VCCT_GTBL_USER_VOLTAGE
  • POWER_VCCT_GTBR_USER_VOLTAGE
  • POWER_VCCT_GTB_USER_VOLTAGE
  • POWER_VCCT_GXBL_USER_OPTION
  • POWER_VCCT_GXBL_USER_VOLTAGE
  • POWER_VCCT_GXBR_USER_OPTION
  • POWER_VCCT_GXBR_USER_VOLTAGE
  • POWER_VCCT_GXB_USER_OPTION
  • POWER_VCCT_GXB_USER_VOLTAGE
  • POWER_VCCT_L_USER_VOLTAGE
  • POWER_VCCT_R_USER_VOLTAGE
  • POWER_VCCT_USER_VOLTAGE
  • POWER_VCC_USER_VOLTAGE
  • POWER_VCD_FILE_END_TIME
  • POWER_VCD_FILE_START_TIME
  • POWER_VCD_FILTER_GLITCHES
  • POWER_WILDCARDS
  • PPF_FILE
  • PR_ALLOW_GLOBAL_LIMS
  • PR_BASE
  • PR_BASE_MSF
  • PR_BASE_SOF
  • PR_DONE_OPEN_DRAIN
  • PRE_CONFIG
  • PRE_FLOW_SCRIPT_FILE
  • PRE_MAPPING_RESYNTHESIS
  • PR_ERROR_OPEN_DRAIN
  • PRESERVE_FANOUT_FREE_NODE
  • PRESERVE_HIERARCHICAL_BOUNDARY
  • PRESERVE
  • PRESERVE_PLL_COUNTER_ORDER
  • PRESERVE_PORT_NAME
  • PRESERVE_REGISTER
  • PRESERVE_SYNONYMS
  • PRESERVE_UNUSED_XCVR_CHANNEL
  • PR_IMPL
  • PRINT_DEBUG_MSG_AND_EXIT
  • PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10
  • PRODUCT_TERM
  • PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES
  • PROGRAMMABLE_POWER_TECHNOLOGY_SETTING
  • PROGRAMMABLE_PREEMPHASIS
  • PROGRAMMABLE_VOD
  • PROGRAMMER_ASSIGNMENT
  • PROGRAMMER_OBJECT_FILE
  • PROGRAMMING_FILE_TYPE
  • PROGRAMMING_MODE_APEX20KF
  • PROGRAMMING_MODE_APEX20K
  • PROGRAMMING_MODE_ARMSTRONG
  • PROGRAMMING_MODE_CUDA
  • PROGRAMMING_MODE_CYCLONEII
  • PROGRAMMING_MODE_DALI
  • PROGRAMMING_MODE_EXCALIBUR
  • PROGRAMMING_MODE_FLEX10K
  • PROGRAMMING_MODE_FLEX6K
  • PROGRAMMING_MODE
  • PROGRAMMING_MODE_TITAN
  • PROGRAMMING_MODE_TORNADO
  • PROGRAMMING_MODE_YEAGER
  • PROGRAMMING_MODE_ZIPPLEBACK
  • PROJECT_ASSIGNMENT
  • PROJECT_CREATION_TIME_DATE
  • PROJECT_INFO
  • PROJECT_IP_REGENERATION_POLICY
  • PROJECT_IP_SEARCH_PATHS
  • PROJECT_MIGRATION_TIMESTAMP
  • PROJECT_OUTPUT_DIRECTORY
  • PROJECT_SHOW_ENTITY_NAME
  • PROJECT_SOURCE_FILE
  • PROJECT_THUNDER_BAY
  • PROJECT_USE_SIMPLIFIED_NAMES
  • PRO_ONLY
  • PROPAGATE_CONSTANTS_ON_INPUTS
  • PROPAGATE_INVERSIONS_ON_INPUTS
  • PR_PARTITION
  • PR_PINS_OPEN_DRAIN
  • PRPOF_ID
  • PR_READY_OPEN_DRAIN
  • PR_SKIP_BASE_CHECK
  • PR_SYN
  • PULL_DN
  • PULLDOWN_DRIVE_STRENGTH_BITS
  • PULL_DOWN
  • PULL_RESISTOR
  • PULLUP_DRIVE_STRENGTH_BITS
  • PULL_UP_TO_VCCELA
  • PULSE_WIDTH_0
  • PULSE_WIDTH_1
  • PULSE_WIDTH_2_LARGE
  • PULSE_WIDTH_2
  • PULSE_WIDTH_NONE
  • PV3102_OR_EM1130
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_B
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_M
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_R
  • PWRMGT_SLAVE_DEVICE0_ADDRESS
  • PWRMGT_SLAVE_DEVICE1_ADDRESS
  • PWRMGT_SLAVE_DEVICE2_ADDRESS
  • PWRMGT_SLAVE_DEVICE3_ADDRESS
  • PWRMGT_SLAVE_DEVICE4_ADDRESS
  • PWRMGT_SLAVE_DEVICE5_ADDRESS
  • PWRMGT_SLAVE_DEVICE6_ADDRESS
  • PWRMGT_SLAVE_DEVICE7_ADDRESS
  • PWRMGT_SLAVE_DEVICE_TYPE
  • PWRMGT_VOLTAGE_OUTPUT_FORMAT
  • QAR_FILE
  • QARLOG_FILE
  • QDB_FILE
  • QDB_PATH
  • QDFS_USE_CHERRY
  • QDR_D_PIN_GROUP
  • QHD_MODE
  • QIC_EXPORT_FILE
  • QIC_EXPORT_FLATTEN
  • QIC_EXPORT_NETLIST_TYPE
  • QIC_EXPORT_PARTITION_NAME
  • QIC_EXPORT_ROUTING
  • QIC_USE_BINARY_DATABASES
  • QID_ASSIGNMENT
  • QII_AUTO_PACKED_REGISTERS
  • QIP_FILE
  • QPRD
  • QSGMII_5000
  • QSYS_FILE
  • QUARTUS_ACF_FILE
  • QUARTUS_COMPILER_SETTINGS_FILE
  • QUARTUS_ENTITY_SETTINGS_FILE
  • QUARTUS_GUI_SIGNATURE_ID
  • QUARTUSII
  • QUARTUS_PROJECT_FILE
  • QUARTUS_PROJECT_SETTINGS_FILE
  • QUARTUS_PTF_FILE
  • QUARTUS_SBD_FILE
  • QUARTUS_SIMULATOR_SETTINGS_FILE
  • QUARTUS_SOFTWARE_SETTINGS_FILE
  • QUARTUS_STANDARD_DELAY_FILE
  • QUARTUS_WORKSPACE_FILE
  • QVAR_FILE
  • QXP_FILE
  • R08S
  • R_ADAPT_DFE_CONTROL_SEL_0
  • R_ADAPT_DFE_CONTROL_SEL_1
  • R_ADAPT_DFE_CONTROL_SEL_2
  • R_ADAPT_DFE_CONTROL_SEL_3
  • R_ADAPT_DFE_SEL_0
  • R_ADAPT_DFE_SEL_1
  • R_ADAPT_VGA_SEL_0
  • R_ADAPT_VGA_SEL_1
  • R_ADAPT_VREF_SEL_0
  • R_ADAPT_VREF_SEL_1
  • R_ADAPT_VREF_SEL_2
  • R_ADAPT_VREF_SEL_3
  • RADP_CTLE_ACGAIN_4S_0
  • RADP_CTLE_ACGAIN_4S_10
  • RADP_CTLE_ACGAIN_4S_11
  • RADP_CTLE_ACGAIN_4S_12
  • RADP_CTLE_ACGAIN_4S_13
  • RADP_CTLE_ACGAIN_4S_14
  • RADP_CTLE_ACGAIN_4S_15
  • RADP_CTLE_ACGAIN_4S_16
  • RADP_CTLE_ACGAIN_4S_17
  • RADP_CTLE_ACGAIN_4S_18
  • RADP_CTLE_ACGAIN_4S_19
  • RADP_CTLE_ACGAIN_4S_1
  • RADP_CTLE_ACGAIN_4S_20
  • RADP_CTLE_ACGAIN_4S_21
  • RADP_CTLE_ACGAIN_4S_22
  • RADP_CTLE_ACGAIN_4S_23
  • RADP_CTLE_ACGAIN_4S_24
  • RADP_CTLE_ACGAIN_4S_25
  • RADP_CTLE_ACGAIN_4S_26
  • RADP_CTLE_ACGAIN_4S_27
  • RADP_CTLE_ACGAIN_4S_28
  • RADP_CTLE_ACGAIN_4S_2
  • RADP_CTLE_ACGAIN_4S_3
  • RADP_CTLE_ACGAIN_4S_4
  • RADP_CTLE_ACGAIN_4S_5
  • RADP_CTLE_ACGAIN_4S_6
  • RADP_CTLE_ACGAIN_4S_7
  • RADP_CTLE_ACGAIN_4S_8
  • RADP_CTLE_ACGAIN_4S_9
  • RADP_CTLE_EQZ_1S_SEL_0
  • RADP_CTLE_EQZ_1S_SEL_10
  • RADP_CTLE_EQZ_1S_SEL_11
  • RADP_CTLE_EQZ_1S_SEL_12
  • RADP_CTLE_EQZ_1S_SEL_13
  • RADP_CTLE_EQZ_1S_SEL_14
  • RADP_CTLE_EQZ_1S_SEL_15
  • RADP_CTLE_EQZ_1S_SEL_1
  • RADP_CTLE_EQZ_1S_SEL_2
  • RADP_CTLE_EQZ_1S_SEL_3
  • RADP_CTLE_EQZ_1S_SEL_4
  • RADP_CTLE_EQZ_1S_SEL_5
  • RADP_CTLE_EQZ_1S_SEL_6
  • RADP_CTLE_EQZ_1S_SEL_7
  • RADP_CTLE_EQZ_1S_SEL_8
  • RADP_CTLE_EQZ_1S_SEL_9
  • RADP_DFE_FLTAP_POSITION_0
  • RADP_DFE_FLTAP_POSITION_10
  • RADP_DFE_FLTAP_POSITION_11
  • RADP_DFE_FLTAP_POSITION_12
  • RADP_DFE_FLTAP_POSITION_13
  • RADP_DFE_FLTAP_POSITION_14
  • RADP_DFE_FLTAP_POSITION_15
  • RADP_DFE_FLTAP_POSITION_16
  • RADP_DFE_FLTAP_POSITION_17
  • RADP_DFE_FLTAP_POSITION_18
  • RADP_DFE_FLTAP_POSITION_19
  • RADP_DFE_FLTAP_POSITION_1
  • RADP_DFE_FLTAP_POSITION_20
  • RADP_DFE_FLTAP_POSITION_21
  • RADP_DFE_FLTAP_POSITION_22
  • RADP_DFE_FLTAP_POSITION_23
  • RADP_DFE_FLTAP_POSITION_24
  • RADP_DFE_FLTAP_POSITION_25
  • RADP_DFE_FLTAP_POSITION_26
  • RADP_DFE_FLTAP_POSITION_27
  • RADP_DFE_FLTAP_POSITION_28
  • RADP_DFE_FLTAP_POSITION_29
  • RADP_DFE_FLTAP_POSITION_2
  • RADP_DFE_FLTAP_POSITION_30
  • RADP_DFE_FLTAP_POSITION_31
  • RADP_DFE_FLTAP_POSITION_32
  • RADP_DFE_FLTAP_POSITION_33
  • RADP_DFE_FLTAP_POSITION_34
  • RADP_DFE_FLTAP_POSITION_35
  • RADP_DFE_FLTAP_POSITION_36
  • RADP_DFE_FLTAP_POSITION_37
  • RADP_DFE_FLTAP_POSITION_38
  • RADP_DFE_FLTAP_POSITION_39
  • RADP_DFE_FLTAP_POSITION_3
  • RADP_DFE_FLTAP_POSITION_40
  • RADP_DFE_FLTAP_POSITION_41
  • RADP_DFE_FLTAP_POSITION_42
  • RADP_DFE_FLTAP_POSITION_43
  • RADP_DFE_FLTAP_POSITION_44
  • RADP_DFE_FLTAP_POSITION_45
  • RADP_DFE_FLTAP_POSITION_46
  • RADP_DFE_FLTAP_POSITION_47
  • RADP_DFE_FLTAP_POSITION_48
  • RADP_DFE_FLTAP_POSITION_49
  • RADP_DFE_FLTAP_POSITION_4
  • RADP_DFE_FLTAP_POSITION_50
  • RADP_DFE_FLTAP_POSITION_51
  • RADP_DFE_FLTAP_POSITION_52
  • RADP_DFE_FLTAP_POSITION_53
  • RADP_DFE_FLTAP_POSITION_54
  • RADP_DFE_FLTAP_POSITION_55
  • RADP_DFE_FLTAP_POSITION_5
  • RADP_DFE_FLTAP_POSITION_6
  • RADP_DFE_FLTAP_POSITION_7
  • RADP_DFE_FLTAP_POSITION_8
  • RADP_DFE_FLTAP_POSITION_9
  • RADP_DFE_FXTAP10_0
  • RADP_DFE_FXTAP10_10
  • RADP_DFE_FXTAP10_11
  • RADP_DFE_FXTAP10_12
  • RADP_DFE_FXTAP10_13
  • RADP_DFE_FXTAP10_14
  • RADP_DFE_FXTAP10_15
  • RADP_DFE_FXTAP10_16
  • RADP_DFE_FXTAP10_17
  • RADP_DFE_FXTAP10_18
  • RADP_DFE_FXTAP10_19
  • RADP_DFE_FXTAP10_1
  • RADP_DFE_FXTAP10_20
  • RADP_DFE_FXTAP10_21
  • RADP_DFE_FXTAP10_22
  • RADP_DFE_FXTAP10_23
  • RADP_DFE_FXTAP10_24
  • RADP_DFE_FXTAP10_25
  • RADP_DFE_FXTAP10_26
  • RADP_DFE_FXTAP10_27
  • RADP_DFE_FXTAP10_28
  • RADP_DFE_FXTAP10_29
  • RADP_DFE_FXTAP10_2
  • RADP_DFE_FXTAP10_30
  • RADP_DFE_FXTAP10_31
  • RADP_DFE_FXTAP10_32
  • RADP_DFE_FXTAP10_33
  • RADP_DFE_FXTAP10_34
  • RADP_DFE_FXTAP10_35
  • RADP_DFE_FXTAP10_36
  • RADP_DFE_FXTAP10_37
  • RADP_DFE_FXTAP10_38
  • RADP_DFE_FXTAP10_39
  • RADP_DFE_FXTAP10_3
  • RADP_DFE_FXTAP10_40
  • RADP_DFE_FXTAP10_41
  • RADP_DFE_FXTAP10_42
  • RADP_DFE_FXTAP10_43
  • RADP_DFE_FXTAP10_44
  • RADP_DFE_FXTAP10_45
  • RADP_DFE_FXTAP10_46
  • RADP_DFE_FXTAP10_47
  • RADP_DFE_FXTAP10_48
  • RADP_DFE_FXTAP10_49
  • RADP_DFE_FXTAP10_4
  • RADP_DFE_FXTAP10_50
  • RADP_DFE_FXTAP10_51
  • RADP_DFE_FXTAP10_52
  • RADP_DFE_FXTAP10_53
  • RADP_DFE_FXTAP10_54
  • RADP_DFE_FXTAP10_55
  • RADP_DFE_FXTAP10_56
  • RADP_DFE_FXTAP10_57
  • RADP_DFE_FXTAP10_58
  • RADP_DFE_FXTAP10_59
  • RADP_DFE_FXTAP10_5
  • RADP_DFE_FXTAP10_60
  • RADP_DFE_FXTAP10_61
  • RADP_DFE_FXTAP10_62
  • RADP_DFE_FXTAP10_63
  • RADP_DFE_FXTAP10_6
  • RADP_DFE_FXTAP10_7
  • RADP_DFE_FXTAP10_8
  • RADP_DFE_FXTAP10_9
  • RADP_DFE_FXTAP1_0
  • RADP_DFE_FXTAP10_SGN_0
  • RADP_DFE_FXTAP10_SGN_1
  • RADP_DFE_FXTAP1_100
  • RADP_DFE_FXTAP1_101
  • RADP_DFE_FXTAP1_102
  • RADP_DFE_FXTAP1_103
  • RADP_DFE_FXTAP1_104
  • RADP_DFE_FXTAP1_105
  • RADP_DFE_FXTAP1_106
  • RADP_DFE_FXTAP1_107
  • RADP_DFE_FXTAP1_108
  • RADP_DFE_FXTAP1_109
  • RADP_DFE_FXTAP1_10
  • RADP_DFE_FXTAP11_0
  • RADP_DFE_FXTAP1_110
  • RADP_DFE_FXTAP11_10
  • RADP_DFE_FXTAP1_111
  • RADP_DFE_FXTAP11_11
  • RADP_DFE_FXTAP1_112
  • RADP_DFE_FXTAP11_12
  • RADP_DFE_FXTAP1_113
  • RADP_DFE_FXTAP11_13
  • RADP_DFE_FXTAP1_114
  • RADP_DFE_FXTAP11_14
  • RADP_DFE_FXTAP1_115
  • RADP_DFE_FXTAP11_15
  • RADP_DFE_FXTAP1_116
  • RADP_DFE_FXTAP11_16
  • RADP_DFE_FXTAP1_117
  • RADP_DFE_FXTAP11_17
  • RADP_DFE_FXTAP1_118
  • RADP_DFE_FXTAP11_18
  • RADP_DFE_FXTAP1_119
  • RADP_DFE_FXTAP11_19
  • RADP_DFE_FXTAP1_11
  • RADP_DFE_FXTAP11_1
  • RADP_DFE_FXTAP1_120
  • RADP_DFE_FXTAP11_20
  • RADP_DFE_FXTAP1_121
  • RADP_DFE_FXTAP11_21
  • RADP_DFE_FXTAP1_122
  • RADP_DFE_FXTAP11_22
  • RADP_DFE_FXTAP1_123
  • RADP_DFE_FXTAP11_23
  • RADP_DFE_FXTAP1_124
  • RADP_DFE_FXTAP11_24
  • RADP_DFE_FXTAP1_125
  • RADP_DFE_FXTAP11_25
  • RADP_DFE_FXTAP1_126
  • RADP_DFE_FXTAP11_26
  • RADP_DFE_FXTAP1_127
  • RADP_DFE_FXTAP11_27
  • RADP_DFE_FXTAP11_28
  • RADP_DFE_FXTAP11_29
  • RADP_DFE_FXTAP1_12
  • RADP_DFE_FXTAP11_2
  • RADP_DFE_FXTAP11_30
  • RADP_DFE_FXTAP11_31
  • RADP_DFE_FXTAP11_32
  • RADP_DFE_FXTAP11_33
  • RADP_DFE_FXTAP11_34
  • RADP_DFE_FXTAP11_35
  • RADP_DFE_FXTAP11_36
  • RADP_DFE_FXTAP11_37
  • RADP_DFE_FXTAP11_38
  • RADP_DFE_FXTAP11_39
  • RADP_DFE_FXTAP1_13
  • RADP_DFE_FXTAP11_3
  • RADP_DFE_FXTAP11_40
  • RADP_DFE_FXTAP11_41
  • RADP_DFE_FXTAP11_42
  • RADP_DFE_FXTAP11_43
  • RADP_DFE_FXTAP11_44
  • RADP_DFE_FXTAP11_45
  • RADP_DFE_FXTAP11_46
  • RADP_DFE_FXTAP11_47
  • RADP_DFE_FXTAP11_48
  • RADP_DFE_FXTAP11_49
  • RADP_DFE_FXTAP1_14
  • RADP_DFE_FXTAP11_4
  • RADP_DFE_FXTAP11_50
  • RADP_DFE_FXTAP11_51
  • RADP_DFE_FXTAP11_52
  • RADP_DFE_FXTAP11_53
  • RADP_DFE_FXTAP11_54
  • RADP_DFE_FXTAP11_55
  • RADP_DFE_FXTAP11_56
  • RADP_DFE_FXTAP11_57
  • RADP_DFE_FXTAP11_58
  • RADP_DFE_FXTAP11_59
  • RADP_DFE_FXTAP1_15
  • RADP_DFE_FXTAP11_5
  • RADP_DFE_FXTAP11_60
  • RADP_DFE_FXTAP11_61
  • RADP_DFE_FXTAP11_62
  • RADP_DFE_FXTAP11_63
  • RADP_DFE_FXTAP1_16
  • RADP_DFE_FXTAP11_6
  • RADP_DFE_FXTAP1_17
  • RADP_DFE_FXTAP11_7
  • RADP_DFE_FXTAP1_18
  • RADP_DFE_FXTAP11_8
  • RADP_DFE_FXTAP1_19
  • RADP_DFE_FXTAP11_9
  • RADP_DFE_FXTAP1_1
  • RADP_DFE_FXTAP11_SGN_0
  • RADP_DFE_FXTAP11_SGN_1
  • RADP_DFE_FXTAP1_20
  • RADP_DFE_FXTAP1_21
  • RADP_DFE_FXTAP1_22
  • RADP_DFE_FXTAP1_23
  • RADP_DFE_FXTAP1_24
  • RADP_DFE_FXTAP1_25
  • RADP_DFE_FXTAP1_26
  • RADP_DFE_FXTAP1_27
  • RADP_DFE_FXTAP1_28
  • RADP_DFE_FXTAP1_29
  • RADP_DFE_FXTAP1_2
  • RADP_DFE_FXTAP1_30
  • RADP_DFE_FXTAP1_31
  • RADP_DFE_FXTAP1_32
  • RADP_DFE_FXTAP1_33
  • RADP_DFE_FXTAP1_34
  • RADP_DFE_FXTAP1_35
  • RADP_DFE_FXTAP1_36
  • RADP_DFE_FXTAP1_37
  • RADP_DFE_FXTAP1_38
  • RADP_DFE_FXTAP1_39
  • RADP_DFE_FXTAP1_3
  • RADP_DFE_FXTAP1_40
  • RADP_DFE_FXTAP1_41
  • RADP_DFE_FXTAP1_42
  • RADP_DFE_FXTAP1_43
  • RADP_DFE_FXTAP1_44
  • RADP_DFE_FXTAP1_45
  • RADP_DFE_FXTAP1_46
  • RADP_DFE_FXTAP1_47
  • RADP_DFE_FXTAP1_48
  • RADP_DFE_FXTAP1_49
  • RADP_DFE_FXTAP1_4
  • RADP_DFE_FXTAP1_50
  • RADP_DFE_FXTAP1_51
  • RADP_DFE_FXTAP1_52
  • RADP_DFE_FXTAP1_53
  • RADP_DFE_FXTAP1_54
  • RADP_DFE_FXTAP1_55
  • RADP_DFE_FXTAP1_56
  • RADP_DFE_FXTAP1_57
  • RADP_DFE_FXTAP1_58
  • RADP_DFE_FXTAP1_59
  • RADP_DFE_FXTAP1_5
  • RADP_DFE_FXTAP1_60
  • RADP_DFE_FXTAP1_61
  • RADP_DFE_FXTAP1_62
  • RADP_DFE_FXTAP1_63
  • RADP_DFE_FXTAP1_64
  • RADP_DFE_FXTAP1_65
  • RADP_DFE_FXTAP1_66
  • RADP_DFE_FXTAP1_67
  • RADP_DFE_FXTAP1_68
  • RADP_DFE_FXTAP1_69
  • RADP_DFE_FXTAP1_6
  • RADP_DFE_FXTAP1_70
  • RADP_DFE_FXTAP1_71
  • RADP_DFE_FXTAP1_72
  • RADP_DFE_FXTAP1_73
  • RADP_DFE_FXTAP1_74
  • RADP_DFE_FXTAP1_75
  • RADP_DFE_FXTAP1_76
  • RADP_DFE_FXTAP1_77
  • RADP_DFE_FXTAP1_78
  • RADP_DFE_FXTAP1_79
  • RADP_DFE_FXTAP1_7
  • RADP_DFE_FXTAP1_80
  • RADP_DFE_FXTAP1_81
  • RADP_DFE_FXTAP1_82
  • RADP_DFE_FXTAP1_83
  • RADP_DFE_FXTAP1_84
  • RADP_DFE_FXTAP1_85
  • RADP_DFE_FXTAP1_86
  • RADP_DFE_FXTAP1_87
  • RADP_DFE_FXTAP1_88
  • RADP_DFE_FXTAP1_89
  • RADP_DFE_FXTAP1_8
  • RADP_DFE_FXTAP1_90
  • RADP_DFE_FXTAP1_91
  • RADP_DFE_FXTAP1_92
  • RADP_DFE_FXTAP1_93
  • RADP_DFE_FXTAP1_94
  • RADP_DFE_FXTAP1_95
  • RADP_DFE_FXTAP1_96
  • RADP_DFE_FXTAP1_97
  • RADP_DFE_FXTAP1_98
  • RADP_DFE_FXTAP1_99
  • RADP_DFE_FXTAP1_9
  • RADP_DFE_FXTAP2_0
  • RADP_DFE_FXTAP2_100
  • RADP_DFE_FXTAP2_101
  • RADP_DFE_FXTAP2_102
  • RADP_DFE_FXTAP2_103
  • RADP_DFE_FXTAP2_104
  • RADP_DFE_FXTAP2_105
  • RADP_DFE_FXTAP2_106
  • RADP_DFE_FXTAP2_107
  • RADP_DFE_FXTAP2_108
  • RADP_DFE_FXTAP2_109
  • RADP_DFE_FXTAP2_10
  • RADP_DFE_FXTAP2_110
  • RADP_DFE_FXTAP2_111
  • RADP_DFE_FXTAP2_112
  • RADP_DFE_FXTAP2_113
  • RADP_DFE_FXTAP2_114
  • RADP_DFE_FXTAP2_115
  • RADP_DFE_FXTAP2_116
  • RADP_DFE_FXTAP2_117
  • RADP_DFE_FXTAP2_118
  • RADP_DFE_FXTAP2_119
  • RADP_DFE_FXTAP2_11
  • RADP_DFE_FXTAP2_120
  • RADP_DFE_FXTAP2_121
  • RADP_DFE_FXTAP2_122
  • RADP_DFE_FXTAP2_123
  • RADP_DFE_FXTAP2_124
  • RADP_DFE_FXTAP2_125
  • RADP_DFE_FXTAP2_126
  • RADP_DFE_FXTAP2_127
  • RADP_DFE_FXTAP2_12
  • RADP_DFE_FXTAP2_13
  • RADP_DFE_FXTAP2_14
  • RADP_DFE_FXTAP2_15
  • RADP_DFE_FXTAP2_16
  • RADP_DFE_FXTAP2_17
  • RADP_DFE_FXTAP2_18
  • RADP_DFE_FXTAP2_19
  • RADP_DFE_FXTAP2_1
  • RADP_DFE_FXTAP2_20
  • RADP_DFE_FXTAP2_21
  • RADP_DFE_FXTAP2_22
  • RADP_DFE_FXTAP2_23
  • RADP_DFE_FXTAP2_24
  • RADP_DFE_FXTAP2_25
  • RADP_DFE_FXTAP2_26
  • RADP_DFE_FXTAP2_27
  • RADP_DFE_FXTAP2_28
  • RADP_DFE_FXTAP2_29
  • RADP_DFE_FXTAP2_2
  • RADP_DFE_FXTAP2_30
  • RADP_DFE_FXTAP2_31
  • RADP_DFE_FXTAP2_32
  • RADP_DFE_FXTAP2_33
  • RADP_DFE_FXTAP2_34
  • RADP_DFE_FXTAP2_35
  • RADP_DFE_FXTAP2_36
  • RADP_DFE_FXTAP2_37
  • RADP_DFE_FXTAP2_38
  • RADP_DFE_FXTAP2_39
  • RADP_DFE_FXTAP2_3
  • RADP_DFE_FXTAP2_40
  • RADP_DFE_FXTAP2_41
  • RADP_DFE_FXTAP2_42
  • RADP_DFE_FXTAP2_43
  • RADP_DFE_FXTAP2_44
  • RADP_DFE_FXTAP2_45
  • RADP_DFE_FXTAP2_46
  • RADP_DFE_FXTAP2_47
  • RADP_DFE_FXTAP2_48
  • RADP_DFE_FXTAP2_49
  • RADP_DFE_FXTAP2_4
  • RADP_DFE_FXTAP2_50
  • RADP_DFE_FXTAP2_51
  • RADP_DFE_FXTAP2_52
  • RADP_DFE_FXTAP2_53
  • RADP_DFE_FXTAP2_54
  • RADP_DFE_FXTAP2_55
  • RADP_DFE_FXTAP2_56
  • RADP_DFE_FXTAP2_57
  • RADP_DFE_FXTAP2_58
  • RADP_DFE_FXTAP2_59
  • RADP_DFE_FXTAP2_5
  • RADP_DFE_FXTAP2_60
  • RADP_DFE_FXTAP2_61
  • RADP_DFE_FXTAP2_62
  • RADP_DFE_FXTAP2_63
  • RADP_DFE_FXTAP2_64
  • RADP_DFE_FXTAP2_65
  • RADP_DFE_FXTAP2_66
  • RADP_DFE_FXTAP2_67
  • RADP_DFE_FXTAP2_68
  • RADP_DFE_FXTAP2_69
  • RADP_DFE_FXTAP2_6
  • RADP_DFE_FXTAP2_70
  • RADP_DFE_FXTAP2_71
  • RADP_DFE_FXTAP2_72
  • RADP_DFE_FXTAP2_73
  • RADP_DFE_FXTAP2_74
  • RADP_DFE_FXTAP2_75
  • RADP_DFE_FXTAP2_76
  • RADP_DFE_FXTAP2_77
  • RADP_DFE_FXTAP2_78
  • RADP_DFE_FXTAP2_79
  • RADP_DFE_FXTAP2_7
  • RADP_DFE_FXTAP2_80
  • RADP_DFE_FXTAP2_81
  • RADP_DFE_FXTAP2_82
  • RADP_DFE_FXTAP2_83
  • RADP_DFE_FXTAP2_84
  • RADP_DFE_FXTAP2_85
  • RADP_DFE_FXTAP2_86
  • RADP_DFE_FXTAP2_87
  • RADP_DFE_FXTAP2_88
  • RADP_DFE_FXTAP2_89
  • RADP_DFE_FXTAP2_8
  • RADP_DFE_FXTAP2_90
  • RADP_DFE_FXTAP2_91
  • RADP_DFE_FXTAP2_92
  • RADP_DFE_FXTAP2_93
  • RADP_DFE_FXTAP2_94
  • RADP_DFE_FXTAP2_95
  • RADP_DFE_FXTAP2_96
  • RADP_DFE_FXTAP2_97
  • RADP_DFE_FXTAP2_98
  • RADP_DFE_FXTAP2_99
  • RADP_DFE_FXTAP2_9
  • RADP_DFE_FXTAP2_SGN_0
  • RADP_DFE_FXTAP2_SGN_1
  • RADP_DFE_FXTAP3_0
  • RADP_DFE_FXTAP3_100
  • RADP_DFE_FXTAP3_101
  • RADP_DFE_FXTAP3_102
  • RADP_DFE_FXTAP3_103
  • RADP_DFE_FXTAP3_104
  • RADP_DFE_FXTAP3_105
  • RADP_DFE_FXTAP3_106
  • RADP_DFE_FXTAP3_107
  • RADP_DFE_FXTAP3_108
  • RADP_DFE_FXTAP3_109
  • RADP_DFE_FXTAP3_10
  • RADP_DFE_FXTAP3_110
  • RADP_DFE_FXTAP3_111
  • RADP_DFE_FXTAP3_112
  • RADP_DFE_FXTAP3_113
  • RADP_DFE_FXTAP3_114
  • RADP_DFE_FXTAP3_115
  • RADP_DFE_FXTAP3_116
  • RADP_DFE_FXTAP3_117
  • RADP_DFE_FXTAP3_118
  • RADP_DFE_FXTAP3_119
  • RADP_DFE_FXTAP3_11
  • RADP_DFE_FXTAP3_120
  • RADP_DFE_FXTAP3_121
  • RADP_DFE_FXTAP3_122
  • RADP_DFE_FXTAP3_123
  • RADP_DFE_FXTAP3_124
  • RADP_DFE_FXTAP3_125
  • RADP_DFE_FXTAP3_126
  • RADP_DFE_FXTAP3_127
  • RADP_DFE_FXTAP3_12
  • RADP_DFE_FXTAP3_13
  • RADP_DFE_FXTAP3_14
  • RADP_DFE_FXTAP3_15
  • RADP_DFE_FXTAP3_16
  • RADP_DFE_FXTAP3_17
  • RADP_DFE_FXTAP3_18
  • RADP_DFE_FXTAP3_19
  • RADP_DFE_FXTAP3_1
  • RADP_DFE_FXTAP3_20
  • RADP_DFE_FXTAP3_21
  • RADP_DFE_FXTAP3_22
  • RADP_DFE_FXTAP3_23
  • RADP_DFE_FXTAP3_24
  • RADP_DFE_FXTAP3_25
  • RADP_DFE_FXTAP3_26
  • RADP_DFE_FXTAP3_27
  • RADP_DFE_FXTAP3_28
  • RADP_DFE_FXTAP3_29
  • RADP_DFE_FXTAP3_2
  • RADP_DFE_FXTAP3_30
  • RADP_DFE_FXTAP3_31
  • RADP_DFE_FXTAP3_32
  • RADP_DFE_FXTAP3_33
  • RADP_DFE_FXTAP3_34
  • RADP_DFE_FXTAP3_35
  • RADP_DFE_FXTAP3_36
  • RADP_DFE_FXTAP3_37
  • RADP_DFE_FXTAP3_38
  • RADP_DFE_FXTAP3_39
  • RADP_DFE_FXTAP3_3
  • RADP_DFE_FXTAP3_40
  • RADP_DFE_FXTAP3_41
  • RADP_DFE_FXTAP3_42
  • RADP_DFE_FXTAP3_43
  • RADP_DFE_FXTAP3_44
  • RADP_DFE_FXTAP3_45
  • RADP_DFE_FXTAP3_46
  • RADP_DFE_FXTAP3_47
  • RADP_DFE_FXTAP3_48
  • RADP_DFE_FXTAP3_49
  • RADP_DFE_FXTAP3_4
  • RADP_DFE_FXTAP3_50
  • RADP_DFE_FXTAP3_51
  • RADP_DFE_FXTAP3_52
  • RADP_DFE_FXTAP3_53
  • RADP_DFE_FXTAP3_54
  • RADP_DFE_FXTAP3_55
  • RADP_DFE_FXTAP3_56
  • RADP_DFE_FXTAP3_57
  • RADP_DFE_FXTAP3_58
  • RADP_DFE_FXTAP3_59
  • RADP_DFE_FXTAP3_5
  • RADP_DFE_FXTAP3_60
  • RADP_DFE_FXTAP3_61
  • RADP_DFE_FXTAP3_62
  • RADP_DFE_FXTAP3_63
  • RADP_DFE_FXTAP3_64
  • RADP_DFE_FXTAP3_65
  • RADP_DFE_FXTAP3_66
  • RADP_DFE_FXTAP3_67
  • RADP_DFE_FXTAP3_68
  • RADP_DFE_FXTAP3_69
  • RADP_DFE_FXTAP3_6
  • RADP_DFE_FXTAP3_70
  • RADP_DFE_FXTAP3_71
  • RADP_DFE_FXTAP3_72
  • RADP_DFE_FXTAP3_73
  • RADP_DFE_FXTAP3_74
  • RADP_DFE_FXTAP3_75
  • RADP_DFE_FXTAP3_76
  • RADP_DFE_FXTAP3_77
  • RADP_DFE_FXTAP3_78
  • RADP_DFE_FXTAP3_79
  • RADP_DFE_FXTAP3_7
  • RADP_DFE_FXTAP3_80
  • RADP_DFE_FXTAP3_81
  • RADP_DFE_FXTAP3_82
  • RADP_DFE_FXTAP3_83
  • RADP_DFE_FXTAP3_84
  • RADP_DFE_FXTAP3_85
  • RADP_DFE_FXTAP3_86
  • RADP_DFE_FXTAP3_87
  • RADP_DFE_FXTAP3_88
  • RADP_DFE_FXTAP3_89
  • RADP_DFE_FXTAP3_8
  • RADP_DFE_FXTAP3_90
  • RADP_DFE_FXTAP3_91
  • RADP_DFE_FXTAP3_92
  • RADP_DFE_FXTAP3_93
  • RADP_DFE_FXTAP3_94
  • RADP_DFE_FXTAP3_95
  • RADP_DFE_FXTAP3_96
  • RADP_DFE_FXTAP3_97
  • RADP_DFE_FXTAP3_98
  • RADP_DFE_FXTAP3_99
  • RADP_DFE_FXTAP3_9
  • RADP_DFE_FXTAP3_SGN_0
  • RADP_DFE_FXTAP3_SGN_1
  • RADP_DFE_FXTAP4_0
  • RADP_DFE_FXTAP4_10
  • RADP_DFE_FXTAP4_11
  • RADP_DFE_FXTAP4_12
  • RADP_DFE_FXTAP4_13
  • RADP_DFE_FXTAP4_14
  • RADP_DFE_FXTAP4_15
  • RADP_DFE_FXTAP4_16
  • RADP_DFE_FXTAP4_17
  • RADP_DFE_FXTAP4_18
  • RADP_DFE_FXTAP4_19
  • RADP_DFE_FXTAP4_1
  • RADP_DFE_FXTAP4_20
  • RADP_DFE_FXTAP4_21
  • RADP_DFE_FXTAP4_22
  • RADP_DFE_FXTAP4_23
  • RADP_DFE_FXTAP4_24
  • RADP_DFE_FXTAP4_25
  • RADP_DFE_FXTAP4_26
  • RADP_DFE_FXTAP4_27
  • RADP_DFE_FXTAP4_28
  • RADP_DFE_FXTAP4_29
  • RADP_DFE_FXTAP4_2
  • RADP_DFE_FXTAP4_30
  • RADP_DFE_FXTAP4_31
  • RADP_DFE_FXTAP4_32
  • RADP_DFE_FXTAP4_33
  • RADP_DFE_FXTAP4_34
  • RADP_DFE_FXTAP4_35
  • RADP_DFE_FXTAP4_36
  • RADP_DFE_FXTAP4_37
  • RADP_DFE_FXTAP4_38
  • RADP_DFE_FXTAP4_39
  • RADP_DFE_FXTAP4_3
  • RADP_DFE_FXTAP4_40
  • RADP_DFE_FXTAP4_41
  • RADP_DFE_FXTAP4_42
  • RADP_DFE_FXTAP4_43
  • RADP_DFE_FXTAP4_44
  • RADP_DFE_FXTAP4_45
  • RADP_DFE_FXTAP4_46
  • RADP_DFE_FXTAP4_47
  • RADP_DFE_FXTAP4_48
  • RADP_DFE_FXTAP4_49
  • RADP_DFE_FXTAP4_4
  • RADP_DFE_FXTAP4_50
  • RADP_DFE_FXTAP4_51
  • RADP_DFE_FXTAP4_52
  • RADP_DFE_FXTAP4_53
  • RADP_DFE_FXTAP4_54
  • RADP_DFE_FXTAP4_55
  • RADP_DFE_FXTAP4_56
  • RADP_DFE_FXTAP4_57
  • RADP_DFE_FXTAP4_58
  • RADP_DFE_FXTAP4_59
  • RADP_DFE_FXTAP4_5
  • RADP_DFE_FXTAP4_60
  • RADP_DFE_FXTAP4_61
  • RADP_DFE_FXTAP4_62
  • RADP_DFE_FXTAP4_63
  • RADP_DFE_FXTAP4_6
  • RADP_DFE_FXTAP4_7
  • RADP_DFE_FXTAP4_8
  • RADP_DFE_FXTAP4_9
  • RADP_DFE_FXTAP4_SGN_0
  • RADP_DFE_FXTAP4_SGN_1
  • RADP_DFE_FXTAP5_0
  • RADP_DFE_FXTAP5_10
  • RADP_DFE_FXTAP5_11
  • RADP_DFE_FXTAP5_12
  • RADP_DFE_FXTAP5_13
  • RADP_DFE_FXTAP5_14
  • RADP_DFE_FXTAP5_15
  • RADP_DFE_FXTAP5_16
  • RADP_DFE_FXTAP5_17
  • RADP_DFE_FXTAP5_18
  • RADP_DFE_FXTAP5_19
  • RADP_DFE_FXTAP5_1
  • RADP_DFE_FXTAP5_20
  • RADP_DFE_FXTAP5_21
  • RADP_DFE_FXTAP5_22
  • RADP_DFE_FXTAP5_23
  • RADP_DFE_FXTAP5_24
  • RADP_DFE_FXTAP5_25
  • RADP_DFE_FXTAP5_26
  • RADP_DFE_FXTAP5_27
  • RADP_DFE_FXTAP5_28
  • RADP_DFE_FXTAP5_29
  • RADP_DFE_FXTAP5_2
  • RADP_DFE_FXTAP5_30
  • RADP_DFE_FXTAP5_31
  • RADP_DFE_FXTAP5_32
  • RADP_DFE_FXTAP5_33
  • RADP_DFE_FXTAP5_34
  • RADP_DFE_FXTAP5_35
  • RADP_DFE_FXTAP5_36
  • RADP_DFE_FXTAP5_37
  • RADP_DFE_FXTAP5_38
  • RADP_DFE_FXTAP5_39
  • RADP_DFE_FXTAP5_3
  • RADP_DFE_FXTAP5_40
  • RADP_DFE_FXTAP5_41
  • RADP_DFE_FXTAP5_42
  • RADP_DFE_FXTAP5_43
  • RADP_DFE_FXTAP5_44
  • RADP_DFE_FXTAP5_45
  • RADP_DFE_FXTAP5_46
  • RADP_DFE_FXTAP5_47
  • RADP_DFE_FXTAP5_48
  • RADP_DFE_FXTAP5_49
  • RADP_DFE_FXTAP5_4
  • RADP_DFE_FXTAP5_50
  • RADP_DFE_FXTAP5_51
  • RADP_DFE_FXTAP5_52
  • RADP_DFE_FXTAP5_53
  • RADP_DFE_FXTAP5_54
  • RADP_DFE_FXTAP5_55
  • RADP_DFE_FXTAP5_56
  • RADP_DFE_FXTAP5_57
  • RADP_DFE_FXTAP5_58
  • RADP_DFE_FXTAP5_59
  • RADP_DFE_FXTAP5_5
  • RADP_DFE_FXTAP5_60
  • RADP_DFE_FXTAP5_61
  • RADP_DFE_FXTAP5_62
  • RADP_DFE_FXTAP5_63
  • RADP_DFE_FXTAP5_6
  • RADP_DFE_FXTAP5_7
  • RADP_DFE_FXTAP5_8
  • RADP_DFE_FXTAP5_9
  • RADP_DFE_FXTAP5_SGN_0
  • RADP_DFE_FXTAP5_SGN_1
  • RADP_DFE_FXTAP6_0
  • RADP_DFE_FXTAP6_10
  • RADP_DFE_FXTAP6_11
  • RADP_DFE_FXTAP6_12
  • RADP_DFE_FXTAP6_13
  • RADP_DFE_FXTAP6_14
  • RADP_DFE_FXTAP6_15
  • RADP_DFE_FXTAP6_16
  • RADP_DFE_FXTAP6_17
  • RADP_DFE_FXTAP6_18
  • RADP_DFE_FXTAP6_19
  • RADP_DFE_FXTAP6_1
  • RADP_DFE_FXTAP6_20
  • RADP_DFE_FXTAP6_21
  • RADP_DFE_FXTAP6_22
  • RADP_DFE_FXTAP6_23
  • RADP_DFE_FXTAP6_24
  • RADP_DFE_FXTAP6_25
  • RADP_DFE_FXTAP6_26
  • RADP_DFE_FXTAP6_27
  • RADP_DFE_FXTAP6_28
  • RADP_DFE_FXTAP6_29
  • RADP_DFE_FXTAP6_2
  • RADP_DFE_FXTAP6_30
  • RADP_DFE_FXTAP6_31
  • RADP_DFE_FXTAP6_3
  • RADP_DFE_FXTAP6_4
  • RADP_DFE_FXTAP6_5
  • RADP_DFE_FXTAP6_6
  • RADP_DFE_FXTAP6_7
  • RADP_DFE_FXTAP6_8
  • RADP_DFE_FXTAP6_9
  • RADP_DFE_FXTAP6_SGN_0
  • RADP_DFE_FXTAP6_SGN_1
  • RADP_DFE_FXTAP7_0
  • RADP_DFE_FXTAP7_10
  • RADP_DFE_FXTAP7_11
  • RADP_DFE_FXTAP7_12
  • RADP_DFE_FXTAP7_13
  • RADP_DFE_FXTAP7_14
  • RADP_DFE_FXTAP7_15
  • RADP_DFE_FXTAP7_16
  • RADP_DFE_FXTAP7_17
  • RADP_DFE_FXTAP7_18
  • RADP_DFE_FXTAP7_19
  • RADP_DFE_FXTAP7_1
  • RADP_DFE_FXTAP7_20
  • RADP_DFE_FXTAP7_21
  • RADP_DFE_FXTAP7_22
  • RADP_DFE_FXTAP7_23
  • RADP_DFE_FXTAP7_24
  • RADP_DFE_FXTAP7_25
  • RADP_DFE_FXTAP7_26
  • RADP_DFE_FXTAP7_27
  • RADP_DFE_FXTAP7_28
  • RADP_DFE_FXTAP7_29
  • RADP_DFE_FXTAP7_2
  • RADP_DFE_FXTAP7_30
  • RADP_DFE_FXTAP7_31
  • RADP_DFE_FXTAP7_3
  • RADP_DFE_FXTAP7_4
  • RADP_DFE_FXTAP7_5
  • RADP_DFE_FXTAP7_6
  • RADP_DFE_FXTAP7_7
  • RADP_DFE_FXTAP7_8
  • RADP_DFE_FXTAP7_9
  • RADP_DFE_FXTAP7_SGN_0
  • RADP_DFE_FXTAP7_SGN_1
  • RADP_DFE_FXTAP8_0
  • RADP_DFE_FXTAP8_10
  • RADP_DFE_FXTAP8_11
  • RADP_DFE_FXTAP8_12
  • RADP_DFE_FXTAP8_13
  • RADP_DFE_FXTAP8_14
  • RADP_DFE_FXTAP8_15
  • RADP_DFE_FXTAP8_16
  • RADP_DFE_FXTAP8_17
  • RADP_DFE_FXTAP8_18
  • RADP_DFE_FXTAP8_19
  • RADP_DFE_FXTAP8_1
  • RADP_DFE_FXTAP8_20
  • RADP_DFE_FXTAP8_21
  • RADP_DFE_FXTAP8_22
  • RADP_DFE_FXTAP8_23
  • RADP_DFE_FXTAP8_24
  • RADP_DFE_FXTAP8_25
  • RADP_DFE_FXTAP8_26
  • RADP_DFE_FXTAP8_27
  • RADP_DFE_FXTAP8_28
  • RADP_DFE_FXTAP8_29
  • RADP_DFE_FXTAP8_2
  • RADP_DFE_FXTAP8_30
  • RADP_DFE_FXTAP8_31
  • RADP_DFE_FXTAP8_32
  • RADP_DFE_FXTAP8_33
  • RADP_DFE_FXTAP8_34
  • RADP_DFE_FXTAP8_35
  • RADP_DFE_FXTAP8_36
  • RADP_DFE_FXTAP8_37
  • RADP_DFE_FXTAP8_38
  • RADP_DFE_FXTAP8_39
  • RADP_DFE_FXTAP8_3
  • RADP_DFE_FXTAP8_40
  • RADP_DFE_FXTAP8_41
  • RADP_DFE_FXTAP8_42
  • RADP_DFE_FXTAP8_43
  • RADP_DFE_FXTAP8_44
  • RADP_DFE_FXTAP8_45
  • RADP_DFE_FXTAP8_46
  • RADP_DFE_FXTAP8_47
  • RADP_DFE_FXTAP8_48
  • RADP_DFE_FXTAP8_49
  • RADP_DFE_FXTAP8_4
  • RADP_DFE_FXTAP8_50
  • RADP_DFE_FXTAP8_51
  • RADP_DFE_FXTAP8_52
  • RADP_DFE_FXTAP8_53
  • RADP_DFE_FXTAP8_54
  • RADP_DFE_FXTAP8_55
  • RADP_DFE_FXTAP8_56
  • RADP_DFE_FXTAP8_57
  • RADP_DFE_FXTAP8_58
  • RADP_DFE_FXTAP8_59
  • RADP_DFE_FXTAP8_5
  • RADP_DFE_FXTAP8_60
  • RADP_DFE_FXTAP8_61
  • RADP_DFE_FXTAP8_62
  • RADP_DFE_FXTAP8_63
  • RADP_DFE_FXTAP8_6
  • RADP_DFE_FXTAP8_7
  • RADP_DFE_FXTAP8_8
  • RADP_DFE_FXTAP8_9
  • RADP_DFE_FXTAP8_SGN_0
  • RADP_DFE_FXTAP8_SGN_1
  • RADP_DFE_FXTAP9_0
  • RADP_DFE_FXTAP9_10
  • RADP_DFE_FXTAP9_11
  • RADP_DFE_FXTAP9_12
  • RADP_DFE_FXTAP9_13
  • RADP_DFE_FXTAP9_14
  • RADP_DFE_FXTAP9_15
  • RADP_DFE_FXTAP9_16
  • RADP_DFE_FXTAP9_17
  • RADP_DFE_FXTAP9_18
  • RADP_DFE_FXTAP9_19
  • RADP_DFE_FXTAP9_1
  • RADP_DFE_FXTAP9_20
  • RADP_DFE_FXTAP9_21
  • RADP_DFE_FXTAP9_22
  • RADP_DFE_FXTAP9_23
  • RADP_DFE_FXTAP9_24
  • RADP_DFE_FXTAP9_25
  • RADP_DFE_FXTAP9_26
  • RADP_DFE_FXTAP9_27
  • RADP_DFE_FXTAP9_28
  • RADP_DFE_FXTAP9_29
  • RADP_DFE_FXTAP9_2
  • RADP_DFE_FXTAP9_30
  • RADP_DFE_FXTAP9_31
  • RADP_DFE_FXTAP9_32
  • RADP_DFE_FXTAP9_33
  • RADP_DFE_FXTAP9_34
  • RADP_DFE_FXTAP9_35
  • RADP_DFE_FXTAP9_36
  • RADP_DFE_FXTAP9_37
  • RADP_DFE_FXTAP9_38
  • RADP_DFE_FXTAP9_39
  • RADP_DFE_FXTAP9_3
  • RADP_DFE_FXTAP9_40
  • RADP_DFE_FXTAP9_41
  • RADP_DFE_FXTAP9_42
  • RADP_DFE_FXTAP9_43
  • RADP_DFE_FXTAP9_44
  • RADP_DFE_FXTAP9_45
  • RADP_DFE_FXTAP9_46
  • RADP_DFE_FXTAP9_47
  • RADP_DFE_FXTAP9_48
  • RADP_DFE_FXTAP9_49
  • RADP_DFE_FXTAP9_4
  • RADP_DFE_FXTAP9_50
  • RADP_DFE_FXTAP9_51
  • RADP_DFE_FXTAP9_52
  • RADP_DFE_FXTAP9_53
  • RADP_DFE_FXTAP9_54
  • RADP_DFE_FXTAP9_55
  • RADP_DFE_FXTAP9_56
  • RADP_DFE_FXTAP9_57
  • RADP_DFE_FXTAP9_58
  • RADP_DFE_FXTAP9_59
  • RADP_DFE_FXTAP9_5
  • RADP_DFE_FXTAP9_60
  • RADP_DFE_FXTAP9_61
  • RADP_DFE_FXTAP9_62
  • RADP_DFE_FXTAP9_63
  • RADP_DFE_FXTAP9_6
  • RADP_DFE_FXTAP9_7
  • RADP_DFE_FXTAP9_8
  • RADP_DFE_FXTAP9_9
  • RADP_DFE_FXTAP9_SGN_0
  • RADP_DFE_FXTAP9_SGN_1
  • RADP_LFEQ_FB_SEL_0
  • RADP_LFEQ_FB_SEL_1
  • RADP_LFEQ_FB_SEL_2
  • RADP_LFEQ_FB_SEL_3
  • RADP_LFEQ_FB_SEL_4
  • RADP_LFEQ_FB_SEL_5
  • RADP_LFEQ_FB_SEL_6
  • RADP_LFEQ_FB_SEL_7
  • RADP_ONETIME_DFE_0
  • RADP_ONETIME_DFE_1
  • RADP_VGA_SEL_0
  • RADP_VGA_SEL_1
  • RADP_VGA_SEL_2
  • RADP_VGA_SEL_3
  • RADP_VGA_SEL_4
  • RADP_VGA_SEL_5
  • RADP_VGA_SEL_6
  • RADP_VGA_SEL_7
  • RADP_VREF_SEL_0
  • RADP_VREF_SEL_10
  • RADP_VREF_SEL_11
  • RADP_VREF_SEL_12
  • RADP_VREF_SEL_13
  • RADP_VREF_SEL_14
  • RADP_VREF_SEL_15
  • RADP_VREF_SEL_16
  • RADP_VREF_SEL_17
  • RADP_VREF_SEL_18
  • RADP_VREF_SEL_19
  • RADP_VREF_SEL_1
  • RADP_VREF_SEL_20
  • RADP_VREF_SEL_21
  • RADP_VREF_SEL_22
  • RADP_VREF_SEL_23
  • RADP_VREF_SEL_24
  • RADP_VREF_SEL_25
  • RADP_VREF_SEL_26
  • RADP_VREF_SEL_27
  • RADP_VREF_SEL_28
  • RADP_VREF_SEL_29
  • RADP_VREF_SEL_2
  • RADP_VREF_SEL_30
  • RADP_VREF_SEL_31
  • RADP_VREF_SEL_3
  • RADP_VREF_SEL_4
  • RADP_VREF_SEL_5
  • RADP_VREF_SEL_6
  • RADP_VREF_SEL_7
  • RADP_VREF_SEL_8
  • RADP_VREF_SEL_9
  • RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
  • RAM_CTL
  • RAM_REGISTER_DUPLICATION
  • RAMSTYLE_ATTRIBUTE
  • RAM_USE_DCD
  • RANDOM
  • RANDOM_PIN
  • RANDOM_PIN_SEED
  • RAPID_RECOMPILE_ASSIGNMENT_CHECKING
  • RAPID_RECOMPILE_MODE
  • RAPID_RECOMPILE_SYNTHESIS_MODE
  • RAW_BINARY_FILE
  • RBCGEN_CRITICAL_WARNING_TO_ERROR
  • RDYNBUSY_RESERVED
  • READ
  • READ_OR_WRITE_IN_BYTE_ADDRESS
  • REALISTIC
  • RECOMPILE_QUESTION
  • RECONFIGURABLE
  • RECONFIGURABLE_REVISION
  • REFCLK_COUNTER_OUT
  • REFCLK_COUPLING_OCT
  • REGENERATE_IP_IF_HDL_QSYS_MISMATCH
  • REGISTER_LOCATION_TYPE
  • REGISTER_PACKING_ARMSTRONG
  • REGISTER_PACKING_TSUNAMI
  • REGISTERS_ONLY
  • RELATIVE_NEUTRON_FLUX
  • RELEASE_CLEARS_BEFORE_TRI
  • RELEASE_CLEARS_BEFORE_TRI_STATES
  • REMOTE
  • REMOVE_DUPLICATE_LOGIC
  • REMOVE_DUPLICATE_REGISTERS
  • REMOVE_FANOUT_FREE_REGISTERS
  • REMOVE
  • REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS
  • REMOVE_REDUNDANT_LOGIC_CELLS
  • REMOVE_REDUNDANT_USER_CELLS
  • REPLACE_CONFLICTING
  • REPORT_AS_DQS
  • REPORT_CONNECTIVITY_CHECKS
  • REPORT_DELAY
  • REPORT_IO_PATHS_SEPARATELY
  • REPORT_PARAMETER_SETTINGS
  • REPORT_PARAMETER_SETTINGS_PRO
  • REPORT_SOURCE_ASSIGNMENTS
  • REPORT_SOURCE_ASSIGNMENTS_PRO
  • REQUIRED_DUTY_CYCLE
  • REQUIRED_FMAX
  • RESERVE_ALL_UNUSED_PINS
  • RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND
  • RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP
  • RESERVE_ASDO_AFTER_CONFIGURATION
  • RESERVE_AVST_CLK_AFTER_CONFIGURATION
  • RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION
  • RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
  • RESERVE_AVST_VALID_AFTER_CONFIGURATION
  • RESERVED1
  • RESERVED2
  • RESERVED3
  • RESERVED_ALL_UNUSED_PINS
  • RESERVED_ALL_UNUSED_PINS_NO_OUTPUT_GND
  • RESERVE_DATA0_AFTER_CONFIGURATION
  • RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION
  • RESERVE_DATA1_AFTER_CONFIGURATION
  • RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION
  • RESERVE_DCLK_AFTER_CONFIGURATION
  • RESERVED_PIN
  • RESERVE_FLASH_NCE_AFTER_CONFIGURATION
  • RESERVE_FLEXIBLE_CLOCK_NETWORK
  • RESERVE_NCEO_AFTER_CONFIGURATION
  • RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION
  • RESERVE_OTHER_APF_PINS_AFTER_CONFIGURATION
  • RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION
  • RESERVE_PIN
  • RESERVE_PLACE_REGION
  • RESERVE_PR_PINS
  • RESERVE_RDYNBUSY_AFTER_CONFIGURATION
  • RESERVE_ROUTING_OUTPUT_FLEXIBILITY
  • RESERVE_SDO_AFTER_CONFIGURATION
  • RESET_CAT
  • RESET_RULE_ALL
  • RESET_RULE_COMB_ASYNCH_RESET
  • RESET_RULE_IMSYNCH_ASYNCH_DOMAIN
  • RESET_RULE_IMSYNCH_EXRESET
  • RESET_RULE_INPINS_RESETNET
  • RESET_RULE_REG_ASNYCH
  • RESET_RULE_UNSYNCH_ASYNCH_DOMAIN
  • RESET_RULE_UNSYNCH_EXRESET
  • RESOLVE_FILENAME
  • RESOURCE_ALLOCATION
  • RESYNTHESIS_EXTRA_DEBUGGING_INFORMATION
  • RESYNTHESIS_OPTIMIZATION_EFFORT
  • RESYNTHESIS_PHYSICAL_SYNTHESIS
  • RESYNTHESIS_RETIMING
  • RETAIN_COMB_LOGIC_OUTSIDE_CLOUD
  • RETIMER_ASSIGNMENT
  • RETIMER_FAST_FORWARD_ASSIGNMENT
  • REVISION_BASED_FILE_NAME
  • REVISION_CONTROL_DIR
  • REVISION_CONTROL_SYSTEM
  • REVISION_CONTROL_TCL
  • REVISION_CONTROL_TCL_SCRIPT
  • REVISION_TYPE
  • R_EXT0
  • RISE
  • ROOT
  • ROUTER_CLOCKING_TOPOLOGY_ANALYSIS
  • ROUTER_EFFORT_MULTIPLIER
  • ROUTE_REGION
  • ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION
  • ROUTER_REGISTER_DUPLICATION
  • ROUTER_TIMING_OPTIMIZATION_LEVEL
  • ROUTING_BACK_ANNOTATE
  • ROUTING_BACK_ANNOTATION_FILE
  • ROUTING_BACK_ANNOTATION_MODE
  • ROW_GLOBAL_SIGNAL
  • R_R1
  • R_R2
  • RR_HYBRID
  • RTERM_CODE0
  • RTERM_CODE10
  • RTERM_CODE11
  • RTERM_CODE12
  • RTERM_CODE13
  • RTERM_CODE14
  • RTERM_CODE15
  • RTERM_CODE1
  • RTERM_CODE2
  • RTERM_CODE3
  • RTERM_CODE4
  • RTERM_CODE5
  • RTERM_CODE6
  • RTERM_CODE7
  • RTERM_CODE8
  • RTERM_CODE9
  • RTLV_GROUP_COMB_LOGIC_IN_CLOUD
  • RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV
  • RTLV_GROUP_RELATED_NODES
  • RTLV_GROUP_RELATED_NODES_TMV
  • RTLV_PRESERVED_HANGING_NODES
  • RTLV_REMOVE_FANOUT_FREE_REGISTERS
  • RTLV_RETAIN_COMB_LOGIC_OUTSIDE_CLOUD
  • RTLV_SIMPLIFIED_LOGIC
  • RUN_ALL_TIMING_ANALYSES
  • RUN_CLOCK_TAN
  • RUN_COMPARISON_ON_EVERY_COMPILE
  • RUN_DRC_DURING_COMPILATION
  • RUN_FITTER_IN_SIGNALPROBE_MODE
  • RUN_FULL_COMPILE_ON_DEVICE_CHANGE
  • RUN_P2P_TAN
  • RUN_TAN
  • RUN_TIMING_ANALYSES
  • RUN_TIMING_ANALYSES_ONLY_FOR_TIMING_ASSIGNMENTS
  • RX_DET_OFF
  • RX_DET_ON
  • RX_DET_PCIE_OUT
  • RX_DET_QPI_OUT
  • RZQ_GROUP
  • S0L9
  • SAFE_STATE_MACHINE
  • SAME_AS_MULTICYCLE
  • SAMPLE_AND_SUSTAIN
  • SAP_NAME
  • SATA1_I
  • SATA1_M
  • SATA1_X
  • SATA2_I
  • SATA2_M
  • SATA2_X
  • SAVE_DISK_SPACE
  • SAVE_INTERMEDIATE_FITTING_RESULTS
  • SAVE_MIGRATION_INFO_DURING_COMPILATION
  • SBI_FILE
  • SCE_PIN
  • SDC_ENTITY_FILE
  • SDC_ENTITY_HELPER_FILE
  • SDC_STATEMENT
  • SDC_UNIQUIFIED_STATEMENT
  • SDI_1485_HD
  • SDI_270_SD
  • SDI_2970_3G
  • SDLV_0
  • SDLV_10
  • SDLV_11
  • SDLV_12
  • SDLV_13
  • SDLV_14
  • SDLV_15
  • SDLV_1
  • SDLV_2
  • SDLV_3
  • SDLV_4
  • SDLV_5
  • SDLV_6
  • SDLV_7
  • SDLV_8
  • SDLV_9
  • SDO_PIN
  • SDO_RESERVED
  • SEARCH_PATH
  • SECTION_COLUMN
  • SECURITY_BIT
  • SELECTED_EDGE
  • SEQUENTIAL
  • SERIAL_BITSTREAM_FILE
  • SERIAL_LITE_III_16400
  • SERIAL_LITE_III_17400
  • SERIAL_VECTOR_FILE
  • SERIES_25_OHMS
  • SERIES_25_OHMS_WITH_CALIBRATION
  • SERIES_25_OHMS_WITHOUT_CALIBRATION
  • SERIES_50_OHMS
  • SERIES_50_OHMS_WITH_CALIBRATION
  • SERIES_50_OHMS_WITHOUT_CALIBRATION
  • SET_PULSE_WIDTH
  • SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
  • SETUP_HOLD_DETECTION
  • SETUP_HOLD_TIME_VIOLATION_DETECTION
  • SETUP_RELATIONSHIP
  • SEU_FIT_REPORT
  • SFCU
  • SFI_S_6250
  • SFIS
  • SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL
  • SHOW_ALL_TAN_PANELS
  • SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT
  • SHOW_REGISTRATION_MESSAGE
  • SHOW_TIMING_MODEL_CHANGE_MESSAGE
  • SIGNAL_ACTIVITY_FILE
  • SIGNAL_INTEGRITY_ASSIGNMENT
  • SIGNAL_INTEGRITY_WILDCARDS
  • SIGNALPROBE_ALLOW_OVERUSE
  • SIGNALPROBE_ASSIGNMENT
  • SIGNALPROBE_CLOCK
  • SIGNALPROBE_DURING_NORMAL_COMPILATION
  • SIGNAL_PROBE_ENABLE
  • SIGNALPROBE_ENABLE
  • SIGNALPROBE_NUM_REGISTERS
  • SIGNALRACE_CAT
  • SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN
  • SIGNALRACE_RULE_CLK_PORT_RACE
  • SIGNALRACE_RULE_RESET_RACE
  • SIGNALRACE_RULE_SECOND_SIGNAL_RACE
  • SIGNALRACE_RULE_TRISTATE
  • SIGNALTAP_ASSIGNMENTS
  • SIGNALTAP_LOGIC_ANALYZER_PROJECT_FILES
  • SIGNALTAP_LOGIC_ANALYZER_SETTINGS
  • SIGNOFF_ONLY
  • SIM_AUTO_USE_GLITCH_FILTERING
  • SIM_BEHAVIOR_SIMULATION
  • SIM_BUS_CHANNEL_GROUPING
  • SIM_CELL_DELAY_MODEL_TYPE
  • SIM_COMPARE_SIGNAL
  • SIM_COMPILE_HDL_FILES
  • SIM_DEFAULT_VECTOR_COMPARE_TOLERANCE
  • SIM_DELAY_MODEL_TYPE
  • SIM_ENABLE_SIMULATION_NETLIST_VIEWER
  • SIMGEN_ARBITRARY_BLACKBOX
  • SIMGEN_BLACKBOX_FILE
  • SIMGEN_PARAMETER
  • SIM_HDL_TOP_MODULE_NAME
  • SIM_INTERCONNECT_DELAY_MODEL_TYPE
  • SIM_NO_DELAYS
  • SIM_OUTPUT_POWERPLAY_VCD
  • SIM_OUTPUT_POWERPLAY_VCD_NAME
  • SIM_OUTPUT_SAF
  • SIM_OUTPUT_SAF_NAME
  • SIM_OVERWRITE_WAVEFORM_INPUTS
  • SIMPLE_18_BIT_MULTIPLIERS
  • SIMPLE_MULTIPLIERS
  • SIMPLE_MULT
  • SIMPLE_MULT_UPGRADE_WIDTH
  • SIM_POWERPLAY_VCD_END_TIME
  • SIM_POWERPLAY_VCD_START_TIME
  • SIM_PVT_TIMING_MODEL_TYPE
  • SIM_SET_NO_DELAYS_VIRTUAL_IO
  • SIM_SIGNAL_ACTIVITY_END_TIME
  • SIM_SIGNAL_ACTIVITY_START_TIME
  • SIM_SIGNAL_COMPARE_TOLERANCE
  • SIM_SIGNAL_TRIGGER_VECTOR_COMPARE
  • SIM_SIMULATION_DEBUGGER
  • SIM_TAP_REGISTER_D_Q_PORTS
  • SIMULATION_ASSIGNMENT
  • SIMULATION_BUS_CHANNEL_GROUPING
  • SIMULATION_CELL_DELAY_MODEL_TYPE
  • SIMULATION_COMPARE_SIGNAL
  • SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL
  • SIMULATION_COVERAGE
  • SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE
  • SIMULATION_DELAY_MODEL_TYPE
  • SIMULATION_INCREMENTAL_TIME_INPUT
  • SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE
  • SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL
  • SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL
  • SIMULATION_MODE
  • SIMULATION_NETLIST_VIEWER
  • SIMULATION_SIGNAL_COMPARE_TOLERANCE
  • SIMULATION_TYPE
  • SIMULATION_VDB_RESULT_FLUSH
  • SIMULATION_VECTOR_COMPARE_BEGIN_TIME
  • SIMULATION_VECTOR_COMPARE_END_TIME
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_0
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_1
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_DC
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_H
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_L
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_U
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_W
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_X
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_Z
  • SIMULATION_WITH_AUTO_GLITCH_FILTERING
  • SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW
  • SIMULATION_WITH_GLITCH_FILTERING
  • SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF
  • SIMULATOR_ACTION_POINTS
  • SIMULATOR_GENERATE_POWERPLAY_VCD_FILE
  • SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE
  • SIMULATOR_POWERPLAY_VCD_FILE_END_TIME
  • SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION
  • SIMULATOR_POWERPLAY_VCD_FILE_START_TIME
  • SIMULATOR_PVT_TIMING_MODEL_TYPE
  • SIMULATOR_SETTINGS
  • SIMULATOR_SETTINGS_LIST
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME
  • SIMULATOR_TCL_SCRIPT_FILE
  • SIM_USE_FAST_TIMING_MODEL
  • SIM_USE_GLITCH_FILTERING
  • SIM_USE_GLITCH_FILTERING_WHEN_GENERATING_SAF
  • SIM_USE_PDB_NETLIST
  • SIM_VDB_RESULT_FLUSH
  • SIM_VECTOR_COMPARE_BEGIN_TIME
  • SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE
  • SIM_VECTOR_COMPARED_CLOCK_OFFSET
  • SIM_VECTOR_COMPARED_CLOCK_PERIOD
  • SIM_VECTOR_COMPARE_END_TIME
  • SIM_VECTOR_COMPARE_RULE_FOR_0
  • SIM_VECTOR_COMPARE_RULE_FOR_1
  • SIM_VECTOR_COMPARE_RULE_FOR_DC
  • SIM_VECTOR_COMPARE_RULE_FOR_H
  • SIM_VECTOR_COMPARE_RULE_FOR_L
  • SIM_VECTOR_COMPARE_RULE_FOR_U
  • SIM_VECTOR_COMPARE_RULE_FOR_W
  • SIM_VECTOR_COMPARE_RULE_FOR_X
  • SIM_VECTOR_COMPARE_RULE_FOR_Z
  • SIM_VECTOR_COMPARE_TRIGGER_CLOCK
  • SIM_VECTOR_COMPARE_TRIGGER_MODE
  • SIM_VECTOR_COMPARE_TRIGGER_SIGNAL
  • SIM_VECTOR_OUTPUT_FILE
  • SIM_VECTOR_OUTPUT_FORMAT
  • SINGLE_COMP_IMAGE
  • SINGLE_COMP_IMAGE_WITH_ERAM
  • SINGLE_IMAGE
  • SINGLE_IMAGE_WITH_ERAM
  • SINGLE_PIN
  • SIP_FILE
  • SKIP_ATOM_SWEEPER
  • SKIP_CONFLICTING
  • SKIP_CRC_CHECK_IN_HC
  • SKIP_REGENERATING_IP_IF_HDL_MODIFIED
  • SLD_BIDIR_PIN_CONNECT_FROM_PORT
  • SLD_FABRIC_PARTITION
  • SLD_FILE
  • SLD_INCR_NODE_CREATOR_ID
  • SLD_INCR_NODE_ENTITY_NAME
  • SLD_INCR_NODE_PARAMETER_ASSIGNMENT
  • SLD_INCR_NODE_SOURCE_FILE
  • SLD_INFO
  • SLD_NODE_CONNECT_FROM_PORT
  • SLD_NODE_CONNECT_TO_PORT
  • SLD_NODE_CREATOR_ID
  • SLD_NODE_ENTITY_NAME
  • SLD_NODE_PARAMETER_ASSIGNMENT
  • SLD_NODE_SOURCE_FILE
  • SLD_PARAMETER_ASSIGNMENT
  • SLD_PARAMETER_COMPATIBILITY_STRING
  • SLD_PIN_CONNECT_FROM_PORT
  • SLD_PIN_CONNECT_TO_PORT
  • SLD_PRE_SYN_COMPATIBILITY_STRING
  • SLEW_R0
  • SLEW_R1
  • SLEW_R2
  • SLEW_R3
  • SLEW_R4
  • SLEW_R5
  • SLEW_R6
  • SLEW_R7
  • SLOW_POR_DELAY
  • SLOW_SLEW_RATE
  • SMALL
  • SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES
  • SMART_RECOMPILE
  • SMF_FILE
  • SMP_PROCESS_TYPE
  • SOFTWARE_ACTION_POINTS
  • SOFTWARE_LIBRARY_FILE
  • SOFTWARE_SETTINGS
  • SOFTWARE_SETTINGS_LIST
  • SONET
  • SONET_OC12_622
  • SONET_OC192_9953
  • SONET_OC3_155
  • SONET_OC48_2488
  • SOPC_BUILDER_SIGNATURE_ID
  • SOPC_FILE
  • SOPCINFO_FILE
  • SOURCES_PER_DESTINATION_INCLUDE_COUNT
  • SOURCE_SYNCHRONOUS
  • SOURCE_TCL_SCRIPT_FILE
  • SOURCE_TCL_SCRIPT
  • SPARSE_AUTO
  • SPARSE
  • SPAUI_6250
  • SPD_FILE
  • SPECTRAQ_PHYSICAL_SYNTHESIS
  • SPEED_DISK_USAGE_TRADEOFF
  • SPEED
  • SRECORDS_FILE
  • SRIO_1250_LR
  • SRIO_1250_SR
  • SRIO_2500_LR
  • SRIO_2500_SR
  • SRIO_3125_LR
  • SRIO_3125_SR
  • SRIO_5000_LR
  • SRIO_5000_MR
  • SRIO_5000_SR
  • SRIO_6250_LR
  • SRIO_6250_MR
  • SRIO_6250_SR
  • SRIO
  • STA_IGNORED_EMBEDDED_SDC_STATEMENT
  • STA_MODE
  • STANDARD_DELAY_FORMAT_OUTPUT_FILE
  • STANDARD_FIT
  • STANDARD_PARTITION
  • STATE_MACHINE_PROCESSING
  • STD_ONLY
  • STG1_GAIN7
  • STG2_GAIN7
  • STG3_GAIN7
  • STG4_GAIN7
  • STOP
  • STP_FILE
  • STP_INCREMENTAL_SOURCE
  • STP_SIGNAL_PROBE_SOURCE
  • STP_SIGNALPROBE_SOURCE
  • STP_VIRTUAL_PIN_CLK_SOURCE
  • STP_VIRTUAL_PIN
  • STRATIX_CARRY_CHAIN_LENGTH
  • STRATIX_CONFIG_DEVICE_JTAG_USER_CODE
  • STRATIX_CONFIGURATION_DEVICE
  • STRATIX_CONFIGURATION_SCHEME
  • STRATIX_CRC_ERROR_CHECKING
  • STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • STRATIX_DEVICE_IO_STANDARD
  • STRATIX_FAST_PLL_INCREASE_LOCK_WINDOW
  • STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET
  • STRATIXGX_ALLOW_DEDICATED_CLOCK_FANOUT_WITH_ANALOG_RESET
  • STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE
  • STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
  • STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B
  • STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
  • STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_POST8B10B_LOOPBACK
  • STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK
  • STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS
  • STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
  • STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
  • STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT
  • STRATIXGX_OCT_VALUE
  • STRATIXGX_TERMINATION_VALUE
  • STRATIXII_ALLOW_DUAL_PORT_DUAL_CLOCK_MRAM_USAGE
  • STRATIXII_CARRY_CHAIN_LENGTH
  • STRATIX_II_CONFIGURATION_DEVICE
  • STRATIXII_CONFIGURATION_DEVICE
  • STRATIX_II_CONFIGURATION_SCHEME
  • STRATIXII_CONFIGURATION_SCHEME
  • STRATIXII_EP2S60ES_ALLOW_MRAM_USAGE
  • STRATIXIIGX_OCT_VALUE
  • STRATIXIIGX_TERMINATION_VALUE
  • STRATIXIII_CONFIGURATION_SCHEME
  • STRATIXIII_LUTAB_SLOWDOWN
  • STRATIXIII_MRAM_COMPATIBILITY
  • STRATIXIII_OUTPUT_DUTY_CYCLE_DELAY
  • STRATIXIII_UPDATE_MODE
  • STRATIXII_MRAM_COMPATIBILITY
  • STRATIXII_OPTIMIZATION_TECHNIQUE
  • STRATIXII_OUTPUT_DUTY_CYCLE_CONTROL
  • STRATIXII_SILICON_VERSION
  • STRATIXII_TERMINATION
  • STRATIXIV_CONFIGURATION_SCHEME
  • STRATIX_JTAG_USER_CODE
  • STRATIX_OPTIMIZATION_TECHNIQUE
  • STRATIX_TECHNOLOGY_MAPPER
  • STRATIX_UPDATE_MODE
  • STRATIXV_CONFIGURATION_SCHEME
  • STRICT_POST_FIT
  • STRICT_RAM_RECOGNITION
  • STRIPE_TO_PLD_BRIDGE_EPXA4_10
  • STRIPE_TO_PLD_INTERRUPTS_EPXA4_10
  • SUBCLIQUE_OF
  • SUPPRESS_DA_RULE_INTERNAL
  • SUPPRESS_REG_MINIMIZATION_MSG
  • SYMBOL_FILE
  • SYM_FILE
  • SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
  • SYNCHRONIZER_IDENTIFICATION
  • SYNCHRONIZER_TOGGLE_RATE
  • SYNCHRONOUS_GROUP
  • SYNTH_CHECK_PORT_CONNECTIONS
  • SYNTH_CLOCK_MUX_PROTECTION
  • SYNTH_CRITICAL_CLOCK
  • SYNTH_CRITICAL_CLOCK_TO_OUTPUT
  • SYNTH_CRITICAL_ENABLE
  • SYNTH_CRITICAL_INPUT_TO_CLOCK
  • SYNTH_CRITICAL_PIN
  • SYNTHESIS_FITTING_SETTINGS
  • SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
  • SYNTHESIS_ON_ATOMS
  • SYNTHESIS_ONLY
  • SYNTHESIS_ONLY_QIP
  • SYNTHESIS_S10_MIGRATION_CHECKS
  • SYNTHESIS_SEED
  • SYNTHESIS_WILDCARDS
  • SYNTH_GATED_CLOCK_CONVERSION
  • SYNTH_MESSAGE_LEVEL
  • SYNTH_PROTECT_SDC_CONSTRAINT
  • SYNTH_REPORT_SOURCE_ASSIGNMENTS
  • SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM
  • SYNTH_RPT_SHOW_PARAMS_PER_ENTITY_INSTANCE
  • SYNTH_TIMING_DRIVEN_BALANCED_MAPPING
  • SYNTH_TIMING_DRIVEN_REGISTER_DUPLICATION
  • SYNTH_TIMING_DRIVEN_SYNTHESIS
  • SYSTEMVERILOG_2005
  • SYSTEMVERILOG_FILE
  • T10_DELAY
  • T10_FINE_DELAY
  • T10_OCT_DELAY
  • T10_OE_DELAY
  • T10_OE_FINE_DELAY
  • T11_0_DELAY
  • T11_1_DELAY
  • T11_DELAY
  • T11_FINE_DELAY
  • T1_DELAY
  • T1_FINE_DELAY
  • T2_DELAY
  • T3_DELAY
  • T4_DELAY
  • T7_DELAY
  • T7_FINE_DELAY
  • T8_DELAY0
  • T8_DELAY1
  • T9_DELAY
  • T9_FINE_DELAY
  • T9_OCT_DELAY
  • T9_OE_DELAY
  • TAN_SCRIPT_FILE
  • TAO_FILE
  • TAO_FILE_NAME
  • TBFF_PULSE_WIDTH
  • TCL_ENTITY_FILE
  • TCL_FILE
  • TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT
  • TDC_CCPP_TRADEOFF_TOLERANCE
  • TDO_DUMP_FILE
  • TECH_MAPPER_APEX20K
  • TECH_MAPPER_DALI
  • TECH_MAPPER_FLEX10K
  • TECH_MAPPER_FLEX6K
  • TECH_MAPPER
  • TECH_MAPPER_MAX7000
  • TECH_MAPPER_YEAGER
  • TECHNOLOGY_MAPPER_DALI
  • TECHNOLOGY_MAPPER_FLEX6K
  • TEMPLATE_FILE
  • TENG_1588
  • TENG_BASER
  • TENG_KR_10312
  • TENG_SDI
  • TERMINATION_CONTROL_BLOCK
  • TEST_BENCH_MODE
  • TESTING_BOOL
  • TESTING_ENUM
  • TESTING_FILE
  • TESTING_INT_GLOBAL_DISALLOWED_IN_QIP
  • TESTING_INT
  • TESTING_SINGLE_ABSOLUTE_NODE_ENTITY_INT
  • TESTING_SINGLE_BOOL
  • TESTING_SINGLE_ENUM
  • TESTING_SINGLE_INT
  • TESTING_SINGLE_RELATIVE_BOOL
  • TESTING_SINGLE_RELATIVE_ENTITY_INT
  • TESTING_SINGLE_RELATIVE_NODE_ENTITY_BOOL
  • TESTING_SINGLE_RELATIVE_NODE_ENTITY_INT
  • TESTING_SINGLE_RELATIVE_NODE_INT
  • TESTING_SINGLE_STRING
  • TESTING_STRING
  • TEXT_FORMAT_REPORT_FILE
  • THIRD_PARTY_EDA_TOOLS
  • THREE
  • TH_REQUIREMENT
  • THR_THREAD_MAIN_ID
  • TIMEGROUP_EXCEPTION
  • TIMEGROUP_MEMBER
  • TIMEQUEST2
  • TIMEQUEST_CCPP_TRADEOFF_TOLERANCE
  • TIMEQUEST_DO_CCPP_REMOVAL
  • TIMEQUEST_DO_REPORT_TIMING
  • TIMEQUEST_MULTICORNER_ANALYSIS
  • TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS
  • TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
  • TIMEQUEST_REPORT_SCRIPT
  • TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS
  • TIMEQUEST_SPECTRA_Q
  • TIMING_ANALYSIS_OUTPUT_FILE
  • TIMING_ASSIGNMENT
  • TIMING_CAT
  • TIMING_DERATING_FILE
  • TIMING_RULE_COIN_CLKEDGE
  • TIMING_RULE_HIGH_FANOUTS
  • TIMING_RULE_SHIFT_REG
  • TIMING_USING_FAST_TIMING_MODEL
  • TOOLSET
  • TOP_LEVEL_ENTITY
  • TOP_PARTITION_PIN
  • TRANSPORT
  • TREAT_BIDIR_AS_OUTPUT
  • TRI_CONVERTED_FROM_DIRECTIONAL_BUFFER
  • TRIGGER_EQUATION
  • TRIGGER_VECTOR_COMPARE_ON_SIGNAL
  • TRISTATE1
  • TRISTATED1
  • TRI_STATE
  • TRISTATE_OFF
  • TRISTATE_ON
  • TRI_STATE_SPI_PINS
  • TRUE
  • TRUE_WYSIWYG_FLOW
  • TSUNAMI_OPTIMIZATION_TECHNIQUE
  • TSU_REQUIREMENT
  • TXPMA_SLEW_RATE
  • TYPICAL
  • UC_DCD_CAL_OFF
  • UC_DCD_CAL_ON
  • UC_RO_CAL_OFF
  • UC_RO_CAL_ON
  • UC_RX_DFE_CAL_OFF
  • UC_RX_DFE_CAL_ON
  • UC_SKEW_CAL_OFF
  • UC_SKEW_CAL_ON
  • UC_TX_VOD_CAL_CONT_OFF
  • UC_TX_VOD_CAL_CONT_ON
  • UC_TX_VOD_CAL_OFF
  • UC_TX_VOD_CAL_ON
  • UI_DEFAULT_ASSEMBLER_SETTING
  • UI_DEFAULT_COMP_PROCESS_SETTING
  • UI_DEFAULT_EDA_NATIVELINK_SETTING
  • UI_DEFAULT_EDA_SIMULATION_SETTING
  • UI_DEFAULT_FITTER_SETTING
  • UI_DEFAULT_HYPERFLEX_SETTING
  • UI_DEFAULT_OPTIMIZATION_SETTING
  • UI_DEFAULT_SIMULATOR_SETTING
  • UI_DEFAULT_SYNTHESIS_SETTING
  • UI_DEFAULT_TIMING_SETTING
  • UNFORCE_MERGE_PLL
  • UNFORCE_MERGE_PLL_OUTPUT_COUNTER
  • UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE
  • UNIPHY_TEMP_VER_CODE
  • UNNAMED_POOL
  • UNSECURED
  • UNUSED_RXCLK_BTI_MITIGATION
  • UNUSED_RXTXCLK_BTI_MITIGATION
  • UNUSED_TSD_PINS_GND
  • UPCORE_TRANSACTION_MODEL_FILE
  • UPDATE_ASE_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_ASSIGNMENT_GROUP_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_CHIP_EDITOR_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_CONFLICTING
  • UPDATE_ECMC_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_FLOORPLAN_EDITOR_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_MODE_INTERNAL_FLASH
  • UPDATE_MODE_TITAN
  • UPDATE_MODE_YEAGER
  • UPDATE_PAT_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_PIN_PLANNER_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_SIM_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_SSN_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_TAN_FEATURE_TIME_WHEN_CHANGED
  • USE_ADVANCED_DETAILED_LAB_LEGALITY
  • USE_AS_PROGRAMMING_PIN
  • USE_AS_REGULAR_IO
  • USE_CAP
  • USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT
  • USE_CHECKSUM_AS_USERCODE
  • USE_CHECKSUM_AS_USERCODE_MAX7000
  • USE_CLK_FOR_VIRTUAL_PIN
  • USE_CLOCK
  • USE_CLOCK_SETTINGS
  • USE_COMPILER_SETTINGS
  • USE_CONF_DONE
  • USE_CONFIGURATION_DEVICE
  • USE_CONFIGURATION_DEVICE_NAME_APEX20K
  • USE_CONFIGURATION_DEVICE_NAME_ARMSTRONG
  • USE_CONFIGURATION_DEVICE_NAME_CUDA
  • USE_CONFIGURATION_DEVICE_NAME_CYCLONE
  • USE_CONFIGURATION_DEVICE_NAME_DALI
  • USE_CONFIGURATION_DEVICE_NAME_EXCALIBUR
  • USE_CONFIGURATION_DEVICE_NAME_FLEX10K
  • USE_CONFIGURATION_DEVICE_NAME_FLEX6K
  • USE_CONFIGURATION_DEVICE_NAME
  • USE_CONFIGURATION_DEVICE_NAME_YEAGER
  • USE_CONFIGURATION_DEVICE_OPTIONS
  • USE_C_PREPROCESSOR_FOR_GNU_ASM_FILES
  • USE_CVP_CONFDONE
  • USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
  • USE_DMF
  • USE_GENERATED_PHYSICAL_CONSTRAINTS
  • USE_GLOBAL_SETTINGS
  • USE_HIGH_SPEED_ADDER
  • USE_INIT_DONE
  • USE_LOCAL_APEX20K
  • USE_LOCAL_FLEX6K
  • USE_LOCAL
  • USE_LOGIC_ANALYZER_INTERFACE_FILE
  • USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
  • USE_LPM_FOR_AHDL_OPERATORS
  • USE_MULTITAP_FILE
  • USE_NEW_TEXT_REPORT_TABLE_FORMAT
  • USE_PWRMGT_ALERT
  • USE_PWRMGT_SCL
  • USE_PWRMGT_SDA
  • USER_CUSTOM
  • USER_ENABLED
  • USER_ENCODED
  • USER_FILES_NEW_EXTRACTOR
  • USER_JTAG_CODE_APEX20K
  • USER_JTAG_CODE_DALI
  • USER_JTAG_CODE_FLEX10K
  • USER_JTAG_CODE_FLEX6K
  • USER_JTAG_CODE_MAX7000
  • USER_JTAG_CODE_MAX7000S
  • USER_JTAG_CODE_YEAGER
  • USER_LIBRARIES
  • USER_MESSAGE
  • USER_START_UP_CLOCK
  • USER_VALUE
  • USE_SEU_ERROR
  • USE_SIGNALTAP_FILE
  • USE_TCL_PROC
  • USE_TIMEQUEST_TIMING_ANALYZER
  • USE_TIMING_DRIVEN_COMPILATION
  • USE_VPACK
  • USE_VPR
  • USE_VQM_INSTEAD_OF_SOURCE
  • V0P00
  • V0P58
  • V0P64
  • V0P67
  • V0P70
  • V0P75
  • V0P81
  • V0P86
  • V0P87
  • V0P93
  • V0P96
  • V1P00
  • V1P04
  • V1P13
  • V1P22
  • V1P30
  • V1P39
  • VALUE_IS_NODE
  • VARIABLE_VALUE_CANNOT_BE_CHANGED
  • VCCAUX_SHARED_USER_VOLTAGE
  • VCCELA_0P85V
  • VCCELA_0P9V
  • VCCELA_1P0V
  • VCCELA_1P1V
  • VCCER
  • VCCIO_45
  • VCCIO_50
  • VCCIO_55
  • VCCIO_65
  • VCCIO_70
  • VCCIO_75
  • VCCIO_CURRENT_1PT8V
  • VCCIO_CURRENT_2PT5V
  • VCCIO_CURRENT_GTL
  • VCCIO_CURRENT_GTL_PLUS
  • VCCIO_CURRENT_LVCMOS
  • VCCIO_CURRENT_LVTTL
  • VCCIO_CURRENT_PCI
  • VCCIO_CURRENT_SSTL2_CLASS1
  • VCCIO_CURRENT_SSTL2_CLASS2
  • VCCIO_CURRENT_SSTL3_CLASS1
  • VCCIO_CURRENT_SSTL3_CLASS2
  • VCCIO_IOBANK1_MAX7000B
  • VCCIO_IOBANK2_MAX7000B
  • VCCIOREF_HPS_USER_VOLTAGE
  • VCCPD_VOLTAGE
  • VCCRSTCLK_HPS_USER_VOLTAGE
  • VCC_SETTING0
  • VCC_SETTING1
  • VCC_SETTING2
  • VCC_SETTING3
  • VCD_FILE
  • VCM_CURRENT_1
  • VCM_CURRENT_2
  • VCM_CURRENT_3
  • VCM_CURRENT_DEFAULT
  • VCM_SETTING_00
  • VCM_SETTING_01
  • VCM_SETTING_02
  • VCM_SETTING_03
  • VCM_SETTING_04
  • VCM_SETTING_05
  • VCM_SETTING_06
  • VCM_SETTING_07
  • VCM_SETTING_08
  • VCM_SETTING_09
  • VCM_SETTING_10
  • VCM_SETTING_11
  • VCM_SETTING_12
  • VCM_SETTING_13
  • VCM_SETTING_14
  • VCM_SETTING_15
  • VECTOR_COMPARE_TRIGGER_MODE
  • VECTOR_INPUT_SOURCE
  • VECTOR_OUTPUT_DESTINATION
  • VECTOR_SOURCE_FILE
  • VECTOR_TABLE_OUTPUT_FILE
  • VECTOR_TEXT_FILE
  • VER_COMPATIBLE_DB_DIR
  • VERILOG_1995
  • VERILOG_2001
  • VERILOG_CONSTANT_LOOP_LIMIT
  • VERILOG_CU_MODE
  • VERILOG_INCLUDE_FILE
  • VERILOG_INPUT_VERSION
  • VERILOG_LMF_FILE
  • VERILOG_MACRO
  • VERILOG_NON_CONSTANT_LOOP_LIMIT
  • VERILOG_OUTPUT_FILE
  • VERILOG_SHOW_LMF_MAPPING_MESSAGES
  • VERILOG_SHOW_LMF_MAPPING_MSGS
  • VERILOG_TEST_BENCH_FILE
  • VERILOG_VH_FILE
  • VHDL_1987
  • VHDL_1993
  • VHDL_2008
  • VHDL87
  • VHDL93
  • VHDL_FILE
  • VHDL_INPUT_LIBRARY
  • VHDL_INPUT_VERSION
  • VHDL_LMF_FILE
  • VHDL_OUTPUT_FILE
  • VHDL_SHOW_LMF_MAPPING_MESSAGES
  • VHDL_SHOW_LMF_MAPPING_MSGS
  • VHDL_TEST_BENCH_FILE
  • VID_OPERATION_MODE
  • VIRTUAL_CLOCK_REFERENCE
  • VIRTUAL_IO_DRIVES_CLOCK_PORT
  • VOLT_0MV
  • VOLT_0P35V
  • VOLT_0P50V
  • VOLT_0P55V
  • VOLT_0P60V
  • VOLT_0P65V
  • VOLT_0P70V
  • VOLT_0P75V
  • VOLT_0P80V
  • VPACK_ONLY
  • VQM_FILE
  • VREF_VOLT_0
  • VREF_VOLT_0P5
  • VREF_VOLT_0P75
  • VREF_VOLT_1P0
  • VTT_0P35V
  • VTT_0P50V
  • VTT_0P55V
  • VTT_0P60V
  • VTT_0P65V
  • VTT_0P70V
  • VTT_0P75V
  • VTT_0P80V
  • VTT_PDN_STRONG
  • VTT_PDN_WEAK
  • VTT_PUP_STRONG
  • VTT_PUP_WEAK
  • VTT_VCMOFF0
  • VTT_VCMOFF1
  • VTT_VCMOFF2
  • VTT_VCMOFF3
  • VTT_VCMOFF4
  • VTT_VCMOFF5
  • VTT_VCMOFF6
  • VTT_VCMOFF7
  • WAIT_1_MS
  • WAIT_2_MS
  • WAIT_4_MS
  • WAIT_50_MS
  • WAIT_8_MS
  • WEAK_PULL_UP
  • WEAK_PULL_UP_RESISTOR
  • WHEN_TSU_AND_TPD_CONSTRAINTS_PERMIT
  • WIDTH_18_BIT_MULTIPLIERS
  • WIDTH_3
  • WRITE
  • X1_PLL_FREQUENCY
  • XACTO_INCREMENTAL_COMPILE_ASSIGNMENT
  • XACTO_INCREMENTAL_COMPILE_FILE
  • XACTO_REGION
  • XACTO_VQM_FILES
  • XAUI_3125
  • XAUI
  • XCVR_A10_CDR_PLL_ANALOG_MODE
  • XCVR_A10_CDR_PLL_POWER_MODE
  • XCVR_A10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • XCVR_A10_CDR_PLL_UC_RO_CAL
  • XCVR_A10_CMU_FPLL_ANALOG_MODE
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • XCVR_A10_CMU_FPLL_POWER_MODE
  • XCVR_A10_LC_PLL_ANALOG_MODE
  • XCVR_A10_LC_PLL_POWER_MODE
  • XCVR_A10_PM_UC_CLKDIV_SEL
  • XCVR_A10_PM_UC_CLKSEL_CORE
  • XCVR_A10_PM_UC_CLKSEL_OSC
  • XCVR_A10_REFCLK_TERM_TRISTATE
  • XCVR_A10_RX_ADAPT_DFE_CONTROL_SEL
  • XCVR_A10_RX_ADAPT_DFE_SEL
  • XCVR_A10_RX_ADAPT_VGA_SEL
  • XCVR_A10_RX_ADAPT_VREF_SEL
  • XCVR_A10_RX_ADP_CTLE_ACGAIN_4S
  • XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
  • XCVR_A10_RX_ADP_DFE_FLTAP_POSITION
  • XCVR_A10_RX_ADP_DFE_FXTAP10
  • XCVR_A10_RX_ADP_DFE_FXTAP10_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP11
  • XCVR_A10_RX_ADP_DFE_FXTAP11_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP1
  • XCVR_A10_RX_ADP_DFE_FXTAP2
  • XCVR_A10_RX_ADP_DFE_FXTAP2_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP3
  • XCVR_A10_RX_ADP_DFE_FXTAP3_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP4
  • XCVR_A10_RX_ADP_DFE_FXTAP4_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP5
  • XCVR_A10_RX_ADP_DFE_FXTAP5_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP6
  • XCVR_A10_RX_ADP_DFE_FXTAP6_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP7
  • XCVR_A10_RX_ADP_DFE_FXTAP7_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP8
  • XCVR_A10_RX_ADP_DFE_FXTAP8_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP9
  • XCVR_A10_RX_ADP_DFE_FXTAP9_SGN
  • XCVR_A10_RX_ADP_LFEQ_FB_SEL
  • XCVR_A10_RX_ADP_ONETIME_DFE
  • XCVR_A10_RX_ADP_VGA_SEL
  • XCVR_A10_RX_ADP_VREF_SEL
  • XCVR_A10_RX_BYPASS_EQZ_STAGES_234
  • XCVR_A10_RX_EQ_BW_SEL
  • XCVR_A10_RX_EQ_DC_GAIN_TRIM
  • XCVR_A10_RX_INPUT_VCM_SEL
  • XCVR_A10_RX_LINK
  • XCVR_A10_RX_OFFSET_CANCELLATION_CTRL
  • XCVR_A10_RX_ONE_STAGE_ENABLE
  • XCVR_A10_RX_POWER_MODE
  • XCVR_A10_RX_QPI_ENABLE
  • XCVR_A10_RX_RX_SEL_BIAS_SOURCE
  • XCVR_A10_RX_SD_OUTPUT_OFF
  • XCVR_A10_RX_SD_OUTPUT_ON
  • XCVR_A10_RX_SD_THRESHOLD
  • XCVR_A10_RX_TERM_SEL
  • XCVR_A10_RX_TERM_TRI_ENABLE
  • XCVR_A10_RX_UC_RX_DFE_CAL
  • XCVR_A10_RX_VCCELA_SUPPLY_VOLTAGE
  • XCVR_A10_RX_VCM_CURRENT_ADD
  • XCVR_A10_RX_VCM_SEL
  • XCVR_A10_RX_XRX_PATH_ANALOG_MODE
  • XCVR_A10_TX_COMPENSATION_EN
  • XCVR_A10_TX_DCD_DETECTION_EN
  • XCVR_A10_TX_DPRIO_CGB_VREG_BOOST
  • XCVR_A10_TX_LINK
  • XCVR_A10_TX_LOW_POWER_EN
  • XCVR_A10_TX_POWER_MODE
  • XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • XCVR_A10_TX_RES_CAL_LOCAL
  • XCVR_A10_TX_RX_DET
  • XCVR_A10_TX_RX_DET_OUTPUT_SEL
  • XCVR_A10_TX_RX_DET_PDB
  • XCVR_A10_TX_SLEW_RATE_CTRL
  • XCVR_A10_TX_TERM_CODE
  • XCVR_A10_TX_TERM_SEL
  • XCVR_A10_TX_UC_DCD_CAL
  • XCVR_A10_TX_UC_GEN3
  • XCVR_A10_TX_UC_GEN4
  • XCVR_A10_TX_UC_SKEW_CAL
  • XCVR_A10_TX_UC_TXVOD_CAL_CONT
  • XCVR_A10_TX_UC_TXVOD_CAL
  • XCVR_A10_TX_UC_VCC_SETTING
  • XCVR_A10_TX_USER_FIR_COEFF_CTRL_SEL
  • XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
  • XCVR_A10_TX_XTX_PATH_ANALOG_MODE
  • XCVR_ANALOG_SETTINGS_PROTOCOL
  • XCVR_FAST_LOCK_MODE
  • XCVR_GT_IO_PIN_TERMINATION
  • XCVR_GT_RX_COMMON_MODE_VOLTAGE
  • XCVR_GT_RX_CTLE
  • XCVR_GT_RX_DC_GAIN
  • XCVR_GT_RX_FORCE_VCO_CONST
  • XCVR_GT_TX_COMMON_MODE_VOLTAGE
  • XCVR_GT_TX_PRE_EMP_1ST_POST_TAP
  • XCVR_GT_TX_PRE_EMP_INV_PRE_TAP
  • XCVR_GT_TX_PRE_EMP_PRE_TAP
  • XCVR_GT_TX_VOD_MAIN_TAP
  • XCVR_IO_PIN_TERMINATION
  • XCVR_RECONFIG_AVMM_GROUP
  • XCVR_RECONFIG_GROUP
  • XCVR_REFCLK_PIN_TERMINATION
  • XCVR_RX_ACGAIN_A
  • XCVR_RX_ACGAIN_V
  • XCVR_RX_ADCE_HSF_HFBW
  • XCVR_RX_ADCE_RGEN_BW
  • XCVR_RX_ADCE_RGEN_MODE
  • XCVR_RX_BYPASS_EQ_STAGES_234
  • XCVR_RX_COMMON_MODE_VOLTAGE
  • XCVR_RX_DC_GAIN
  • XCVR_RX_DFE_PI_BW
  • XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
  • XCVR_RX_EQ_BW_SEL
  • XCVR_RX_EYEQ_BANDWIDTH
  • XCVR_RX_INPUT_VCM_SEL
  • XCVR_RX_LINEAR_EQUALIZER_CONTROL
  • XCVR_RX_PMOS_GAIN_PEAK
  • XCVR_RX_QPI_ENABLE
  • XCVR_RX_SD_ENABLE
  • XCVR_RX_SD_OFF
  • XCVR_RX_SD_ON
  • XCVR_RX_SD_THRESHOLD
  • XCVR_RX_SEL_BIAS_SOURCE
  • XCVR_RX_SEL_HALF_BW
  • XCVR_RX_VCM_DRIVE_STRENGTH
  • XCVR_TX_COMMON_MODE_VOLTAGE
  • XCVR_TX_DRIVER_RESOLUTION_CTRL
  • XCVR_TX_LOCAL_IB_CTL
  • XCVR_TX_PLL_RECONFIG_GROUP
  • XCVR_TX_PRE_EMP_1ST_POST_TAP
  • XCVR_TX_PRE_EMP_2ND_POST_TAP
  • XCVR_TX_PRE_EMP_2ND_POST_TAP_USER
  • XCVR_TX_PRE_EMP_INV_2ND_TAP
  • XCVR_TX_PRE_EMP_INV_PRE_TAP
  • XCVR_TX_PRE_EMP_PRE_TAP
  • XCVR_TX_PRE_EMP_PRE_TAP_USER
  • XCVR_TX_QPI_EN
  • XCVR_TX_RX_DET_ENABLE
  • XCVR_TX_RX_DET_MODE
  • XCVR_TX_RX_DET_OUTPUT_SEL
  • XCVR_TX_SLEW_RATE_CTRL
  • XCVR_TX_SWING_BOOST
  • XCVR_TX_VCM_CTRL_SRC
  • XCVR_TX_VCM_DRIVE_STRENGTH
  • XCVR_TX_VOD_BOOST
  • XCVR_TX_VOD
  • XCVR_TX_VOD_PRE_EMP_CTRL_SRC
  • XCVR_VCCA_VOLTAGE
  • XCVR_VCCR_VCCT_VOLTAGE
  • X_ON_VIOLATION_OPTION
  • XOR_SYNTHESIS
  • XR_AUTO_SIZE
  • XR_CORE_ONLY
  • XR_EXCLUDE
  • XR_HEIGHT
  • XR_MEMBER_OF
  • XR_MEMBER_OPTION
  • XR_MEMBER_RESOURCE_EXCLUDE
  • XR_MEMBER_STATE
  • XR_NODE_LOCATION
  • XR_ORIGIN
  • XR_PARENT
  • XR_PATH_EXCLUDE
  • XR_PATH_INCLUDE
  • XR_PRIORITY
  • XR_RESERVE
  • XR_ROOT_REGION
  • XR_ROUGH
  • XR_SOFT
  • XR_STATE
  • XR_WIDTH
  • XSTL_INPUT_ALLOW_SE_BUFFER
  • YEAGER_CONFIGURATION_DEVICE
  • YEAGER_CRC_ERROR_CHECKING
  • YEAGER_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • YEAGER_DEVICE_IO_STANDARD
  • YEAGER_OCT_AND_IMPEDANCE_MATCHING
  • YEAGER_OPTIMIZATION_TECHNIQUE
  • YEAGER_TECHNOLOGY_MAPPER
  • YEAGER_UPDATE_MODE
  • ZBT_OE_FALLING_EDGE_DELAY
  • ZERO_DELAY_BUFFER
  • ZIP_VECTOR_CHANNEL_FILE
  • ZIP_VECTOR_WAVEFORM_FILE
  • ZL8800
  • ZL9117M

Reverse engineering Cyclone 10 transceiver’s attributes

Introduction

This post summarizes some scattered findings I made while trying to make a Cyclone 10′s signal detect feature work properly for detecting a SuperSpeed USB LFPS signal. As it turned out, Cyclone 10′s transceiver isn’t capable of this, as explained below.

But since the documentation on this issue was lacking, I resorted to reverse engineering Quartus in the attempt to find a solution. So this post is a bit about the transceiver and more about the reverse engineering efforts, which might be relevant in completely different contexts.

I should mention that everything on this page relates to Cyclone 10, even though the output from the tools keep naming different logic elements with “a10″, as if it was Arria 10. Clearly, the transceivers for the two FPGA families are the same.

Software: Quartus Pro 17.1 running on a 64-bit Linux machine (Mint 19).

Cyclone 10′s signal detect is rubbish

The purpose of the signal detector is to tell whether the differential wires are in an electrical idle state, or if there’s some activity on these. This is used by several protocols to wake up the link partners from a low power state: A PCIe link can be awaken by an upstream facing link partner (typically the device waking up the host) from a L2 state by virtue of a beacon, which consists of toggling the polarity at a rate of 30 kHz — 500 MHz. A SATA link can be awaken by one of the link partners transmitting a special data pattern. The USB 3.x protocol also uses out-of-band (OOB) signals if this sort, for various purposes, and calls them LFPS (Low Frequency Pulse Signaling). The toggling rate is defined between 10 — 50 MHz.

The first, relatively simple obstacle, was to turn on the signal detector. The Cyclone 10 GX Transceiver PHY User Guide says in Table 67, regarding rx_std_signaldetect:

When enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage. You can specify the signal detect threshold using a Quartus Prime Settings File (.qsf) assignment. This signal is required for the PCI Express, SATA and SAS protocols.

Similar notes are made in other places in that guide. However it doesn’t mention that if the transceiver is configured in “basic” mode (as opposed to SATA mode, as well as PCIe mode, I suppose), rx_std_signaldetect is stuck on logic ’1′, so enabling this signal alone isn’t enough.

But the real problem is that the signal detector is probably not good for anything but detecting SATA’s OOB: When I selected SATA mode, I did get some response on rx_std_signaldetect, but it was clearly not detecting the LFPS activity in a useful way. Unlike Cyclone V’s signal detector, Cyclone 10′s detector barely responded at all to a 31.25 MHz LFPS, and the detections occurred with pretty arbitrary timing, often with a pulse when the LFPS signal stopped, and some other random pulses as the wires went into electrical idle. In short, far from the desired assertion when the LFPS signals starts and deassertion when it stops.

Things got better as the toggling frequency increased, and around 125 MHz the assertion of the signal detect was steadily aligned with the onset of the LFPS toggling, however the deassertion was often delayed after the LFPS stopped. So even if the LFPS signal could be guaranteed to be at this frequency (it can’t, as it’s produced by the USB 3.x link partner, and 125 MHz is above maximum) the issue with the deassertion makes it impossible to use it with LFPS, which is extremely sensitive to the timing of onset and release of the toggling.

In fact, it’s probably useless for PCIe as well, as a PCIe beacon is allowed between 30 kHz – 500 MHz. This might explain why recent version of user guides for PCIe block for Cyclone V, Arria V, Cyclone 10 and Arria 10, had this sentence added:

These IP cores also do not support the in-band beacon or sideband WAKE# signal, which are mechanisms to signal a wake-up event to the upstream device.

The problem was probably not spotted for a while because the beacon is rarely used: The PCIe spec utilizes beacon transmission only from a device towards the host (upstream) for the sake of bringing up the link from a low power state. So signal detection by an FPGA for the sake of PCIe is only required when the FPGA acts as a host, and low-power modes are supported. In short, practically never.

What’s left? SATA. That will probably work, because the differential wires toggle rapidly, and it doesn’t matter so much if the detection is a bit off-beat.

So I resorted to detecting the LFPS bursts directly from uncoded received data, rather than using the signal detect feature. The rest of this post relates to my attempts before I gave up.

The options are limited

Quartus is going a long way to be “helpful” by verifying that the parameter assignments make sense with regards to the intended protocol (e.g. SATA, PCIe etc), as reflected by the “prot_mode” parameter. This often means that the fitter throws an error when one tries to alter a parameter from its default. It’s like someone said nope, if you’re using the transceiver for SATA, these and these are the correct analog parameters for the PMA, and if you try otherwise, the fitter will kick your bottom for your own protection.

Or maybe it’s a gentle way of telling us users not to try anything but the protocols for which the transceiver is directly intended for.

The fitter may also ignore assignments because they were assinged an unrelated entity (e.g. to gtx_tx instead of the positive-signal’s name, gtx_txp). So be always sure to look in the fitter report’s “Ignored Assignments” section.

One could speculate that this nanny-like behavior can be disabled by setting one of the pma_*_sup_mode parameters to “engineering_mode” rather than the default “user_mode”, but see below on this.

QSF

I expected to solve this by turning the parameters of the signal detector like I’ve previously done with Cyclone V: By virtue of assignments of QSF file.

So here’s the catch: The User Guide also says that the signal detect threshold can be set by virtue of .qsf assignments, but none such are documented in the it (as of the version for Quartus 20.1), and the Assignment Editor offers no parameter of this sort.

For Cyclone V, it’s documented in the V-Series Transceiver PHY IP Core User Guide around page 20-31, and there are recommended values on this page. My anecdotal experiments seem to indicate that assigning XCVR_* attributes (without the C10 part) to a Cyclone 10 transceiver is accepted however ignored by Quartus. In other words, trying to use Cyclone-V QSF assignments won’t cut.

So let’s start the guesswork on the names of the QSF parameters.

Hint source I: The fitter report

The fitter report has a section called “Receiver Channel”, which shows the attributes of the transceiver’s components as applied de-facto. Among others, there’s a part saying

;             -- Name                                           ; frontend_ins|xcvr_inst|xcvr_native_a10_0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_sd.inst_twentynm_hssi_pma_rx_sd                               ;
;             -- Location                                       ; HSSIPMARXSD_1D4                                                                                                                                                                                                                                                       ;
;         -- Advanced Parameters                                ;                                                                                                                                                                                                                                                                       ;
;             -- link                                           ; mr                                                                                                                                                                                                                                                                    ;
;             -- power_mode                                     ; mid_power                                                                                                                                                                                                                                                             ;
;             -- prot_mode                                      ; sata_rx                                                                                                                                                                                                                                                               ;
;             -- sd_output_off                                  ; 1                                                                                                                                                                                                                                                                     ;
;             -- sd_output_on                                   ; 1                                                                                                                                                                                                                                                                     ;
;             -- sd_pdb                                         ; sd_on                                                                                                                                                                                                                                                                 ;
;             -- sd_threshold                                   ; sdlv_3

It’s actually recommended to go through this part in the fitter report in any case, to make sure it was set up as desired.

But this part allows guessing the names of the parameters for the QSF file. For example, the following assignments are perfectly legal (and match the setting shown above):

set_instance_assignment -name XCVR_C10_RX_SD_OUTPUT_OFF 1 -to gtx_rxp
set_instance_assignment -name XCVR_C10_RX_SD_OUTPUT_ON 1 -to gtx_rxp
set_instance_assignment -name XCVR_C10_RX_SD_THRESHOLD SDLV_3 -to gtx_rxp

It doesn’t take a cyber hacker to see the connection between the QSF parameter names and those appearing in the report. This works for some parameters, and not for other. But this is the easiest way to guess parameter names.

Hint source II: Read the sources

But what’s the allowed values that can be assigned to these parameters? Hints on that can be obtained from the System Verilog files generated for the IP, in particular the one named xcvr_xcvr_native_a10_0_altera_xcvr_native_a10_171_ev4uzpa.sv (the “ev4uzpa” suffix varies), which has a section going:

parameter pma_rx_sd_prot_mode = "basic_rx",//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
parameter pma_rx_sd_sd_output_off = 1,//0:28
parameter pma_rx_sd_sd_output_on = 1,//0:15
parameter pma_rx_sd_sd_pdb = "sd_off",//sd_off sd_on
parameter pma_rx_sd_sd_threshold = 3,//0:15
parameter pma_rx_sd_sup_mode = "user_mode",//engineering_mode user_mode

Note the comments, saying which values are allowed for each parameter. On a good day, staying within these value ranges makes the tools accept the assignments, and on an even better day, the fitter won’t throw an error because it considers the values unsuitable.

It’s worth taking a look on the other modules as well, even though they’re likely to have the same comments.

As far as I’ve seen, these parameters are set by the toplevel module for the transceiver IP. QSF assignments, if present, override the former.

Hint source III: What do these assignments mean?

For this I suggest looking at ip/altera/alt_xcvr/alt_xcvr_core/nd/doc/PMA_RegMap.csv (or similar file name) under the root directory of the Quartus installation. Yes, we’re digging in Quartus’ backyard now. I found these files by searching for strings in all files of the Quartus installation. Reverse engineering, after all.

In fact, I’m not sure if this is the correct file to look at, or maybe CR2_PMA_RegMap.csv or whatever. Neither do I know what they mean exactly. It’s however quite evident that these CSV files (opens with your favorite spreadsheet application) were intended to document the register space of the PMA. But the table that shows has a “Attribute Description” column with a few meaningful words on each attribute as well as a column named “Attribute Encoding”, which may happen to be the value to use in a QSF assignment (may and may not work).

There’s also an official register map from Intel available for download, named c10-registermap-official.xlsx, which apparently contains complimentary information. But it’s not possible to deduce QSF names from this file.

Hint source IV: What assignments are legal, then?

I mentioned earlier that the fitter rejects certain value assignment because they apparently don’t make sense. The rules seem to be written as a Tcl script in ip/altera/alt_xcvr/alt_xcvr_core/nd/tcl/ct2_pma_rx_sd_simple.tcl (and similar). Once again, under the Quartus installation root. And yet once again, sometimes this helps, and sometimes it doesn’t.

Hint source V: The names of the QSF paramaters

Up to this point, the names of the parameters to assign in the QSF file were a matter of speculation, based upon similar names in other contexts.

It’s possible to harvest all possible names by searching for strings in one of Quartus’ installed binaries, as shown on this post for non-Pro Quartus 17.1, and this post for Quartus Pro 19.2.

For a complete list of allowed QSF assignment that relate to Cyclone 10 transceivers (or so I groundlessly believe), search for strings in libdb_acf.so, e.g.

$ strings ./quartus/linux64/libdb_acf.so | grep XCVR_C10 | sort
XCVR_C10_CDR_PLL_ANALOG_MODE
XCVR_C10_CDR_PLL_POWER_MODE
XCVR_C10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
XCVR_C10_CDR_PLL_UC_RO_CAL
XCVR_C10_CMU_FPLL_ANALOG_MODE
XCVR_C10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
XCVR_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
XCVR_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
XCVR_C10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
XCVR_C10_CMU_FPLL_POWER_MODE
XCVR_C10_LC_PLL_ANALOG_MODE
XCVR_C10_LC_PLL_POWER_MODE
XCVR_C10_PM_UC_CLKDIV_SEL
XCVR_C10_PM_UC_CLKSEL_CORE
XCVR_C10_PM_UC_CLKSEL_OSC
XCVR_C10_REFCLK_TERM_TRISTATE
XCVR_C10_RX_ADAPT_DFE_CONTROL_SEL
XCVR_C10_RX_ADAPT_DFE_SEL
XCVR_C10_RX_ADAPT_VGA_SEL
XCVR_C10_RX_ADAPT_VREF_SEL
XCVR_C10_RX_ADP_CTLE_ACGAIN_4S
XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL
XCVR_C10_RX_ADP_DFE_FLTAP_POSITION
XCVR_C10_RX_ADP_DFE_FXTAP1
XCVR_C10_RX_ADP_DFE_FXTAP10
XCVR_C10_RX_ADP_DFE_FXTAP10_SGN
XCVR_C10_RX_ADP_DFE_FXTAP11
XCVR_C10_RX_ADP_DFE_FXTAP11_SGN
XCVR_C10_RX_ADP_DFE_FXTAP2
XCVR_C10_RX_ADP_DFE_FXTAP2_SGN
XCVR_C10_RX_ADP_DFE_FXTAP3
XCVR_C10_RX_ADP_DFE_FXTAP3_SGN
XCVR_C10_RX_ADP_DFE_FXTAP4
XCVR_C10_RX_ADP_DFE_FXTAP4_SGN
XCVR_C10_RX_ADP_DFE_FXTAP5
XCVR_C10_RX_ADP_DFE_FXTAP5_SGN
XCVR_C10_RX_ADP_DFE_FXTAP6
XCVR_C10_RX_ADP_DFE_FXTAP6_SGN
XCVR_C10_RX_ADP_DFE_FXTAP7
XCVR_C10_RX_ADP_DFE_FXTAP7_SGN
XCVR_C10_RX_ADP_DFE_FXTAP8
XCVR_C10_RX_ADP_DFE_FXTAP8_SGN
XCVR_C10_RX_ADP_DFE_FXTAP9
XCVR_C10_RX_ADP_DFE_FXTAP9_SGN
XCVR_C10_RX_ADP_LFEQ_FB_SEL
XCVR_C10_RX_ADP_ONETIME_DFE
XCVR_C10_RX_ADP_VGA_SEL
XCVR_C10_RX_ADP_VREF_SEL
XCVR_C10_RX_BYPASS_EQZ_STAGES_234
XCVR_C10_RX_EQ_BW_SEL
XCVR_C10_RX_EQ_DC_GAIN_TRIM
XCVR_C10_RX_INPUT_VCM_SEL
XCVR_C10_RX_LINK
XCVR_C10_RX_OFFSET_CANCELLATION_CTRL
XCVR_C10_RX_ONE_STAGE_ENABLE
XCVR_C10_RX_POWER_MODE
XCVR_C10_RX_QPI_ENABLE
XCVR_C10_RX_RX_SEL_BIAS_SOURCE
XCVR_C10_RX_SD_OUTPUT_OFF
XCVR_C10_RX_SD_OUTPUT_ON
XCVR_C10_RX_SD_THRESHOLD
XCVR_C10_RX_TERM_SEL
XCVR_C10_RX_TERM_TRI_ENABLE
XCVR_C10_RX_UC_RX_DFE_CAL
XCVR_C10_RX_VCCELA_SUPPLY_VOLTAGE
XCVR_C10_RX_VCM_CURRENT_ADD
XCVR_C10_RX_VCM_SEL
XCVR_C10_RX_XRX_PATH_ANALOG_MODE
XCVR_C10_TX_COMPENSATION_EN
XCVR_C10_TX_DCD_DETECTION_EN
XCVR_C10_TX_DPRIO_CGB_VREG_BOOST
XCVR_C10_TX_LINK
XCVR_C10_TX_LOW_POWER_EN
XCVR_C10_TX_POWER_MODE
XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP
XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP
XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T
XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T
XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
XCVR_C10_TX_RES_CAL_LOCAL
XCVR_C10_TX_RX_DET
XCVR_C10_TX_RX_DET_OUTPUT_SEL
XCVR_C10_TX_RX_DET_PDB
XCVR_C10_TX_SLEW_RATE_CTRL
XCVR_C10_TX_TERM_CODE
XCVR_C10_TX_TERM_SEL
XCVR_C10_TX_UC_DCD_CAL
XCVR_C10_TX_UC_GEN3
XCVR_C10_TX_UC_GEN4
XCVR_C10_TX_UC_SKEW_CAL
XCVR_C10_TX_UC_TXVOD_CAL
XCVR_C10_TX_UC_TXVOD_CAL_CONT
XCVR_C10_TX_UC_VCC_SETTING
XCVR_C10_TX_USER_FIR_COEFF_CTRL_SEL
XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL
XCVR_C10_TX_XTX_PATH_ANALOG_MODE

So yes, now we’re looking for strings in a binary file.

And yet, all this doesn’t necessarily help

With all these hints, there’s still some pure guesswork. For example, I tried

set_instance_assignment -name XCVR_C10_RX_SD_OUTPUT_ON 3 -to gtx_rxp

and the fitter gave me

    Error (15744): The settings must match one or more of these conditions:
    Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( prot_mode != SATA_RX ) OR ( sd_output_on == DATA_PULSE_6 )
    Error (15744): But the following assignments violate the above conditions:
    Error (15744): sup_mode = USER_MODE
    Error (15744): prot_mode = SATA_RX
    Error (15744): sd_output_on = DATA_PULSE_10 -- Set by Pin Assignment "XCVR_A10_RX_SD_OUTPUT_ON" (QSF Name "XCVR_A10_RX_SD_OUTPUT_ON")

So first, let’s notice that it blames a XCVR_A10_* assignment, even though I used a XCVR_C10_* assignment in the QSF file. Really.

Also note the hint that setting sup_mode to ENGINEERING_MODE would have let us off the hook. More on that below (however don’t expect much).

But how did the assigning XCVR_C10_RX_SD_OUTPUT_ON with the integer 3 turn into DATA_PULSE_10? Maybe look in PMA_RegMap.csv, mentioned above? But no, DATA_PULSE_10 is assigned 5′b01110 as a value to write to a register, and it’s the 5th value listed, so no matter if you count from zero or one, 3 is not the answer.

Maybe ct2_pma_rx_sd_simple.tcl, also mentioned above? That helps even less, as there’s no sign there that DATA_PULSE_10 would be special. In short, just play with the integer value until hitting gold. Or even better, don’t assign anything, and use the default.

Likewise, setting

set_instance_assignment -name XCVR_C10_RX_SD_OUTPUT_OFF 6 -to gtx_rxp

yields

    Error (15744): In atom 'frontend_ins|xcvr_inst|xcvr_native_a10_0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_sd.inst_twentynm_hssi_pma_rx_sd'
    Error (15744): The settings must match one or more of these conditions:
    Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( prot_mode != SATA_RX ) OR ( sd_output_off == CLK_DIVRX_2 )
    Error (15744): But the following assignments violate the above conditions:
    Error (15744): sup_mode = USER_MODE
    Error (15744): prot_mode = SATA_RX
    Error (15744): sd_output_off = CLK_DIVRX_7 -- Set by Pin Assignment "XCVR_A10_RX_SD_OUTPUT_OFF" (QSF Name "XCVR_A10_RX_SD_OUTPUT_OFF")

Attempting to enable Engineering Mode

Since ENGINEERING_MODE is often mentioned in the fitter’s error messages, I thought maybe enabling it could silence these errors and allow wider options. For example, I attempted to enable the Electrical Idle state on the transmission wires on a non-PCIe transciever by editing one of the files generated by the transceiver IP tools (xcvr_xcvr_native_a10_0.v), changing the line saying

.hssi_tx_pcs_pma_interface_bypass_pma_txelecidle("true"),

to

.hssi_tx_pcs_pma_interface_bypass_pma_txelecidle("false"),

but the fitter threw the following error:

    Error (15744): In atom 'xcvr_inst|xcvr_native_a10_0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pcs_pma_interface.inst_twentynm_hssi_tx_pcs_pma_interface'
    Error (15744): The settings must match one or more of these conditions:
    Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( bypass_pma_txelecidle == TRUE ) OR ( pcie_sub_prot_mode_tx != OTHER_PROT_MODE )
    Error (15744): But the following assignments violate the above conditions:
    Error (15744): sup_mode = USER_MODE
    Error (15744): bypass_pma_txelecidle = FALSE
    Error (15744): pcie_sub_prot_mode_tx = OTHER_PROT_MODE

So it tells me that if I want bypass_pma_txelecidle as “false” I have to either set pcie_sub_prot_mode_tx to one of the PCIe modes, or set sup_mode to ENGINEERING_MODE. Changing pcie_sub_prot_mode_tx is out of the question, because the only way to settle the conflicts reported by the fitter is to turn the entire transceiver to follow the predefined PCIe settings. Had I been able to go that path, I would have done that long ago.

So switch to Engineering Mode, whatever that means, by editing the same file, changing

.hssi_tx_pcs_pma_interface_sup_mode("user_mode"),

to

.hssi_tx_pcs_pma_interface_sup_mode("engineering_mode"),

but the fitter really didn’t like that:

    Error (15744): In atom 'xcvr_inst|xcvr_native_a10_0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pcs_pma_interface.inst_twentynm_hssi_tx_pcs_pma_interface'
    Error (15744): The settings must match one or more of these conditions:
    Error (15744): ( sup_mode OR ( sup_mode == USER_MODE )
    Error (15744): But the following assignments violate the above conditions:
    Error (15744): sup_mode = ENGINEERING_MODE

This is somewhat cryptic, because it implies that sup_mode could just evaluate “true” in some way. Anyhow, selecting ENGINEERING_MODE was rejected flat, so that’s not an option for us regular people. There’s probably some secret sauce method to allow this, but that goes beyond what is sensible to work around the tools’ restrictions.

Conclusion

Setting up a Cyclone 10 transceiver for a use other than specifically intended by the FPGA’s vendor is a visit to nomansland. Reverse engineering Quartus does help to some extent, but some issues are left to guessing.

And the transceiver itself appears to be a step backwards compared with the series-V FPGAs. It may reach higher rates, but that came at a cost. Or maybe it’s related to the different silicon process. This way or another, it’s not all that impressive.