Making any IP in the IP Catalog availabe in QSys

Introduction I needed the Cyclone V Transceiver Native PHY IP Core inside QSys. Why? Actually, part of a failed attempt to find solve a compilation error. The IP is available in Quartus 15.1′s IP Catalog, but inside the same toolkit’s QSys it doesn’t appear in the list of IPs. As discussed in this forum thread, [...]

Posted Under: FPGA,Intel FPGA (Altera),Tcl
This post was written by eli on April 30, 2018 Comments (0)

Combining PCIe and Gigabit Transceiver on Cyclone V

Overview The goal: Using one of the PCIe transceivers for something else on a Cyclone V GT FPGA Development Kit Board, while keeping the PCIe link (narrowing it down from 4x to 2x). This allows allocating some other logic to the transceiver that goes to the PCIe finger, and do the bifurcation with a PCIe [...]

Posted Under: FPGA,Intel FPGA (Altera)
This post was written by eli on April 30, 2018 Comments (3)