Power supply parameters of Xilinx’ KC705 board, obtained via PMBus

What’s this? This is a dump of some parameters of the three power supplies on the KC705 board. More precisely, these are the outputs of the “getvals” utility, which is published on this post, running with the FPGA design published on this post. The control of these power supplies is discussed in another post of [...]

Example C sources for controlling a power supply with PMBus

Overview This post is best read after another post of mine, “Controlling the power supplies on a Xilinx KC705 FPGA board with PMBus“. This C code assumes that the FPGA is loaded with the design published in this post. These are the sources of utilities I wrote to fetch parameters and update the VADJ voltage [...]

FPGA source code for a PMBus master on Xilinx KC705

Introduction This post is best read after another post of mine, “Controlling the power supplies on a Xilinx KC705 FPGA board with PMBus“. C utilities for using the design outlined below can be found in another post of mine. These are the sources for allowing a computer to monitor and control the power supplies of [...]

Controlling the power supplies on a Xilinx KC705 FPGA board with PMBus

You probably don’t want to read all of this First of all: There is a GUI tool offered by TI to monitor and control its power controller. In hindsight, I have to admit it’s probably the quick & painless way to modify the voltage of a power rail (see this post, not that I’ve tried [...]

The pin assignment of an FMC connector in CSV format

As the title says: These are the labels of an HPC (High Pin Count) FMC connector, in plain CSV format for easy handling. It was a bit odd to me that I didn’t find this info on the web myself. Just copy-paste: A1,GND A2,DP1_M2C_P A3,DP1_M2C_N A4,GND A5,GND A6,DP2_M2C_P A7,DP2_M2C_N A8,GND A9,GND A10,DP3_M2C_P A11,DP3_M2C_N A12,GND A13,GND [...]

Gtkwave notes

General Gtkwave is a simple and convenient viewer of electronic waveforms. It’s a free software tool at its best: A bit rough to start working with, but after a while it becomes clear that the decisions have been made by someone who uses the tool himself. Really recommended. So here are my jumpstart notes for [...]

Notes on USB 1.1 low-level protocol for FPGA implementation

Introduction These are the consideration and design decisions I took when designing a transparent hub for low- and full-speed USB (that is, all covered by USB 1.1, and not high-speed as required by USB 2.0). A transparent 1:1 hub is a device with one male USB plug, and one female plug. It basically substitutes an [...]

Altera NIOS II jots

About this post These are things I wrote down at different stages of introducing myself to Nios II and its environment. Nothing really consistent nor necessarily the right way to do things. Jots Open Qsys. Follow this post. Went for Nios II classic, used Nios/e (no Hardware multiplication, as the target device doesn’t have it. [...]

Remote Update from ECPQ flash on Altera Cyclone IV

Introduction This post relates to Altera (or should I say Intel FPGA?) Cyclone IV FPGAs loaded from an ECPQ flash in Active Serial x 1 (AS x 1) mode. Things written below are probably relevant to other Altera FPGAs as well, but keep in mind that Cyclone IV FPGAs have several peculiarities you won’t find [...]

Quartus/Linux: Setting PATH and environment for command-line

The classic way: $ export QUARTUS_ROOTDIR=/path/to/altera/15.1/quartus $ . $QUARTUS_ROOTDIR/adm/qenv.sh Or open a shell (will set path, but not a full environment): $ /path/to/altera/15.1/nios2eds/nios2_command_shell.sh This is good for compiling for NIOS etc.