Altera ECPQ flash access with a Nios II processor + programming bitfiles

Introduction This post outlines some technical details on accessing an Altera ECPQ flash from a Nios II processor for read, write and erase. A non-OS settings (“bare metal”) setting is assumed. And as a bonus (at the bottom of this post), how to program the flash based upon a SOF file, both with JTAG and [...]

gcc: Solving “undefined reference” even when the required library is listed with -l

It worked all so nicely on my Fedora 12 machine, and then on Ubuntu 14.04.1 it failed colossally: $ make gcc -Wall  -O3 -g -lusb-1.0 -c  -o bulkread.o bulkread.c gcc -Wall  -O3 -g -lusb-1.0 -c  -o usberrors.o usberrors.c gcc -Wall  -O3 -g -lusb-1.0 bulkread.o usberrors.o -o bulkread bulkread.o: In function `main’: bulkread.c:39: undefined reference to [...]

XEmacs / VHDL: Stop that annoying “assistance” while typing

Emacs’ (and hence XEmacs’) VHDL mode has an annoying thing about hopping in and “help me” with composing code. Type “if” and it tells me I need to add an expression. Thanks. I wouldn’t have figured it out myself. So here’s how to disable this annoyance: Add in~/.xemacs/custom.el, to the custom-set-variables clause ‘(vhdl-electric-mode nil) ‘(vhdl-stutter-mode [...]

Quartus’ timing analysis on set_input_delay and set_output_delay constraints

OK, what’s this? This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints. TimeQuest (Quartus’ timing analyzer) performs a four-corner check (max/min temperature, max/min voltage) and picks the worst slack. In the examples below, the worst case of these four corners is shown. It’s [...]

Vivado’s timing analysis on set_input_delay and set_output_delay constraints

OK, what’s this? This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints. As mentioned on the other post, the relevant timing constraints were: create_clock -name theclk -period 20 [get_ports test_clk] set_output_delay -clock theclk -max 8 [get_ports test_out] set_output_delay -clock theclk -min -3 [get_ports [...]

Meaning of set_input_delay and set_output_delay in SDC timing constraints

Introduction Synopsys Design Constraints (SDC) has been adopted by Xilinx (in Vivado, as .xdc files) as well as Altera (in Quartus, as .sdc files) and other FPGA vendors as well. Despite the wide use of this format, there seems to be some confusion regarding the constraints for defining I/O timing. This post is defines what [...]

Quartus: Packing registers into I/O cells

Often I prefer to handle I/O timing simply by ensuring that all registers are pushed into the I/O cells. Where timing matters, that is. It seems like I/O register packing isn’t the default in Quartus. Anyhow, here’s the lazy man’s recipe for this scenario. First, disable timing checking on all I/Os. This will silence the [...]