Quartus Pro 19.2: List of QSF parameter names
Due to rather peculiar reasons described in this post, I found myself looking for all QSF parameter names that Quartus recognizes. I ended up searching a binary file in Quartus’ installation directory. So this is by no means an authoritative list, but since I made it, I thought I should post it. Just in case someone else is in the business of guesswork.
So this was done with Quartus Pro 19.2 running Linux. For non-Pro Quartus 17.1, refer to this post.
This is plain text search, so quite clearly not all items appearing here are legal QSF parameters, and neither is it clear if this list is complete. Or otherwise useful, for that matter.
$ strings ./quartus/linux64/libdb_acf.so | perl -ne '/^[A-Z][A-Z0-9_]+\n*$/ && print' | sort -u
- ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS
- ACCEPTS_NEGATIVE
- ACCEPTS_OPEN
- ACCEPTS_SHORT
- ACCEPTS_TRACK_VCCIO
- ACCEPTS_WILDCARDS
- ACCEPTS_ZERO
- AC_COUPLING
- ACEX1K
- ACF_ASSIGNMENT_USE_STRING_POOL
- ACF_NOTIFY_ACF_MANAGER_ASSIGNMENTS_CHANGED
- ACF_STRING_POOL_MASSIVE_DUMP
- ACF_VARIABLE_TRAIT_TYPE_MAX_TRAIT_TYPE
- ACF_VARIABLE_TYPE_ACF_ACF_LAST_VARIABLE
- ACLK_CAT
- ACLK_RULE_IMSZER_ADOMAIN
- ACLK_RULE_NO_SZER_ACLK_DOMAIN
- ACLK_RULE_SZER_BTW_ACLK_DOMAIN
- ACTION
- ACTIVE_PARALLEL
- ACTIVE_SERIAL_CLOCK
- ACTIVE_SERIAL
- ACTIVE_SERIAL_X1
- ACTIVE_SERIAL_X4
- ADCE_ENABLED
- ADCE_FULL_BW
- ADCE_HALF_BW
- ADCE_HIGH_BW
- ADCE_HIGH_FREQ_MODE
- ADCE_LOW_BW
- ADCE_LOW_FREQ_MODE
- ADCE_MED_HIGH_BW
- ADCE_MED_HIGH_MODE
- ADCE_MED_LOW_BW
- ADCE_MED_LOW_MODE
- ADD_DEFAULT_PINS_TO_OUTPUT_VECTOR_FILE
- ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS
- ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
- ADD_TO_SIMULATION_OUTPUT_WAVEFORMS
- ADVANCED_CLOCK_OPTIMIZATION
- ADVANCED
- ADVANCED_PHYSICAL_OPTIMIZATION
- ADVANCED_PHYSICAL_RETIMING
- ADVANCED_PHYSICAL_SYNTHESIS
- ADVANCED_PHYSICAL_SYNTHESIS_REGISTER_PACKING
- ADVANCED_PRE_PHYSICAL_SYNTHESIS
- ADV_NETLIST_OPT_ALLOWED
- ADV_NETLIST_OPT_DONT_TOUCH
- ADV_NETLIST_OPT_FIT_LE_DUPLICATION
- ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTHESIS
- ADV_NETLIST_OPT_FIT_LE_RETIME
- ADV_NETLIST_OPT_METASTABLE_REGS
- ADV_NETLIST_OPT_RETIME_CORE_AND_IO
- ADV_NETLIST_OPT_STRING
- ADV_NETLIST_OPT_SYNTH_ALLOW_IP_WYS_UNMAPPING
- ADV_NETLIST_OPT_SYNTH_GATE_RETIME_1
- ADV_NETLIST_OPT_SYNTH_GATE_RETIME_2
- ADV_NETLIST_OPT_SYNTH_GATE_RETIME
- ADV_NETLIST_OPT_SYNTH_REMAP_1
- ADV_NETLIST_OPT_SYNTH_REMAP_2
- ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO
- ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
- ADV_NETLIST_OPT_TEST
- AFTER_INIT_DONE
- AGGREGATE
- AGGREGATE_REVISION
- AGGRESSIVE_AREA
- AGGRESSIVE_COMPILE_TIME___INTERNAL
- AGGRESSIVE_COMPILE_TIME
- AGGRESSIVE
- AGGRESSIVE_POWER
- AHDL_FILE
- AHDL_INCLUDE_FILE
- AHDL_LIMIT_INT_TO_32
- AHDL_TEXT_DESIGN_OUTPUT_FILE
- AHDL_USE_LPM_FOR_OPERATORS
- ALIAS
- ALL_EDGE
- ALL_EXCEPT_COMBINATIONAL_LOGIC_ELEMENT_OUTPUTS
- ALL_NODES
- ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION
- ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
- ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
- ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
- ALLOW_CASCADE_GPLL_TO_LVDS_TX
- ALLOW_CHILD_PARTITIONS
- ALLOW_DSP_RETIMING
- ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER
- ALLOW_MULTIPLE_PERSONAS
- ALLOW_PARALLEL_TERMINATION
- ALLOW_POWER_UP_DONT_CARE
- ALLOW_RAM_RETIMING
- ALLOW_REGISTER_DUPLICATION
- ALLOW_REGISTER_MERGING
- ALLOW_REGISTER_RETIMING
- ALLOW_ROUTING_TO_PERIPHERY_THROUGH_GLOBAL_NETWORK
- ALLOW_SERIES_TERMINATION
- ALLOW_SERIES_WITH_CALIBRATION_TERMINATION
- ALLOW_SEU_FAULT_INJECTION
- ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
- ALLOW_SYNCH_CTRL_USAGE
- ALLOW_VCCR_VCCT_PER_BANK
- ALLOW_VCCR_VCCT_PER_SIX_PACK
- ALLOW_XOR_GATE_USAGE
- ALL_PATHS
- ALL_STAGES_ENABLED
- ALM_REGISTER
- ALM_REGISTER_PACKING_EFFORT
- ALTERA_A10_IOPLL_BOOTSTRAP
- ALTERA_INTERNAL_FIB
- ALTERA
- ALWAYS_ALLOW
- ALWAYS_ENABLE_INPUT_BUFFERS
- ALWAYS
- ALWAYS_REGENERATE_IP
- ALWAYS_REGENERATE_IP_SIM
- ALWAYS_WRITE_TO_FILE
- ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS
- ANALYZE_LATCHES
- ANALYZE_METASTABILITY
- APEX20KC
- APEX20K_CLIQUE_TYPE
- APEX20K_CONFIG_DEVICE_JTAG_USER_CODE
- APEX20K_CONFIGURATION_DEVICE
- APEX20K_CONFIGURATION_SCHEME
- APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- APEX20K_DEVICE_IO_STANDARD
- APEX20KE_DEVICE_IO_STANDARD
- APEX20KE
- APEX20KF_DEVICE_IO_STANDARD
- APEX20K_JTAG_USER_CODE
- APEX20K
- APEX20K_LOCAL_ROUTING_SOURCE
- APEX20K_OPTIMIZATION_TECHNIQUE
- APEX20K_TECHNOLOGY_MAPPER
- APEX_FITTER_TYPE
- APEXII_1_8V_HSTL
- APEX_II_CONFIGURATION_SCHEME
- APEXII_CONFIGURATION_SCHEME
- APEXII_DEVICE_IO_STANDARD
- AREA
- AREF_VOLT_0
- AREF_VOLT_0P5
- AREF_VOLT_0P75
- AREF_VOLT_1P0
- ARM_ASM_COMMAND_LINE
- ARM_CPP_COMMAND_LINE
- ARM_LINK_COMMAND_LINE
- ARMSTRONG_CARRY_CHAIN_LENGTH
- ARMSTRONG_OPTIMIZATION_TECHNIQUE
- ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE
- AS_BIDIRECTIONAL
- ASCII_REPORT_FILE
- AS_FREQ_100MHZ
- AS_FREQ_108MHZ
- AS_FREQ_115MHZ_IOSC
- AS_FREQ_125MHZ
- AS_FREQ_133MHZ
- AS_FREQ_166_6MHZ
- AS_FREQ_25MHZ_IOSC
- AS_FREQ_25MHZ
- AS_FREQ_38MHZ_IOSC
- AS_FREQ_50MHZ
- AS_FREQ_58MHZ_IOSC
- AS_FREQ_71_5MHZ
- AS_FREQ_77MHZ_IOSC
- AS_FREQ_80MHZ
- ASIC_EMULATION_FAST_FLOW
- ASIC_PROTOTYPING_ADVANCED
- ASIC_PROTOTYPING_FEATURES
- ASIC_PROTOTYPING_LATCH_SUPPORT
- ASIC_PROTOTYPING
- ASIC_PROTOTYPING_READBACK_WRITEBACK
- AS_INPUT_TRI_STATED
- AS_INPUT_TRI_STATED_WITH_BUS_HOLD
- AS_INPUT_TRI_STATED_WITH_WEAK_PULL_UP
- ASM_FILE
- ASM_OPTIONS_FILE_KEYWORD
- AS_OUTPUT_DRIVING_AN_UNSPECIFIED_SIGNAL
- AS_OUTPUT_DRIVING_GROUND
- AS_OUTPUT_DRIVING_VCC
- ASP_ASM_COMMAND_LINE
- ASP_CPP_COMMAND_LINE
- ASP_LINK_COMMAND_LINE
- ASSEMBLER_ASSIGNMENT
- ASSG_CAT
- ASSG_RULE_MISSING_FMAX
- ASSG_RULE_MISSING_TIMING
- AS_SIGNALPROBE_OUTPUT
- ASSIGNMENT_GROUP_ASSIGNMENT
- ASSIGNMENT_GROUP_EXCEPTION
- ASSIGNMENT_GROUP
- ASSIGNMENT_GROUP_MEMBER
- AS_VREFA
- AS_VREFB
- AS_VREF
- ATSH
- ATTRACTION_GROUP
- ATTRACTION_GROUP_SOFT_REGION
- ATUH
- ATUSH
- ATUSL
- AUATI
- AUATL
- AUATUH
- AUATUSH
- AUATUS
- AUTO_C3_M9K_BIT_SKIP
- AUTO_CARRY_CHAINS
- AUTO_CARRY
- AUTO_CASCADE_CHAINS
- AUTO_CASCADE
- AUTO_CLOCK_ENABLE_RECOGNITION
- AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS
- AUTO_DELAY_CHAINS
- AUTO_DISCOVER_AND_SORT
- AUTO_DISCOVERY
- AUTO_DSP_RECOGNITION
- AUTO_ENABLE_SMART_COMPILE
- AUTO_EXPORT_INCREMENTAL_COMPILATION
- AUTO_EXPORT_VER_COMPATIBLE_DB
- AUTO_FAST_INPUT_REGISTERS
- AUTO_FAST_OUTPUT_ENABLE_REGISTERS
- AUTO_FAST_OUTPUT_REGISTERS
- AUTO_FIT
- AUTO_GLOBAL_CLOCK
- AUTO_GLOBAL_CLOCK_MAX
- AUTO_GLOBAL_MEM_CTRL
- AUTO_GLOBAL_MEMORY_CONTROLS
- AUTO_GLOBAL_OE
- AUTO_GLOBAL_OE_MAX
- AUTO_GLOBAL_REG_CTRL
- AUTO_GLOBAL_REG_CTRL_MAX
- AUTO_GLOBAL_REGISTER_CONTROLS
- AUTO_IMPLEMENT_IN_ROM
- AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE
- AUTO_INCREMENT_EPROM_JTAG_CODE
- AUTO_INCREMENT_USER_JTAG_CODE
- AUTO_INPUT_REGISTER
- AUTO_INPUT_REGISTERS
- AUTO_INSERT_SLD_HUB_ENTITY
- AUTO_INSERT_SLD_INCR_NODE_ENTITY
- AUTO_INSERT_SLD_NODE_ENTITY
- AUTO_LCELL_INSERTION
- AUTO
- AUTOMATICALLY
- AUTOMATIC_DANGLING_PORT_TIEOFF
- AUTOMATIC
- AUTO_MERGE_PLLS
- AUTO_MODIFIED_PACKED_REGISTERS
- AUTONOMOUS_PCIE_HIP
- AUTO_OPEN_DRAIN
- AUTO_OPEN_DRAIN_PINS
- AUTO_OUTPUT_ENABLE_REGISTER
- AUTO_OUTPUT_REGISTER
- AUTO_OUTPUT_REGISTERS
- AUTO_PACKED_REG_CYCLONE
- AUTO_PACKED_REGISTERS_ARMSTRONG
- AUTO_PACKED_REGISTERS_CYCLONE
- AUTO_PACKED_REGISTERS
- AUTO_PACKED_REGISTERS_MAXII
- AUTO_PACKED_REGISTERS_MAX
- AUTO_PACKED_REGISTERS_STRATIXII
- AUTO_PACKED_REGISTERS_STRATIX
- AUTO_PACKED_REGISTERS_TSUNAMI
- AUTO_PARALLEL_EXPANDERS
- AUTO_PARALLEL_SYNTHESIS
- AUTO_PERIPH
- AUTO_PEXP
- AUTO_QIC_EXPORT
- AUTO_QXP_PARTITION
- AUTO_RAM_BLOCK_BALANCING
- AUTO_RAM_RECOGNITION
- AUTO_RAM_TO_LCELL_CONVERSION
- AUTO_RESERVE_CLKUSR_FOR_CALIBRATION
- AUTO_RESOURCE_SHARING
- AUTO_RESTART_CONFIGURATION
- AUTO_RESTART
- AUTO_ROM
- AUTO_ROM_RECOGNITION
- AUTO_SHIFT_REGISTER_RECOGNITION
- AUTO_SLD_HUB_ENTITY
- AUTO_TURBO_BIT
- AUTO_USE_SIMULATION_PDB_NETLIST
- AVAUA
- AVAUATA
- AVAUATI
- AVAUATUH
- AVAUATUSH
- AVAUI
- AVAUL
- AVST_CLK_RESERVED
- AVST_DATA15_0_RESERVED
- AVST_DATA31_16_RESERVED
- AVST_VALID_RESERVED
- AVST_X16
- AVST_X32
- AVST_X8
- AVUH
- AWAVA
- AWAVAUA
- AWAVAUATA
- AWAVAUATI
- AWAVAUATL
- AWAVAUATUH
- AWAVAUATU
- AWAVAUATUSH
- AWAVAUATUS
- AWAVAUI
- AWAVAUL
- AWAVAUM
- AWAVE
- AWAVI
- AWAVL
- AWAVM
- BACKUP_BATTERY_RAM
- BAK_AUTO_EXPORT
- BAK_EXPORT_DIR
- BALANCED
- BASE_CLOCK
- BASED_ON_CLOCK_SETTINGS
- BASE
- BASEO
- BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
- BASE_REVISION
- BASE_REVISION_PROJECT_OUTPUT_DIRECTORY
- BASIC
- BDF_FILE
- BEST
- BIAS_INT
- BIAS_VCMDRV
- BIDIRECTIONAL
- BINARY_FILE
- BLACKBOX
- BLOCK_DESIGN_NAMING
- BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
- BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS
- BLOCK_RAM_TO_MLAB_CELL_CONVERSION
- BOARD
- BOARD_MODEL_CUSTOM
- BOARD_MODEL_EBD_FAR_END
- BOARD_MODEL_EBD_FILE_NAME
- BOARD_MODEL_EBD_SIGNAL_NAME
- BOARD_MODEL_FAR_C
- BOARD_MODEL_FAR_DIFFERENTIAL_R
- BOARD_MODEL_FAR_PULLDOWN_R
- BOARD_MODEL_FAR_PULLUP_R
- BOARD_MODEL_FAR_SERIES_R
- BOARD_MODEL_NEAR_C
- BOARD_MODEL_NEAR_DIFFERENTIAL_R
- BOARD_MODEL_NEAR_PULLDOWN_R
- BOARD_MODEL_NEAR_PULLUP_R
- BOARD_MODEL_NEAR_SERIES_C
- BOARD_MODEL_NEAR_SERIES_R
- BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
- BOARD_MODEL_NEAR_TLINE_LENGTH
- BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
- BOARD_MODEL_TERMINATION_V
- BOARD_MODEL_TLINE_C_PER_LENGTH
- BOARD_MODEL_TLINE_LENGTH
- BOARD_MODEL_TLINE_L_PER_LENGTH
- BOOST_1_STEP
- BOOST_2_STEP
- BOOST_3_STEP
- BOOST_4_STEP
- BOOST_5_STEP
- BOOST_6_STEP
- BOOST_7_STEP
- BOOST
- BOOT_SEL_PIN
- BOTH_EDGES
- BREAKPOINT_FILE
- BREAKPOINT
- BREAKPOINT_LINE_NUMBER
- BREAKPOINT_STATE
- BSF_FILE
- BW_FULL_12P5
- BW_HALF_6P5
- BYPASS_ERROR_RELEASE_CLEARS_BEFORE_TRISTATES_1S25
- BYPASS
- BYPASS_OFF
- BYPASS_STAGES_234
- BYTE_ORDER
- BYYPASS_STAGES_234
- C0H9
- C0M9
- C3_M9K_BIT_SKIP
- CALIBRATED
- CALIBRATED_SSTL
- CAL_SIM_ACTIVATOR
- CAP_NAME
- CARE
- CARRY_CHAIN_LENGTH_ARMSTRONG
- CARRY_CHAIN_LENGTH_DALI
- CARRY_CHAIN_LENGTH_FLEX10K
- CARRY_CHAIN_LENGTH_FLEX6K
- CARRY_CHAIN_LENGTH
- CARRY_CHAIN_LENGTH_TSUNAMI
- CARRY_CHAIN_LENGTH_YEAGER
- CARRY_OUT_PINS_LCELL_INSERT
- CASCADE_CHAIN_LENGTH
- CASE_SENSITIVE
- CAT_ASSEMBLER
- CAT_ASSIGNMENT_GROUP
- CAT_DESIGN_ASSISTANT
- CAT_FITTER
- CAT_INCREMENTAL_COMPILATION
- CAT_LOCATION_PIN
- CAT_LOGICLOCK
- CAT_MAPPER_SYNTHESIS
- CAT_NETO
- CAT_PARAMETERS
- CAT_POWER_ESTIMATION
- CAT_PROGRAMMER
- CAT_SIGNALPROBE
- CAT_SIGNALTAP
- CAT_SIMULATION
- CAT_SOFTWARE_BUILDER
- CAT_TIMEGROUP
- CAT_TIMING_ANALYSIS
- CAT_TIMING
- CB_CLKUSR
- CB_INTOSC
- CDF_FILE
- CDR_BANDWIDTH_PRESET
- CEI_11100_LR
- CEI_11100_SR
- CEI_4976_LR
- CEI_4976_SR
- CEI_6375_LR
- CEI_6375_SR
- CEI_9950_LR
- CEI_9950_SR
- CE_OPTION
- C_FILE
- CHAIN_FILE
- CHECK_AGAINST_TSM_DELAY
- CHECK_OUTPUTS
- CHIP
- CHIP_WIDE_OE
- CHIP_WIDE_RESET
- CKN_CK_PAIR
- CLAMPING_DIODE
- CLIQUE
- CLIQUE_TYPE_APEX20K
- CLIQUE_TYPE_DALI
- CLIQUE_TYPE_FLEX10K
- CLIQUE_TYPE_FLEX6K
- CLIQUE_TYPE
- CLIQUE_TYPE_MAX7K
- CLK_CAT
- CLK_FPLL_VREG_BOOST_1_STEP
- CLK_FPLL_VREG_BOOST_2_STEP
- CLK_FPLL_VREG_BOOST_3_STEP
- CLK_FPLL_VREG_BOOST_4_STEP
- CLK_FPLL_VREG_BOOST_5_STEP
- CLK_FPLL_VREG_BOOST_6_STEP
- CLK_FPLL_VREG_BOOST_7_STEP
- CLK_FPLL_VREG_NO_VOLTAGE_BOOST
- CLKLOCKX1_INPUT_FREQ
- CLK_RULE_ALL
- CLK_RULE_CLKNET_CLKSPINES
- CLK_RULE_CLKNET_CLKSPINES_THRESHOLD
- CLK_RULE_COMB_CLOCK
- CLK_RULE_GATED_CLK_FANOUT
- CLK_RULE_GATING_SCHEME
- CLK_RULE_INPINS_CLKNET
- CLK_RULE_INV_CLOCK
- CLK_RULE_MIX_EDGES
- CLKUSR
- CLOCK_ANALYSIS_ONLY
- CLOCK_DIVISOR
- CLOCK_ENABLE_MULTICYCLE_HOLD
- CLOCK_ENABLE_MULTICYCLE
- CLOCK_ENABLE_ROUTING
- CLOCK_ENABLE_SOURCE_MULTICYCLE_HOLD
- CLOCK_ENABLE_SOURCE_MULTICYCLE
- CLOCK_FREQUENCY
- CLOCK_HOLD_UNCERTAINTY
- CLOCK
- CLOCK_MAX_ROUTING
- CLOCK_REGION
- CLOCK_SETTINGS
- CLOCK_SETUP_UNCERTAINTY
- CLOCK_SOURCE
- CLOCK_SPINE
- CLOCK_TO_OUTPUT_DELAY
- CLOUD_NOTIFY_COMPILE_ID
- CLOUD_NOTIFY_ENABLE
- CLOUD_NOTIFY_ENABLE_LOGGING
- CLOUD_NOTIFY_GROUP_ID
- CLOUD_NOTIFY_LOGGING
- CLOUD_NOTIFY_PROXY
- CLOUD_NOTIFY_SEND_CRIT_WARNINGS
- CLOUD_NOTIFY_SEND_ERRORS
- CLOUD_NOTIFY_SEND_JSON_REPORTS
- CLOUD_NOTIFY_SERVER
- CLOUD_NOTIFY_TOKEN
- COMMAND_MACRO_FILE
- COMMAND_MACRO_MODE
- COMPANION_REVISION_NAME
- COMPARED_CLOCK
- COMPATIBLE_PLACEMENT_AND_ROUTING
- COMPATIBLE_PLACEMENT
- COMPILATION_LEVEL
- COMPILE_NEW_PROJECT
- COMPILER_ACTION_POINTS
- COMPILER_ASSIGNMENT
- COMPILER_CONFIGURED
- COMPILER_SETTINGS
- COMPILER_SETTINGS_LIST
- COMPILER_SIGNATURE_ID
- COMPRESSION_MODE
- CONBINATION10
- CONBINATION11
- CONBINATION1
- CONBINATION2
- CONBINATION3
- CONBINATION4
- CONBINATION5
- CONBINATION6
- CONBINATION7
- CONBINATION8
- CONBINATION9
- CONFIG_DEVICE_JTAG_USER_CODE_DALI
- CONFIG_DEVICE_JTAG_USER_CODE_FLEX6K
- CONFIG_DEVICE_JTAG_USER_CODE
- CONFIGURATION_CLOCK_DIVISOR
- CONFIGURATION_CLOCK_FREQUENCY
- CONFIGURATION_DEVICE_DALI
- CONFIGURATION_DEVICE_FLEX6K
- CONFIGURATION_DEVICE
- CONFIGURATION_PINS
- CONFIGURATION_SCHEME_DALI
- CONFIGURATION_SCHEME_FLEX6K
- CONFIGURATION_SCHEME
- CONFIGURATION_VCCIO_LEVEL
- CONNECT_BIDIR_PIN_FROM_SLD_INCR_NODE_ENTITY_PORT
- CONNECT_BIDIR_PIN_FROM_SLD_NODE_ENTITY_PORT
- CONNECT_FROM_SLD_INCR_NODE_ENTITY_PORT
- CONNECT_FROM_SLD_NODE_ENTITY_PORT
- CONNECT_PIN_FROM_SLD_INCR_NODE_ENTITY_PORT
- CONNECT_PIN_FROM_SLD_NODE_ENTITY_PORT
- CONNECT_PIN_TO_SLD_INCR_NODE_ENTITY_PORT
- CONNECT_PIN_TO_SLD_NODE_ENTITY_PORT
- CONNECT_SIGNALPROBE_PIN
- CONNECT_TO
- CONNECT_TO_SLD_INCR_NODE_ENTITY_PORT
- CONNECT_TO_SLD_NODE_ENTITY_PORT
- CONTAINS_FAMILY_SPECIFIC_DATA
- CONVERT_ALOAD_TO_CLEAR_PRESET
- CONVERT_PR_WARNINGS_TO_ERRORS
- COPY_IF_NODE_IS_DUPLICATED
- COPY_VARIABLE_TYPE_IN_PIN_PLANNER
- CORE_INITIALIZATION_AND_UPDATE
- CORE_INITIALIZATION
- CORE
- CORE_ONLY_PLACE_REGION
- CORE_UPDATE
- COVERAGE_COMPLETE_PANEL_ENABLED
- COVERAGE
- COVERAGE_MISSING_0_VALUE_PANEL_ENABLED
- COVERAGE_MISSING_1_VALUE_PANEL_ENABLED
- CPH9
- CPP_FILE
- CPP_INCLUDE_FILE
- CPRI_12500
- CPRI_E12HV
- CPRI_E12LVIII
- CPRI_E12LVII
- CPRI_E12LV
- CPRI_E24LVIII
- CPRI_E24LVII
- CPRI_E24LV
- CPRI_E30LVIII
- CPRI_E30LVII
- CPRI_E30LV
- CPRI_E48LVIII
- CPRI_E48LVII
- CPRI_E60LVIII
- CPRI_E60LVII
- CPRI_E6HV
- CPRI_E6LVIII
- CPRI_E6LVII
- CPRI_E6LV
- CPRI_E96LVIII
- CPRI_E99LVIII
- CPRI
- CRC_ERROR_CHECKING
- CRC_ERROR_CHECKING_YEAGER
- CRC_ERROR_OPEN_DRAIN
- CREATED_BY
- CREATED_FROM
- CREATE_PARTITION_BOUNDARY_PORTS
- CREATE_SIGNALPROBE_PIN
- CRITICAL_CHAIN_VIEWER
- CROSS_BOUNDARY_OPTIMIZATIONS
- CURRENT_STRENGTH
- CURRENT_STRENGTH_NEW
- CUSP_FILE
- CUSTOM_BUILD_COMMAND_LINE
- CUSTOM_CLOCK_TREE
- CUT_OFF_CLEAR_AND_PRESET_PATHS
- CUT_OFF_IO_PIN_FEEDBACK
- CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS
- CUT_OFF_READ_DURING_WRITE_PATH
- CUT_OFF_READ_DURING_WRITE_PATHS
- CVPCIE_CONFDONE_OPEN_DRAIN
- CVPCIE_MODE
- CVP_CONFDONE_OPEN_DRAIN
- CVP_MODE
- CVP_REVISION
- CVWF
- CYCLONE_CONFIGURATION_DEVICE
- CYCLONE_CONFIGURATION_SCHEME
- CYCLONEII_CONFIGURATION_SCHEME
- CYCLONEIII_CONFIGURATION_DEVICE
- CYCLONEIII_CONFIGURATION_SCHEME
- CYCLONEII_M4K_COMPATIBILITY
- CYCLONEII_OPTIMIZATION_TECHNIQUE
- CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION
- CYCLONEII_TERMINATION
- CYCLONE_OPTIMIZATION_TECHNIQUE
- D1_DELAY
- D1_FINE_DELAY
- D2_DELAY
- D3_DELAY
- D4_DELAY
- D4_FINE_DELAY
- D5_DELAY
- D5_FINE_DELAY
- D5_OCT_DELAY
- D5_OE_DELAY
- D6_DELAY
- D6_FINE_DELAY
- D6_OCT_DELAY
- D6_OE_DELAY
- D6_OE_FINE_DELAY
- DA_CUSTOM_RULE_FILE
- DANGEROUS_EXCEPTION_FOR_READ_ONLY_CONTACT_INFRASTRUCTURE_GROUP
- DATA0_PIN
- DATA0_RESERVED
- DATA15_8_RESERVED
- DATA1_RESERVED
- DATA31_16_RESERVED
- DATA7_1_RESERVED
- DATA7_2_RESERVED
- DATA7_5_RESERVED
- DC_COUPLING_EXTERNAL_RESISTOR
- DC_COUPLING_EXTERNAL_TERMINATION
- DC_COUPLING_INTERNAL_100_OHMS
- DC_CURRENT_FOR_ELECTROMIGRATION_CHECK
- DCLK
- DCLK_PIN
- DCLK_RESERVED
- DDIO_INPUT_REGISTER
- DDIO_OUTPUT_REGISTER_DISTANCE
- DDIO_OUTPUT_REGISTER
- DEBUG_BOUNDARY
- DEBUG_TRACE
- DECREASE_INPUT_DELAY_TO_INPUT_REGISTER
- DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER
- DEFAULT_DESIGN_ASSISTANT_SETTINGS
- DEFAULT_DEVICE_OPTIONS
- DEFAULT_EQUIVALENCE_CHECKER_SETTINGS
- DEFAULT_HARDCOPY_SETTINGS
- DEFAULT_HOLD_MULTICYCLE
- DEFAULT
- DEFAULT_LOGIC_OPTIONS
- DEFAULT_NETLIST_VIEWER_SETTINGS
- DEFAULT_PARAMETERS
- DEFAULT_SDC_FILE
- DEFAULT_TIMING_REQUIREMENTS
- DEFAULT_VALUE
- DELAY_MATCH_RELATED_CLOCKS
- DELAY_SETTING_FROM_CORE_TO_CE_INPUT_REGISTER
- DELAY_SETTING_FROM_CORE_TO_CE_IO_REGISTER
- DELAY_SETTING_FROM_CORE_TO_CE_OE_REGISTER
- DELAY_SETTING_FROM_CORE_TO_CE_OUTPUT_REGISTER
- DELAY_SETTING_FROM_CORE_TO_OUTPUT_REGISTER
- DELAY_SETTING_FROM_VIO_TO_CORE
- DELAY_SETTING_TO_CORE_APEX20K
- DELAY_SETTING_TO_CORE_DALI
- DELAY_SETTING_TO_CORE_FLEX10K
- DELAY_SETTING_TO_CORE_FLEX6K
- DELAY_SETTING_TO_CORE_TO_OUTPUT_REGISTER
- DELAY_SETTING_TO_CORE_TSUNAMI
- DELAY_SETTING_TO_CORE_YEAGER
- DELAY_SETTING_TO_INPUT_REGISTER
- DELAY_SETTING_TO_OUTPUT_ENABLE
- DELAY_SETTING_TO_OUTPUT
- DELAY_SETTING_TO_ZBT
- DEPENDENCY_FILE
- DESIGN_ASISTANT_INCLUDE_IP_BLOCKS
- DESIGN_ASSISTANT_ASSIGNMENT
- DESIGN_ASSISTANT_INCLUDE_IP_BLOCKS
- DESIGN_ASSISTANT_MAX_VIOLATIONS_PER_RULE
- DESIGN_HASH
- DESIGN_PARTITION
- DEV_FAMILY_ACEX1K
- DEV_FAMILY_APEX20KC
- DEV_FAMILY_APEX20KE
- DEV_FAMILY_APEX20K
- DEV_FAMILY_APEXII
- DEV_FAMILY_ARMSTRONG
- DEV_FAMILY_ARRIAIIGZ
- DEV_FAMILY_ARRIAVGZ
- DEV_FAMILY_ARRIAV
- DEV_FAMILY_ASC
- DEV_FAMILY_AURORA
- DEV_FAMILY_BEDROCK
- DEV_FAMILY_BS
- DEV_FAMILY_CUDA
- DEV_FAMILY_CYCLONE10GX
- DEV_FAMILY_CYCLONE10LP
- DEV_FAMILY_CYCLONEII
- DEV_FAMILY_CYCLONEIVE
- DEV_FAMILY_CYCLONEV
- DEV_FAMILY_DALI
- DEV_FAMILY_EMBEDDED_PROCESSOR
- DEV_FAMILY_EPC1
- DEV_FAMILY_EPC2
- DEV_FAMILY_EXCALIBUR_ARM
- DEV_FAMILY_FALCONMESA_EMULATOR
- DEV_FAMILY_FALCONMESA
- DEV_FAMILY_FLASH_LOGIC
- DEV_FAMILY_FLEX10KA
- DEV_FAMILY_FLEX10KB
- DEV_FAMILY_FLEX10KE
- DEV_FAMILY_FLEX10K
- DEV_FAMILY_FLEX6K
- DEV_FAMILY_FLEX8000
- DEV_FAMILY_FUSION
- DEV_FAMILY_HCXIV
- DEV_FAMILY_HCX
- DEV_FAMILY_INTEL_CFI
- DEV_FAMILY_MAX3000A
- DEV_FAMILY_MAX7000AE
- DEV_FAMILY_MAX7000A
- DEV_FAMILY_MAX7000B
- DEV_FAMILY_MAX7000S
- DEV_FAMILY_MAX9000
- DEV_FAMILY_MAXV
- DEV_FAMILY_NADDER_EMULATOR
- DEV_FAMILY_NADDER
- DEV_FAMILY_NIGHTFURY
- DEV_FAMILY_PGM_DUMMY_FAMILY
- DEV_FAMILY_PGM_EOL_FAMILY
- DEV_FAMILY_PIRANHA
- DEV_FAMILY_SOC_HPS
- DEV_FAMILY_STINGRAY
- DEV_FAMILY_STRATIXHC
- DEV_FAMILY_STRATIXIIGX
- DEV_FAMILY_STRATIXIIGXLITE
- DEV_FAMILY_STRATIXV
- DEV_FAMILY_SYN
- DEV_FAMILY_TARPON
- DEV_FAMILY_TGX
- DEV_FAMILY_TITAN
- DEV_FAMILY_TORNADO
- DEV_FAMILY_TSUNAMI
- DEV_FAMILY_VERMEER
- DEV_FAMILY_VIRTUAL_JTAG_TAP
- DEV_FAMILY_YEAGER
- DEV_FAMILY_ZIPPLEBACK
- DEVICE_FILTER_PACKAGE
- DEVICE_FILTER_PIN_COUNT
- DEVICE_FILTER_SPEED_GRADE
- DEVICE_FILTER_VOLTAGE
- DEVICE_INITIALIZATION_CLOCK
- DEVICE_IO_STANDARD_APEX20KE
- DEVICE_IO_STANDARD_APEX20KF
- DEVICE_IO_STANDARD_APEX20K
- DEVICE_IO_STANDARD_DALI
- DEVICE_IO_STANDARD_FLEX10K
- DEVICE_IO_STANDARD_FLEX6K
- DEVICE_IO_STANDARD
- DEVICE_IO_STANDARD_MAX7000
- DEVICE_IO_STANDARD_YEAGER
- DEVICE
- DEVICE_MIGRATION_LIST
- DEVICE_TECHNOLOGY_MIGRATION_LIST
- DEV_PART_GENERIC
- DEV_PART_INVALID
- DEV_PART_MAX
- DFE_PI_BW_0P5GHZ
- DFE_PI_BW_10GHZ
- DFE_PI_BW_2P5GHZ
- DFE_PI_BW_5GHZ
- DIFFERENTIAL
- DIRECT_FORMAT
- DIRECT
- DISABLE_CONF_DONE_AND_NSTATUS_ON_EPROM
- DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE
- DISABLE_CORE_CLK
- DISABLE_DA_GX_RULE
- DISABLE_DA_RULE
- DISABLED
- DISABLE_DSP_NEGATE_INFERENCING
- DISABLE_EMBEDDED_TIMING_CONSTRAINT
- DISABLE
- DISABLE_MLAB_RAM_USE
- DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE
- DISABLE_OCP_HW_EVAL
- DISABLE_PLL_COMPENSATION_DELAY_CHANGE_WARNING
- DISABLE_REGION_HIERARCHY
- DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
- DISABLE_REGISTER_POWERUP_INITIALIZATION
- DISABLE_TRI
- DISALLOW_GLOBAL_ASSIGNMENT_IN_QIP
- DIV2
- DIV4
- DIVIDE_BASE_CLOCK_BY
- DIVIDE_BASE_CLOCK_PERIOD_BY
- DM_PIN
- DO_COMBINED_ANALYSIS
- DO_MIN_ANALYSIS
- DO_MINMAX_ANALYSIS_USING_RISEFALL_DELAYS
- DO_MIN_TIMING
- DONE
- DONT_AUTODISCOVER_CPP_FILES
- DONT_CARE
- DONT_CONVERT_TO_USER_FRIENDLY_STRING
- DONT_COPY_TO_CREATED_COMPANION_REVISION
- DONT_COPY_TO_NEW_FILE_FORMAT
- DONT_COPY_TO_NEW_REVISION
- DONT_MERGE_REGISTER
- DONT_REUSE_REMOVED_ASSIGNMENT
- DONT_TOUCH_USER_CELL
- DO_POST_BUILD_COMMAND_LINE
- DO_SYSTEM_FMAX
- DOWN
- DP_1620
- DP_2700
- DP_5400
- DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1
- DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1
- DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1
- DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1
- DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1
- DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1
- DPRAM_DEEP_MODE_INPUT_EPXA4_10
- DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10
- DPRAM_DEEP_MODE_OUTPUT_EPXA4_10
- DPRAM_DUAL_PORT_MODE_INPUT_EPXA1
- DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10
- DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1
- DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10
- DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1
- DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10
- DPRAM_INPUT_EPXA4_10
- DPRAM_OTHER_SIGNALS_EPXA4_10
- DPRAM_OUTPUT_EPXA4_10
- DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10
- DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10
- DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10
- DPRAM_WIDE_MODE_INPUT_EPXA4_10
- DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10
- DPRAM_WIDE_MODE_OUTPUT_EPXA4_10
- DPRIO_CHANNEL_NUM
- DPRIO_CRUCLK_NUM
- DPRIO_INTERFACE_REG
- DPRIO_NORMAL_STATUS
- DPRIO_QUAD_NUM
- DPRIO_QUAD_PLL_NUM
- DPRIO_TX_PLL0_REFCLK_NUM
- DPRIO_TX_PLL1_REFCLK_NUM
- DPRIO_TX_PLL_NUM
- DQ_GROUP
- DQ_PIN
- DQSB_DQS_PAIR
- DQS_DELAY
- DQS_ENABLE_DELAY_CHAIN
- DQS_FREQUENCY
- DQS_LOCAL_CLOCK_DELAY_CHAIN
- DQSOUT_DELAY_CHAIN
- DQS_SHIFT
- DQS_SYSTEM_CLOCK
- DRC_DEADLOCK_STATE_LIMIT
- DRC_DETAIL_MESSAGE_LIMIT
- DRC_FANOUT_EXCEEDING
- DRC_GATED_CLOCK_FEED
- DRC_MAX_TOP_FANOUT
- DRC_REPORT_FANOUT_EXCEEDING
- DRC_REPORT_MAX_TOP_FANOUT
- DRC_REPORT_TOP_FANOUT
- DRC_TOP_FANOUT
- DRC_VIOLATION_MESSAGE_LIMIT
- DSE_SEND_REPORT_PANEL
- DSE_SERVER_SEND_REPORTS
- DSE_SERVER_URL
- DSE_SYNTH_EXTRA_EFFORT_MODE
- DSE_WORKER_ID
- DSM_DFT_OUT
- DSM_LSB_OUT
- DSM_MSB_OUT
- DSP_BLOCK_BALANCING_IMPLEMENTATION
- DSP_BLOCK_BALANCING
- DSP_BLOCKS
- DSPBUILDER_FILE
- DSP_REGISTER_PACKING
- DUAL_FAST_REGIONAL_CLOCK
- DUAL_IMAGES
- DUAL_PURPOSE_CLOCK_PIN_DELAY
- DUAL_REGIONAL_CLOCK
- DUPLICATE_ATOM
- DUPLICATE_HIERARCHY_DEPTH
- DUPLICATE_LOGIC_EXTRACTION
- DUPLICATE_REGISTER_EXTRACTION
- DUPLICATE_REGISTER
- DUP_LOGIC_EXTRACTION
- DUP_REG_EXTRACTION
- DUTY_CYCLE
- DYNAMIC_ATOM_CONNECTION
- DYNAMIC_CTL
- DYNAMIC_OCT_CONTROL_GROUP
- EARLY_CLOCK_LATENCY
- ECO_ALLOW_ROUTING_CHANGES
- ECO_OPTIMIZE_TIMING
- ECO_REGENERATE_REPORT
- ECO_TIMING_DRIVEN_COMPILE
- EDA_BOARD_BOUNDARY_SCAN_OPERATION
- EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL
- EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL
- EDA_BOARD_DESIGN_SYMBOL_TOOL
- EDA_BOARD_DESIGN_TIMING_TOOL
- EDA_BOARD_DESIGN_TOOL
- EDA_COPY_TO_SNAPSHOT
- EDA_DATA_FORMAT
- EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
- EDA_DESIGN_EXTRA_ALTERA_SIM_LIB
- EDA_DESIGN_INSTANCE_NAME
- EDA_ENABLE_GLITCH_FILTERING
- EDA_ENABLE_IPUTF_MODE
- EDA_ENABLE_OCV_TIMING_ANALYSIS
- EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE
- EDA_EXCALIBUR_SINGLE_SLICE
- EDA_EXTRA_ELAB_OPTION
- EDA_FLATTEN_BUSES
- EDA_FORMAL_VERIFICATION_ALLOW_RETIMING
- EDA_FORMAL_VERIFICATION_TOOL
- EDA_FV_HIERARCHY
- EDA_GENERATE_FUNCTIONAL_NETLIST
- EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT
- EDA_GENERATE_POWER_INPUT_FILE
- EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT
- EDA_GENERATE_SDF_FOR_POWER
- EDA_GENERATE_SDF_OUTPUT_FILE
- EDA_GENERATE_TIMING_CLOSURE_DATA
- EDA_IBIS_EXTENDED_MODEL_SELECTOR
- EDA_IBIS_MODEL_SELECTOR
- EDA_IBIS_MUTUAL_COUPLING
- EDA_IBIS_SPECIFICATION_VERSION
- EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION
- EDA_INPUT_DATA_FORMAT
- EDA_INPUT_GND
- EDA_INPUT_GND_NAME
- EDA_INPUT_VCC
- EDA_INPUT_VCC_NAME
- EDA_IPFS_FILE
- EDA_LAUNCH_CMD_LINE_TOOL
- EDA_LAUNCH_TOOL
- EDA_LMF_FILE
- EDA_MAINTAIN_DESIGN_HIERARCHY
- EDA_MAP_ILLEGAL_CHARACTERS
- EDA_MAP_ILLEGAL
- EDA_NATIVELINK_GENERATE_SCRIPT_ONLY
- EDA_NATIVELINK_PORTABLE_FILE_PATHS
- EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT
- EDA_NATIVELINK_SIMULATION_TEST_BENCH
- EDA_NETLIST_TYPE
- EDA_NETLIST_WRITER_OUTPUT_DIR
- EDA_OCV_CORE_DERATING_FACTOR
- EDA_OCV_IO_DERATING_FACTOR
- EDA_OUTPUT_DATA_FORMAT
- EDA_RESYNTHESIS_TOOL
- EDA_RTL_SIM_MODE
- EDA_RTL_SIMULATION_RUN_SCRIPT
- EDA_RTL_TEST_BENCH_FILE_NAME
- EDA_RTL_TEST_BENCH_NAME
- EDA_RTL_TEST_BENCH_RUN_FOR
- EDA_RUN_TOOL_AUTOMATICALLY
- EDA_SDC_FILE_NAME
- EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
- EDA_SHOW_LMF_MAPPING_MESSAGES
- EDA_SHOW_LMF_MAPPING_MSGS
- EDA_SIMULATION_RUN_SCRIPT
- EDA_SIMULATION_TOOL
- EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE
- EDA_SIMULATION_VCD_OUTPUT_TCL_FILE
- EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME
- EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
- EDA_TEST_BENCH_ENABLE_STATUS
- EDA_TEST_BENCH_ENTITY_MODULE_NAME
- EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB
- EDA_TEST_BENCH_FILE
- EDA_TEST_BENCH_FILE_NAME
- EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY
- EDA_TEST_BENCH_MODULE_NAME
- EDA_TEST_BENCH_NAME
- EDA_TEST_BENCH_RUN_FOR
- EDA_TEST_BENCH_RUN_SIM_FOR
- EDA_TEST_BENCH_SETTINGS
- EDA_TIME_SCALE
- EDA_TIMESCALE
- EDA_TIMING_ANALYSIS_TOOL
- EDA_TOOL_SETTINGS
- EDA_TRUNCATE_HPATH
- EDA_TRUNCATE_LONG_HIERARCHY_PATHS
- EDA_USE_IBIS_RLC_TYPE
- EDA_USE_LMF
- EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY
- EDA_USE_RISE_FALL_DELAYS
- EDA_VHDL_ARCH_NAME
- EDA_VHDL_LIBRARY
- EDA_WAIT_FOR_GUI_TOOL_COMPLETION
- EDA_WRITE_CONFIG
- EDA_WRITE_DEVICE_CONTROL_PORTS
- EDA_WRITE_NODES_FOR_POWER_ESTIMATION
- EDA_WRITER_DONT_WRITE_TOP_ENTITY
- EDIF_FILE
- ELA_FILE
- ELEMENT_INDEX
- ELF_FILE
- EMBEDDED_PROCESSOR
- EMIF_SOC_PHYCLK_ADVANCE_MODELING
- EMPTY
- EMPTY_PLACE_REGION
- EMU_REPLICATE_SIGNAL_PER_SECTOR
- ENABLE_ACCELERATED_INCREMENTAL_COMPILE
- ENABLE_ADVANCED_IO_DELAY_CHAIN_OPTIMIZATION
- ENABLE_ADV_SEU_DETECTION
- ENABLE_ALT2GXB_CONFIGURATION
- ENABLE_APEX_FITTER_CHOICE
- ENABLE_ASMI_FOR_FLASH_LOADER
- ENABLE_ASM_OPTIONS_FILE
- ENABLE_ATTEMPT_SIMILAR_PLACEMENT
- ENABLE_AUTONOMOUS_PCIE_HIP
- ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS
- ENABLE_BENEFICIAL_SKEW_OPTIMIZATION
- ENABLE_BOOT_SEL_PIN
- ENABLE_BUS_HOLD_CIRCUITRY
- ENABLE_BUS_HOLD
- ENABLE_CHIP_WIDE_OE
- ENABLE_CHIP_WIDE_RESET
- ENABLE_CLOCK_LATENCY
- ENABLE_COMPACT_REPORT_TABLE
- ENABLE_CONFIGURATION_PINS
- ENABLE_CORE_CLK
- ENABLE_CRC_ERROR_PIN
- ENABLE_CVPCIE_CONFDONE
- ENABLE_CVP_CONFDONE
- ENABLE_DA_RULE
- ENABLE_DEVICE_WIDE_OE
- ENABLE_DEVICE_WIDE_RESET
- ENABLE_DISABLED_STRATIX_LVDS_MODES
- ENABLED
- ENABLE_DRC
- ENABLE_DRC_SETTINGS
- ENABLE_ED_CRC_CHECK
- ENABLE_EXTRA_DQ_DELAY
- ENABLE_FALLBACK_TO_EXTERNAL_FLASH
- ENABLE_FORMAL_VERIFICATION
- ENABLE_HOLD_BACK_OFF
- ENABLE_HOLD_MULTICYCLE
- ENABLE_HPS_INTERNAL_TIMING
- ENABLE_INCREMENTAL_DESIGN
- ENABLE_INCREMENTAL_REUSE
- ENABLE_INCREMENTAL_SYNTHESIS
- ENABLE_INIT_DONE_OUTPUT
- ENABLE_INTERMEDIATE_SNAPSHOTS
- ENABLE_IP_DEBUG
- ENABLE_JTAG_BST_SUPPORT
- ENABLE_JTAG_PIN_SHARING
- ENABLE_LAB_SHARING_WITH_PARENT_PARTITION
- ENABLE
- ENABLE_LLIS
- ENABLE_LOGIC_ANALYZER_INTERFACE
- ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
- ENABLE_LOW_VOLT_MODE_FLEX10K
- ENABLE_LOW_VOLT_MODE_FLEX6K
- ENABLE_LOW_VOLT_MODE
- ENABLE_M512
- ENABLE_MERCURY_CDR
- ENABLE_MIXED_PORT_RDW_OLD_DATA_FOR_RAM_WITH_TWO_CLOCKS
- ENABLE_MULTICYCLE_HOLD
- ENABLE_MULTICYCLE
- ENABLE_MULTITAP
- ENABLE_NCEO_OUTPUT
- ENABLE_NCE_PIN
- ENABLE_NCONFIG_FROM_CORE
- ENABLE_NO_HIPI_INITIALIZATION_FLOW
- ENABLE_OCT_DONE
- ENABLE_OCTDONE
- ENABLE_PHYSICAL_DSP_MERGING
- ENABLE_PR_PINS
- ENABLE_PR_POF_ID
- ENABLE_RAPID_RECOMPILE
- ENABLE_RECOVERY_REMOVAL_ANALYSIS
- ENABLE_REDUCED_MEMORY_MODE
- ENABLE_SIGNALTAP
- ENABLE_SMART_VOLTAGE_ID
- ENABLE_SOURCE_MULTICYCLE_HOLD
- ENABLE_SOURCE_MULTICYCLE
- ENABLE_SPI_MODE_CHECK
- ENABLE_SRC_HOLD_MULTICYCLE
- ENABLE_SRC_MULTICYCLE
- ENABLE_STATE_MACHINE_INFERENCE
- ENABLE_STRATIX_II_DPA_DEBUG
- ENABLE_STRATIXII_DPA_DEBUG
- ENABLE_STRATIX_II_LVDS_LOOPBACK
- ENABLE_STRATIXII_LVDS_LOOPBACK
- ENABLE_STRICT_PRESERVATION
- ENABLE_SYNCH_INPUT_REGISTER_1S25
- ENABLE_TRI
- ENABLE_UNUSED_RX_CLOCK_WORKAROUND
- ENABLE_VREFA_PIN
- ENABLE_VREFB_PIN
- ENCRYPTED_LUTMASK
- ENCRYPT_PROGRAMMING_BITSTREAM
- END_TIME
- ENFORCE_CONFIGURATION_VCCIO
- EN_SPI_IO_WEAK_PULLUP
- ENTITY_REBINDING
- EN_USER_IO_WEAK_PULLUP
- EPC1
- EPC2
- EPROM_JTAG_CODE_APEX20K
- EPROM_JTAG_CODE_DALI
- EPROM_JTAG_CODE_FLEX10K
- EPROM_JTAG_CODE_FLEX6K
- EPROM_JTAG_CODE
- EPROM_JTAG_CODE_YEAGER
- EPROM_USE_CHECKSUM_AS_USERCODE
- EQ_BW_1
- EQ_BW_2
- EQ_BW_3
- EQ_BW_4
- EQC_AUTO_BREAK_CONE
- EQC_AUTO_COMP_LOOP_CUT
- EQC_AUTO_INVERSION
- EQC_AUTO_PORTSWAP
- EQC_AUTO_TERMINATE
- EQC_BBOX_MERGE
- EQC_CONSTANT_DFF_DETECTION
- EQC_DETECT_DONT_CARES
- EQC_DFF_SS_EMULATION
- EQC_DUPLICATE_DFF_DETECTION
- EQC_ENUM_AUTO_BREAK_CONE
- EQC_ENUM_AUTO_COMP_LOOP_CUT
- EQC_ENUM_AUTO_INVERSION
- EQC_ENUM_AUTO_PORTSWAP
- EQC_ENUM_AUTO_TERMINATE
- EQC_ENUM_BBOX_MERGE
- EQC_ENUM_CONSTANT_DFF_DETECTION
- EQC_ENUM_DETECT_DONT_CARES
- EQC_ENUM_DFF_SS_EMULATION
- EQC_ENUM_DUPLICATE_DFF_DETECTION
- EQC_ENUM_IO_BUFFER_CONVERSION
- EQC_ENUM_LVDS_MERGE
- EQC_ENUM_MAC_REGISTER_UNPACK
- EQC_ENUM_MANUAL_MAP_LIST
- EQC_ENUM_MAX_BDD_NODES
- EQC_ENUM_PARAMETER_CHECK
- EQC_ENUM_POWER_UP_COMPARE
- EQC_ENUM_RAM_REGISTER_UNPACK
- EQC_ENUM_RAM_UNMERGING
- EQC_ENUM_RENAMING_RULES
- EQC_ENUM_RENAMING_RULES_LIST
- EQC_ENUM_SET_PARTITION_BB_TO_VCC_GND
- EQC_ENUM_SHOW_ALL_MAPPED_POINTS
- EQC_ENUM_STRUCTURE_MATCHING
- EQC_ENUM_SUB_CONE_REPORT
- EQC_LVDS_MERGE
- EQC_MAC_REGISTER_UNPACK
- EQC_PARAMETER_CHECK
- EQC_POWER_UP_COMPARE
- EQC_RAM_REGISTER_UNPACK
- EQC_RAM_UNMERGING
- EQC_RENAMING_RULES
- EQC_RENAMING_RULES_LIST
- EQC_SET_PARTITION_BB_TO_VCC_GND
- EQC_SHOW_ALL_MAPPED_POINTS
- EQC_STRUCTURE_MATCHING
- EQC_SUB_CONE_REPORT
- EQUATION_FILE
- EQUIVALENCE_CHECKER_ASSIGNMENT
- EQZP_DIS_PEAKING
- EQZP_EN_PEAKING
- ERROR_CHECK_FREQUENCY_DIVISOR
- ESTIMATE_POWER_CONSUMPTION
- EXCALIBUR_ARM
- EXCALIBUR_CONFIGURATION_DEVICE
- EXCALIBUR_CONFIGURATION_SCHEME
- EXC_BUSTRANS_SIM_FILE
- EXCLUDE_FMAX_PATHS_GREATER_THAN
- EXCLUDE_SLACK_PATHS_GREATER_THAN
- EXCLUDE_TCO_PATHS_LESS_THAN
- EXCLUDE_TH_PATHS_LESS_THAN
- EXCLUDE_TPD_PATHS_LESS_THAN
- EXCLUDE_TSU_PATHS_LESS_THAN
- EXCLUSIVE_IO_GROUP
- EXI9
- EXPANDED
- EXPORT_BLOCK_NAME_OBFUSCATION
- EXPORT_PARTITION_SNAPSHOT_FINAL
- EXPORT_PARTITION_SNAPSHOT_SYNTHESIZED
- EXTENDS_TOP_BLOCK
- EXTERNAL_FEEDBACK
- EXTERNAL_FLASH_FALLBACK_ADDRESS
- EXTERNAL_INPUT_DELAY
- EXTERNAL
- EXTERNAL_LVDS_RX_USES_DPA
- EXTERNAL_OUTPUT_DELAY
- EXTERNAL_PIN_CONNECTION
- EXTERNAL_RESISTOR
- EXTRACT_AND_OPTIMIZE_BUS_MUXES
- EXTRACT_VERILOG_STATE_MACHINES
- EXTRACT_VHDL_STATE_MACHINES
- EXTRA_EFFORT
- EYEQ_BW_1G_TO_2P5G
- EYEQ_BW_2P5G_TO_7P5G
- EYEQ_BW_GREATER_THAN_7P5G
- EYEQ_BW_LESS_THAN_1G
- F10K_ACEX1K_PCI_LOW_CAP
- FALLBACK_TO_EXTERNAL_FLASH
- FALL
- FALSE
- FAMILY
- FANIN_PER_CELL_MAX7000
- FAP_NAME
- FAR_END
- FAR_GLOBAL_CLOCK
- FAR_REGIONAL_CLOCK
- FAST_FIT_COMPILATION
- FAST_FIT
- FAST_INPUT_REGISTER
- FAST_IO
- FAST
- FAST_OCT_REGISTER
- FAST_OPENCL_COMPILE
- FAST_OUTPUT_ENABLE_REGISTER
- FAST_OUTPUT_REGISTER
- FAST_PASSIVE_PARALLEL
- FAST_POR_DELAY
- FAST_PRESERVE
- FAST_REGIONAL_CLOCK
- FASTROW_INTERCONNECT
- FAST_VIO
- FBCLK_COUNTER_OUT
- FFFFFFFF
- FFFF
- FILES
- FILTER_PACKAGE
- FILTER_PIN_COUNT
- FILTER_SPEED_GRADE
- FILTER_VOLTAGE
- FINAL_PLACEMENT_OPTIMIZATION
- FIR_POST_1T_NEG
- FIR_POST_1T_POS
- FIR_POST_2T_NEG
- FIR_POST_2T_POS
- FIR_PRE_1T_NEG
- FIR_PRE_1T_POS
- FIR_PRE_2T_NEG
- FIR_PRE_2T_POS
- FIT_ATTEMPTS_TO_SKIP
- FIT_FAST_FORWARD
- FIT_FINALIZE
- FIT_INI_VARS
- FIT_ONLY_ONE_ATTEMPT
- FIT_PLACE
- FIT_PLAN
- FIT_ROUTE
- FIT_SCRIPT_FILE
- FIT_SEED
- FIT_SMART_IO
- FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND
- FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION
- FITTER_ASSIGNMENT
- FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN
- FITTER_EARLY_RETIMING
- FITTER_EARLY_TIMING_ESTIMATE_MODE
- FITTER_EFFORT
- FITTER_OPTIMIZED
- FITTER_PACK_AGGRESSIVE_ROUTABILITY
- FITTER_PLL_SCAN_CHAIN_RECONFIG_FILE
- FITTER_RESYNTHESIS
- FITTER_TCL_CALLBACK_FILE
- FITTER_TYPE
- FITTER_WILDARDS
- FITTER_WILDCARDS
- FIT_WYSIWYG_PIA
- FLASH_NCE_RESERVED
- FLASH_PROGRAMMING_FILE_NAME
- FLEX10KA
- FLEX10KB
- FLEX10K_CARRY_CHAIN_LENGTH
- FLEX10K_CLIQUE_TYPE
- FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE
- FLEX10K_CONFIGURATION_DEVICE
- FLEX10K_CONFIGURATION_SCHEME
- FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- FLEX10K_DEVICE_IO_STANDARD
- FLEX10KE
- FLEX10K_ENABLE_LOCK_OUTPUT
- FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
- FLEX10KE_PCI_LOW_CAP_ADJUST
- FLEX10K_JTAG_USER_CODE
- FLEX10K
- FLEX10K_MAX_PERIPHERAL_OE
- FLEX10K_OPTIMIZATION_TECHNIQUE
- FLEX10K_TECHNOLOGY_MAPPER
- FLEX6000
- FLEX6K_CARRY_CHAIN_LENGTH
- FLEX6K_CLIQUE_TYPE
- FLEX6K_CONFIG_DEVICE_JTAG_USER_CODE
- FLEX6K_CONFIGURATION_DEVICE
- FLEX6K_CONFIGURATION_SCHEME
- FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- FLEX6K_DEVICE_IO_STANDARD
- FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
- FLEX6K_JTAG_USER_CODE
- FLEX6K_LOCAL_ROUTING_DESTINATION
- FLEX6K_LOCAL_ROUTING_SOURCE
- FLEX6K_OPTIMIZATION_TECHNIQUE
- FLEX6K_TECHNOLOGY_MAPPER
- FLEX8000
- FLEXIBLE_TIMING
- FLOATING
- FLOATING_REGION
- FLOW_DISABLE_ASSEMBLER
- FLOW_ENABLE_DESIGN_ASSISTANT
- FLOW_ENABLE_EARLY_PLACE
- FLOW_ENABLE_HC_COMPARE
- FLOW_ENABLE_HCII_COMPARE
- FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD
- FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS
- FLOW_ENABLE_PARALLEL_MODULES
- FLOW_ENABLE_POWER_ANALYZER
- FLOW_ENABLE_RTL_VIEWER
- FLOW_ENABLE_TIMEQUEST_AFTER_EARLY_PLACE_STAGE
- FLOW_ENABLE_TIMEQUEST_AFTER_PLAN_STAGE
- FLOW_ENABLE_TIMING_ANALYZER_AFTER_EARLY_PLACE_STAGE
- FLOW_ENABLE_TIMING_ANALYZER_AFTER_PLAN_STAGE
- FLOW_ENABLE_TIMING_CONSTRAINT_CHECK
- FLOW_HARDCOPY_DESIGN_READINESS_CHECK
- FMAX_REQUIREMENT
- FOCUS_ENTITY_NAME
- FORCE_ALL_TILES_WITH_FAILING_TIMING_PATHS_TO_HIGH_SPEED
- FORCE_ALL_USED_TILES_TO_HIGH_SPEED
- FORCE_CONFIGURATION_VCCIO
- FORCED_IF_ASYNCHRONOUS
- FORCED
- FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS
- FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION
- FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER
- FORCE_HYPER_REGISTER_FOR_PERIPHERY_CORE_TRANSFER
- FORCE_HYPER_REGISTER_FOR_UIB_ESRAM_CORE_REGISTER
- FORCE_MERGE_PLL_FANOUTS
- FORCE_MERGE_PLL
- FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION
- FORCE_POINT_TO_POINT
- FORCE_RECOMPILE
- FORCE_SLACK
- FORCE_SSMCLK_TO_ISMCLK
- FORCE_SYNCH_CLEAR
- FORM_DDR_CLUSTERING_CLIQUE
- FPLL
- FPLL_VREG1_BOOST_1_STEP
- FPLL_VREG1_BOOST_2_STEP
- FPLL_VREG1_BOOST_3_STEP
- FPLL_VREG1_BOOST_4_STEP
- FPLL_VREG1_BOOST_5_STEP
- FPLL_VREG1_BOOST_6_STEP
- FPLL_VREG1_BOOST_7_STEP
- FPLL_VREG1_NO_VOLTAGE_BOOST
- FPLL_VREG_BOOST_1_STEP
- FPLL_VREG_BOOST_2_STEP
- FPLL_VREG_BOOST_3_STEP
- FPLL_VREG_BOOST_4_STEP
- FPLL_VREG_BOOST_5_STEP
- FPLL_VREG_BOOST_6_STEP
- FPLL_VREG_BOOST_7_STEP
- FPLL_VREG_NO_VOLTAGE_BOOST
- FRACTAL_SYNTHESIS
- FREQ_100MHZ
- FREQ_12_5MHZ
- FREQ_20MHZ
- FREQ_25MHZ
- FREQ_40MHZ
- FREQ_50MHZ
- FSDA_LEVEL_AUTO
- FSDA_LEVEL_C1
- FSDA_LEVEL_C2
- FSDA_LEVEL_U
- FSM_CAT
- FSM_RULE_DEADLOCK_STATE
- FSM_RULE_NO_RESET_STATE
- FSM_RULE_NO_SZER_ACLK_DOMAIN
- FSM_RULE_UNREACHABLE_STATE
- FSM_RULE_UNUSED_TRANSITION
- FSYN_AND_ICP_REGTEST_MODE
- FULL_BW
- FULL_COMPILATION
- FULL_INCREMENTAL_COMPILATION
- FULL_INCREMENTAL_DESIGN
- FULL
- FULL_VPACK
- FULL_VPR
- FUNCTIONAL
- FV_BLACKBOX
- GBE_1250
- GDF_FILE
- GEN3_OFF
- GEN3_ON
- GEN4_OFF
- GEN4_ON
- GENERAL_POOL
- GENERATE_CONFIG_HEXOUT_FILE
- GENERATE_CONFIG_ISC_FILE
- GENERATE_CONFIG_JAM_FILE
- GENERATE_CONFIG_JBC_FILE_COMPRESSED
- GENERATE_CONFIG_JBC_FILE
- GENERATE_CONFIG_SVF_FILE
- GENERATE_GXB_RECONFIG_MIF
- GENERATE_GXB_RECONFIG_MIF_WITH_PLL
- GENERATE_HEX_FILE
- GENERATE_ISC_FILE
- GENERATE_JAM_FILE
- GENERATE_JBC_FILE_COMPRESSED
- GENERATE_JBC_FILE
- GENERATE_PMSF_FILES
- GENERATE_PR_RBF_FILE
- GENERATE_RBF_FILE
- GENERATE_SVF_FILE
- GENERATE_TTF_FILE
- GENERATION_DIRECTORY
- GENERIC_TRAIT
- GIGE
- GIVE_ERROR
- GIVE_INFO
- GIVE_WARNING
- GLITCH_DETECTION
- GLITCH_DETECTION_PULSE
- GLITCH_INTERVAL
- GLOBAL_CLOCK
- GLOBAL
- GLOBAL_PLACEMENT_EFFORT
- GLOBAL_SIGNAL_CLKCTRL_LOCATION
- GLOBAL_SIGNAL
- GLOBAL_SKEW_BALANCED
- GNDIO_CURRENT_1PT8V
- GNDIO_CURRENT_2PT5V
- GNDIO_CURRENT_GTL
- GNDIO_CURRENT_GTL_PLUS
- GNDIO_CURRENT_LVCMOS
- GNDIO_CURRENT_LVTTL
- GNDIO_CURRENT_PCI
- GNDIO_CURRENT_SSTL2_CLASS1
- GNDIO_CURRENT_SSTL2_CLASS2
- GNDIO_CURRENT_SSTL3_CLASS1
- GNDIO_CURRENT_SSTL3_CLASS2
- GNU_ASM_COMMAND_LINE
- GNU_CPP_COMMAND_LINE
- GNU_CSP_ASM_COMMAND_LINE
- GNU_CSP_CPP_COMMAND_LINE
- GNU_CSP_LINK_COMMAND_LINE
- GNU_LINK_COMMAND_LINE
- GNUPRO_ARM_ASM_COMMAND_LINE
- GNUPRO_ARM_CPP_COMMAND_LINE
- GNUPRO_ARM_LINK_COMMAND_LINE
- GNUPRO_MIPS_ASM_COMMAND_LINE
- GNUPRO_MIPS_CPP_COMMAND_LINE
- GNUPRO_MIPS_LINK_COMMAND_LINE
- GNUPRO_NIOS_ASM_COMMAND_LINE
- GNUPRO_NIOS_CPP_COMMAND_LINE
- GNUPRO_NIOS_LINK_COMMAND_LINE
- GPH9
- GPLL_TO_LVDS_TX
- GPON_1244
- GPON_155
- GPON_2488
- GPON_622
- GRAY
- GROUNDED
- GROUP_COMB_LOGIC_IN_CLOUD
- GROUP_COMB_LOGIC_IN_CLOUD_TMV
- GROUP_NODES
- GROUP_NODES_TMV
- GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME
- GXB_0PPM_CLOCK_GROUP_DRIVER
- GXB_0PPM_CLOCK_GROUP
- GXB_0PPM_CORECLK
- GXB_0PPM_CORE_CLOCK
- GXB_CLOCK_GROUP_DRIVER
- GXB_CLOCK_GROUP
- GXB_IO_PIN_TERMINATION
- GXB_RECONFIG_GROUP
- GXB_RECONFIG_MIF
- GXB_RECONFIG_MIF_PLL
- GXB_REFCLK_COUPLING_TERMINATION_SETTING
- GXB_REFCLK_PIN_TERMINATION
- GXB_RESERVED_TRANSMIT_CHANNEL
- GXB_TX_PLL_RECONFIG_GROUP
- GXB_VCCA_VOLTAGE
- GXB_VCCR_VCCT_VOLTAGE
- H9K8
- HALF_BW
- HALF
- HALF_MEGALAB_COLUMN
- HALF_RESOLUTION
- HALF_ROW
- HARD_BLOCK_PARTITION
- HARDCOPY_DEVICE_IDENTIFIER
- HARDCOPY_EXTERNAL_CLOCK_JITTER
- HARDCOPY_FLOW_AUTOMATION
- HARDCOPYII_COMPANION_REVISION_NAME
- HARDCOPYII_POWER_ON_EXTRA_DELAY
- HARDCOPYII_RUN_COMPARISON_ON_EVERY_COMPILE
- HARDCOPYII_SAVE_MIGRATION_INFO_DURING_COMPILATION
- HARDCOPY_INDIVIDUAL_SETTINGS
- HARDCOPY_INPUT_TRANSITION_CLOCK_PIN
- HARDCOPY_INPUT_TRANSITION_DATA_PIN
- HARDCOPY_NEW_PROJECT_PATH
- HARD_POST_FIT
- HCII_OUTPUT_DIR
- HC_OUTPUT_DIR
- HCPY_ALOAD_SIGNALS
- HCPY_ASYN_RAM
- HCPY_CAT
- HCPY_EXCEED_RAM_USAGE
- HCPY_EXCEED_USER_IO_USAGE
- HCPY_EXT_CLK_JITTER_CHECK
- HCPY_EXT_CLK_JITTER_EDGE
- HCPY_EXT_CLK_JITTER
- HCPY_ILLEGAL_HC_DEV_PKG
- HCPY_INPUT_TRANS_CLK_PIN
- HCPY_INPUT_TRANS_DATA_PIN
- HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES
- HCPY_TRANS_CONDITION_CLK_PIN
- HCPY_TRANS_CONDITION_DATA_PIN
- HCPY_TRANS_EDGE_CLK_PIN
- HCPY_TRANS_EDGE_DATA_PIN
- HCPY_VREF_PINS
- HDL_INITIAL_FANOUT_LIMIT
- HDL_INTERFACE_INSTANCE_ENTITY
- HDL_INTERFACE_INSTANCE_NAME
- HDL_INTERFACE_INSTANCE_PARAMETERS
- HDL_INTERFACE_OUTPUT_PATH
- HDL_MESSAGE_LEVEL
- HDL_MESSAGE_OFF
- HDL_MESSAGE_ON
- HDL_SETTINGS
- HDL_VERSION
- HEIGHT
- HEX_FILE_COUNT_UP_DOWN
- HEX_FILE_COUNT_UP_OR_DOWN
- HEX_FILE
- HEX_FILE_START_ADDRESS
- HEXOUT_FILE_COUNT_DIRECTION
- HEXOUT_FILE
- HEXOUT_FILE_START_ADDRESS
- HEX_OUTPUT_FILE
- HIDE_RCF_WARNINGS
- HIERARCHICAL_COMPILE
- HIERARCHICAL_PRPOF_ID_CHECK
- HIERARCHY_BLACKBOX_FILE
- HIGH_EFFORT
- HIGH_EFFORT_ROUTE_INI
- HIGH
- HIGH_PACKING_ROUTABILITY_EFFORT
- HIGH_PERF
- HIGH_PERFORMANCE_EFFORT
- HIGH_PERFORMANCE_EFFORT_WITH_MAXIMUM_PLACEMENT_EFFORT
- HIGH_PLACEMENT_ROUTABILITY_EFFORT
- HIGH_POWER_EFFORT
- HIGH_ROUTABILITY_EFFORT
- HIGH_VCM
- HIGIG_4062
- HIGIG_5000
- HIGIG_6250
- HIGIG_6562
- HOLD_MULTICYCLE_DEFAULT
- HOLD_MULTICYCLE
- HOLD_RELATIONSHIP
- HPS_AUTO_PARTITION
- HPS_COLD_RESET_PIN_MODE
- HPS_DAP_SPLIT_MODE
- HPS_EARLY_IO_RELEASE
- HPS_FIRST
- HPS_INITIALIZATION
- HPS_IO
- HPS_ISW_DATA
- HPS_ISW_EMIF
- HPS_ISW_FILE
- HPS_LOCATION
- HPS_PARTITION
- HPS_PINS
- HPS_WARM_RESET_PIN_MODE
- HSSI_A10_CDR_PLL_ANALOG_MODE
- HSSI_A10_CDR_PLL_POWER_MODE
- HSSI_A10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
- HSSI_A10_CDR_PLL_UC_RO_CAL
- HSSI_A10_CMU_FPLL_ANALOG_MODE
- HSSI_A10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
- HSSI_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
- HSSI_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
- HSSI_A10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
- HSSI_A10_CMU_FPLL_POWER_MODE
- HSSI_A10_LC_PLL_ANALOG_MODE
- HSSI_A10_LC_PLL_POWER_MODE
- HSSI_A10_PM_UC_CLKDIV_SEL
- HSSI_A10_PM_UC_CLKSEL_CORE
- HSSI_A10_PM_UC_CLKSEL_OSC
- HSSI_A10_REFCLK_TERM_TRISTATE
- HSSI_A10_RX_ADAPT_DFE_CONTROL_SEL
- HSSI_A10_RX_ADAPT_DFE_SEL
- HSSI_A10_RX_ADAPT_VGA_SEL
- HSSI_A10_RX_ADAPT_VREF_SEL
- HSSI_A10_RX_ADP_CTLE_ACGAIN_4S
- HSSI_A10_RX_ADP_CTLE_EQZ_1S_SEL
- HSSI_A10_RX_ADP_DFE_FLTAP_POSITION
- HSSI_A10_RX_ADP_DFE_FXTAP10
- HSSI_A10_RX_ADP_DFE_FXTAP10_SGN
- HSSI_A10_RX_ADP_DFE_FXTAP11
- HSSI_A10_RX_ADP_DFE_FXTAP11_SGN
- HSSI_A10_RX_ADP_DFE_FXTAP1
- HSSI_A10_RX_ADP_DFE_FXTAP2
- HSSI_A10_RX_ADP_DFE_FXTAP2_SGN
- HSSI_A10_RX_ADP_DFE_FXTAP3
- HSSI_A10_RX_ADP_DFE_FXTAP3_SGN
- HSSI_A10_RX_ADP_DFE_FXTAP4
- HSSI_A10_RX_ADP_DFE_FXTAP4_SGN
- HSSI_A10_RX_ADP_DFE_FXTAP5
- HSSI_A10_RX_ADP_DFE_FXTAP5_SGN
- HSSI_A10_RX_ADP_DFE_FXTAP6
- HSSI_A10_RX_ADP_DFE_FXTAP6_SGN
- HSSI_A10_RX_ADP_DFE_FXTAP7
- HSSI_A10_RX_ADP_DFE_FXTAP7_SGN
- HSSI_A10_RX_ADP_DFE_FXTAP8
- HSSI_A10_RX_ADP_DFE_FXTAP8_SGN
- HSSI_A10_RX_ADP_DFE_FXTAP9
- HSSI_A10_RX_ADP_DFE_FXTAP9_SGN
- HSSI_A10_RX_ADP_LFEQ_FB_SEL
- HSSI_A10_RX_ADP_ONETIME_DFE
- HSSI_A10_RX_ADP_VGA_SEL
- HSSI_A10_RX_ADP_VREF_SEL
- HSSI_A10_RX_BYPASS_EQZ_STAGES_234
- HSSI_A10_RX_EQ_BW_SEL
- HSSI_A10_RX_EQ_DC_GAIN_TRIM
- HSSI_A10_RX_INPUT_VCM_SEL
- HSSI_A10_RX_LINK
- HSSI_A10_RX_OFFSET_CANCELLATION_CTRL
- HSSI_A10_RX_ONE_STAGE_ENABLE
- HSSI_A10_RX_POWER_MODE
- HSSI_A10_RX_QPI_ENABLE
- HSSI_A10_RX_RX_SEL_BIAS_SOURCE
- HSSI_A10_RX_SD_OUTPUT_OFF
- HSSI_A10_RX_SD_OUTPUT_ON
- HSSI_A10_RX_SD_THRESHOLD
- HSSI_A10_RX_TERM_SEL
- HSSI_A10_RX_TERM_TRI_ENABLE
- HSSI_A10_RX_UC_RX_DFE_CAL
- HSSI_A10_RX_VCCELA_SUPPLY_VOLTAGE
- HSSI_A10_RX_VCM_CURRENT_ADD
- HSSI_A10_RX_VCM_SEL
- HSSI_A10_RX_XRX_PATH_ANALOG_MODE
- HSSI_A10_TX_COMPENSATION_EN
- HSSI_A10_TX_DCD_DETECTION_EN
- HSSI_A10_TX_DPRIO_CGB_VREG_BOOST
- HSSI_A10_TX_LINK
- HSSI_A10_TX_LOW_POWER_EN
- HSSI_A10_TX_POWER_MODE
- HSSI_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
- HSSI_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
- HSSI_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
- HSSI_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
- HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
- HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
- HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
- HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
- HSSI_A10_TX_RES_CAL_LOCAL
- HSSI_A10_TX_RX_DET
- HSSI_A10_TX_RX_DET_OUTPUT_SEL
- HSSI_A10_TX_RX_DET_PDB
- HSSI_A10_TX_SLEW_RATE_CTRL
- HSSI_A10_TX_TERM_CODE
- HSSI_A10_TX_TERM_SEL
- HSSI_A10_TX_UC_DCD_CAL
- HSSI_A10_TX_UC_GEN3
- HSSI_A10_TX_UC_GEN4
- HSSI_A10_TX_UC_SKEW_CAL
- HSSI_A10_TX_UC_TXVOD_CAL_CONT
- HSSI_A10_TX_UC_TXVOD_CAL
- HSSI_A10_TX_UC_VCC_SETTING
- HSSI_A10_TX_USER_FIR_COEFF_CTRL_SEL
- HSSI_A10_TX_VOD_OUTPUT_SWING_CTRL
- HSSI_A10_TX_XTX_PATH_ANALOG_MODE
- HSSI_ADCE_RGEN_MODE
- HSSI_ANALOG_SETTINGS_PROTOCOL
- HSSI_C10_CDR_PLL_ANALOG_MODE
- HSSI_C10_CDR_PLL_POWER_MODE
- HSSI_C10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
- HSSI_C10_CDR_PLL_UC_RO_CAL
- HSSI_C10_CMU_FPLL_ANALOG_MODE
- HSSI_C10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
- HSSI_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
- HSSI_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
- HSSI_C10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
- HSSI_C10_CMU_FPLL_POWER_MODE
- HSSI_C10_LC_PLL_ANALOG_MODE
- HSSI_C10_LC_PLL_POWER_MODE
- HSSI_C10_PM_UC_CLKDIV_SEL
- HSSI_C10_PM_UC_CLKSEL_CORE
- HSSI_C10_PM_UC_CLKSEL_OSC
- HSSI_C10_REFCLK_TERM_TRISTATE
- HSSI_C10_RX_ADAPT_DFE_CONTROL_SEL
- HSSI_C10_RX_ADAPT_DFE_SEL
- HSSI_C10_RX_ADAPT_VGA_SEL
- HSSI_C10_RX_ADAPT_VREF_SEL
- HSSI_C10_RX_ADP_CTLE_ACGAIN_4S
- HSSI_C10_RX_ADP_CTLE_EQZ_1S_SEL
- HSSI_C10_RX_ADP_DFE_FLTAP_POSITION
- HSSI_C10_RX_ADP_DFE_FXTAP10
- HSSI_C10_RX_ADP_DFE_FXTAP10_SGN
- HSSI_C10_RX_ADP_DFE_FXTAP11
- HSSI_C10_RX_ADP_DFE_FXTAP11_SGN
- HSSI_C10_RX_ADP_DFE_FXTAP1
- HSSI_C10_RX_ADP_DFE_FXTAP2
- HSSI_C10_RX_ADP_DFE_FXTAP2_SGN
- HSSI_C10_RX_ADP_DFE_FXTAP3
- HSSI_C10_RX_ADP_DFE_FXTAP3_SGN
- HSSI_C10_RX_ADP_DFE_FXTAP4
- HSSI_C10_RX_ADP_DFE_FXTAP4_SGN
- HSSI_C10_RX_ADP_DFE_FXTAP5
- HSSI_C10_RX_ADP_DFE_FXTAP5_SGN
- HSSI_C10_RX_ADP_DFE_FXTAP6
- HSSI_C10_RX_ADP_DFE_FXTAP6_SGN
- HSSI_C10_RX_ADP_DFE_FXTAP7
- HSSI_C10_RX_ADP_DFE_FXTAP7_SGN
- HSSI_C10_RX_ADP_DFE_FXTAP8
- HSSI_C10_RX_ADP_DFE_FXTAP8_SGN
- HSSI_C10_RX_ADP_DFE_FXTAP9
- HSSI_C10_RX_ADP_DFE_FXTAP9_SGN
- HSSI_C10_RX_ADP_LFEQ_FB_SEL
- HSSI_C10_RX_ADP_ONETIME_DFE
- HSSI_C10_RX_ADP_VGA_SEL
- HSSI_C10_RX_ADP_VREF_SEL
- HSSI_C10_RX_BYPASS_EQZ_STAGES_234
- HSSI_C10_RX_EQ_BW_SEL
- HSSI_C10_RX_EQ_DC_GAIN_TRIM
- HSSI_C10_RX_INPUT_VCM_SEL
- HSSI_C10_RX_LINK
- HSSI_C10_RX_OFFSET_CANCELLATION_CTRL
- HSSI_C10_RX_ONE_STAGE_ENABLE
- HSSI_C10_RX_POWER_MODE
- HSSI_C10_RX_QPI_ENABLE
- HSSI_C10_RX_RX_SEL_BIAS_SOURCE
- HSSI_C10_RX_SD_OUTPUT_OFF
- HSSI_C10_RX_SD_OUTPUT_ON
- HSSI_C10_RX_SD_THRESHOLD
- HSSI_C10_RX_TERM_SEL
- HSSI_C10_RX_TERM_TRI_ENABLE
- HSSI_C10_RX_UC_RX_DFE_CAL
- HSSI_C10_RX_VCCELA_SUPPLY_VOLTAGE
- HSSI_C10_RX_VCM_CURRENT_ADD
- HSSI_C10_RX_VCM_SEL
- HSSI_C10_RX_XRX_PATH_ANALOG_MODE
- HSSI_C10_TX_COMPENSATION_EN
- HSSI_C10_TX_DCD_DETECTION_EN
- HSSI_C10_TX_DPRIO_CGB_VREG_BOOST
- HSSI_C10_TX_LINK
- HSSI_C10_TX_LOW_POWER_EN
- HSSI_C10_TX_POWER_MODE
- HSSI_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP
- HSSI_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP
- HSSI_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T
- HSSI_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T
- HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
- HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
- HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
- HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
- HSSI_C10_TX_RES_CAL_LOCAL
- HSSI_C10_TX_RX_DET
- HSSI_C10_TX_RX_DET_OUTPUT_SEL
- HSSI_C10_TX_RX_DET_PDB
- HSSI_C10_TX_SLEW_RATE_CTRL
- HSSI_C10_TX_TERM_CODE
- HSSI_C10_TX_TERM_SEL
- HSSI_C10_TX_UC_DCD_CAL
- HSSI_C10_TX_UC_GEN3
- HSSI_C10_TX_UC_GEN4
- HSSI_C10_TX_UC_SKEW_CAL
- HSSI_C10_TX_UC_TXVOD_CAL_CONT
- HSSI_C10_TX_UC_TXVOD_CAL
- HSSI_C10_TX_UC_VCC_SETTING
- HSSI_C10_TX_USER_FIR_COEFF_CTRL_SEL
- HSSI_C10_TX_VOD_OUTPUT_SWING_CTRL
- HSSI_C10_TX_XTX_PATH_ANALOG_MODE
- HSSI_CLOCK_TOPOLOGY
- HSSI_FAST_LOCK_MODE
- HSSI_GT_FORCE_VCO_CONST
- HSSI_GT_RX_CTLE
- HSSI_GT_RX_RX_DC_GAIN
- HSSI_GT_RX_VCM_SEL
- HSSI_GT_TERMINATION
- HSSI_GT_TX_COMMON_MODE_DRIVER_SEL
- HSSI_GT_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
- HSSI_GT_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP
- HSSI_GT_TX_SIG_INV_PRE_TAP
- HSSI_GT_TX_VOD_SWITCHING_CTRL_MAIN_TAP
- HSSI_ODI_EYE_MONITOR_BW_SEL
- HSSI_PARAMETER
- HSSI_REFCLK_TERMINATION
- HSSI_RX_ACGAIN_A
- HSSI_RX_ACGAIN_V
- HSSI_RX_ADCE_HSF_HFBW
- HSSI_RX_ADCE_RGEN_BW
- HSSI_RX_BYPASS_EQZ_STAGES_234
- HSSI_RX_CT_EQUALIZER_SETTING
- HSSI_RX_DFE_PI_BW
- HSSI_RX_ENABLE_RX_GAINCTRL_PCIEMODE
- HSSI_RX_EQ_BW_SEL
- HSSI_RX_INPUT_VCM_SEL
- HSSI_RX_PDB_SD
- HSSI_RX_PMOS_GAIN_PEAK
- HSSI_RX_QPI_ENABLE
- HSSI_RX_RX_DC_GAIN
- HSSI_RX_RX_SEL_BIAS_SOURCE
- HSSI_RX_SD_OFF
- HSSI_RX_SD_ON
- HSSI_RX_SD_THRESHOLD
- HSSI_RX_SEL_HALF_BW
- HSSI_RX_VCCELA_SUPPLY_VOLTAGE
- HSSI_RX_VCM_CURRENT_ADD
- HSSI_RX_VCM_SEL
- HSSI_S10_REFCLK_TERM_TRISTATE
- HSSI_TERMINATION
- HSSI_TX_COMMON_MODE_DRIVER_SEL
- HSSI_TX_DRIVER_RESOLUTION_CTRL
- HSSI_TX_FIR_COEFF_CTRL_SEL
- HSSI_TX_LOCAL_IB_CTL
- HSSI_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
- HSSI_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
- HSSI_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP_USER
- HSSI_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP
- HSSI_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_USER
- HSSI_TX_QPI_EN
- HSSI_TX_RX_DET
- HSSI_TX_RX_DET_OUTPUT_SEL
- HSSI_TX_RX_DET_PDB
- HSSI_TX_SIG_INV_2ND_TAP
- HSSI_TX_SIG_INV_PRE_TAP
- HSSI_TX_SLEW_RATE_CTRL
- HSSI_TX_SWING_BOOST
- HSSI_TX_VCM_CTRL_SEL
- HSSI_TX_VCM_CURRENT_ADDL
- HSSI_TX_VOD_BOOST
- HSSI_TX_VOD_SWITCHING_CTRL_MAIN_TAP
- HSSI_VCCEH_VOLTAGE
- HSSI_VCCER_VCCET_VOLTAGE
- HTML_FILE
- HTML_REPORT_FILE
- HUB_AUTO_INSERT
- HUB_ENTITY_NAME
- HUB_INSTANCE_NAME
- HUB_SOURCE_FILE
- HYBRID_FLOW_NEW_EXTRACTOR
- HYBRID
- HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS
- HYPER_AWARE_OPTIMIZE_SHORT_PATHS
- HYPER_AWARE_OPTIMIZE_TIMING
- HYPER_AWARE_REGISTER_PLACEMENT
- HYPER_AWARE_SET_REGISTER_BYPASS
- HYPER_AWARE_SET_REGISTER_INITIAL_STATE
- HYPER_EARLY_RETIMER
- HYPER_REGISTER_DELAY_CHAIN
- HYPER_REGISTER
- HYPER_RETIMER_ADD_PIPELINING_GROUP
- HYPER_RETIMER_ADD_PIPELINING
- HYPER_RETIMER_ENABLE_ADD_PIPELINING
- HYPER_RETIMER_FALSE_PATH_RESTRICTION
- HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING
- HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX
- HYPER_RETIMER_FAST_FORWARD_AGGRESSIVE_EXPLORATION
- HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR
- HYPER_RETIMER_FAST_FORWARD_CUT_ALL_CLOCK_TRANSFERS
- HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS
- HYPER_RETIMER_FAST_FORWARD_EMULATE_ADD_PIPELINING
- HYPER_RETIMER_FAST_FORWARD_EMULATE_AGGRESSIVE_EXPLORATION
- HYPER_RETIMER_FAST_FORWARD_EMULATE_ASYNCH_CLEAR
- HYPER_RETIMER_FAST_FORWARD_EMULATE_USER_PRESERVE_RESTRICTION
- HYPER_RETIMER_FAST_FORWARD
- HYPER_RETIMER_FAST_FORWARD_OFF_DESCRIPTION
- HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS
- HYPER_RETIMER_FAST_FORWARD_TARGET_MAX_PERFORMANCE
- HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION
- HYPER_RETIMER
- HYPER_RETIMER_REGISTERS_REMOVED
- IB_22OHM
- IB_29OHM
- IB_42OHM
- IB_49OHM
- IEEE_10G_BASE_CR_10312
- IEEE_10G_KR_10312
- IEEE_40G_BASE_KR_10312
- IGNORE_CARRY_BUFFERS
- IGNORE_CARRY
- IGNORE_CASCADE_BUFFERS
- IGNORE_CASCADE
- IGNORE_CLOCK_SETTINGS
- IGNORE_DUPLICATE_DESIGN_ENTITY
- IGNORE_GLOBAL_BUFFERS
- IGNORE_GLOBAL
- IGNORE_HSSI_COLUMN_POWER_FOR_BTI_MITIGATION
- IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS
- IGNORE_LCELL_BUFFERS
- IGNORE_LCELL
- IGNORE_LCELL_MAX7000
- IGNORE_MAX_FANOUT_ASSIGNMENTS
- IGNORE_MODE_FOR_MERGE
- IGNORE_PARTITIONS
- IGNORE_ROW_GLOBAL_BUFFERS
- IGNORE_ROW_GLOBAL
- IGNORE_SOFT_BUFFERS
- IGNORE_SOFT
- IGNORE_SOFT_MAX7000
- IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
- IGNORE_TRANSLATE_OFF
- IGNORE_VERILOG_INITIAL_CONSTRUCTS
- IGNORE_VREF_RESTRICTION
- IMMEDIATE_ASSERTION_FAIL_ACTION
- IMMEDIATE_ASSERTION_FAIL_MESSAGE
- IMMEDIATE_ASSERTION
- IMMEDIATE_ASSERTION_PASS_MESSAGE
- IMMEDIATE_ASSERTION_STATE
- IMMEDIATE_ASSERTION_TEST_CONDITION
- IMPLEMENT_AS_CLOCK_ENABLE
- IMPLEMENT_AS_LCELL
- IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL
- IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE
- IMPLEMENTS_FREE_RUNNING_CLOCK
- IMPORT_BASED_POST_FIT
- IMPORT_BLOCK
- IMPORTED
- IMPORT
- INCLUDED_IN_OLD_CHIP_SECTION
- INCLUDED_IN_OLD_PROJECT_INFO_SECTION
- INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
- INCLUDE_FILE
- INCLUDE_IN_ALL_TB2
- INCLUDE_IN_COMPILER_REPORT
- INCLUDE_IN_FITTER_TB2
- INCLUDE_IN_POWER_TB2
- INCLUDE_IN_SIMULATOR_REPORT
- INCLUDE_IN_SYNTHESIS_REPORT
- INCLUDE_IN_SYNTHESIS_TB2
- INCLUDE_IN_TIMING_TB2
- INCLUDE_PATHS_GREATER_THAN_TCO
- INCLUDE_PATHS_GREATER_THAN_TH
- INCLUDE_PATHS_GREATER_THAN_TPD
- INCLUDE_PATHS_GREATER_THAN_TSU
- INCLUDE_PATHS_LESS_THAN_FMAX
- INCLUDE_PATHS_LESS_THAN_SLACK
- INCLUDE_PIN_DELAYS_IN_CALCULATIONS
- INC_PLACE_PREF_LOCATION
- INC_PLC_MODE
- INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN
- INCREASE_DELAY_TO_OUTPUT_PIN
- INCREASE_INPUT_CLOCK_ENABLE_DELAY
- INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER
- INCREASE_OUTPUT_CLOCK_ENABLE_DELAY
- INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY
- INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAYR
- INCREASE_TZX_DELAY_TO_OUTPUT_PIN
- INCREMENTAL_COMPILATION_EXPORT_FILE
- INCREMENTAL_COMPILATION_EXPORT_FLATTEN
- INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE
- INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME
- INCREMENTAL_COMPILATION_EXPORT_POST_FIT
- INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH
- INCREMENTAL_COMPILATION_EXPORT_ROUTING
- INCREMENTAL_COMPILATION
- INCREMENTAL_INPUT_VECTOR_FILE
- INCREMENTAL_SYNTHESIS_FULL
- INCREMENTAL_SYNTHESIS
- INCREMENTAL_SYNTHESIS_PARTITION
- INCREMENTAL_SYNTHESIS_TOP
- INCREMENTAL_TIME_INPUT
- INCREMENTAL_VECTOR_INPUT_SOURCE
- INCR_SIGNALTAP_PARTITION
- INCR_TAP
- INDIRECT_PORT_ASSIGNMENT
- INERTIAL
- INFER_RAMS_FROM_RAW_LOGIC
- INIT_CLKUSR
- INIT_DCLK
- INIT_DONE_OPEN_DRAIN
- INIT_DONE_OUTPUT
- INITIALIZATION_CLOCK
- INITIAL_PLACEMENT_CONFIGURATION
- INIT_INTOSC
- INI_VARS
- INNER_NUM
- INPUT_DELAY_CHAIN
- INPUT_DELAY
- INPUT_EDGE
- INPUT
- INPUT_MAX_DELAY
- INPUT_MIN_DELAY
- INPUT_OCT_VALUE
- INPUT_ONLY
- INPUT_PERSONA
- INPUT_REFERENCE
- INPUT_REGISTER
- INPUT_TERMINATION
- INPUT_TRANSITION_TIME
- INSERT_ADDITIONAL_LOGIC_CELL
- INSERT_BOUNDARY_WIRE_LUTS
- INSTANT_ON
- INTERFACE
- INTERFACE_ROLE
- INTERFACES
- INTERFACE_TYPE
- INTERLAKEN_11100
- INTERLAKEN_12500
- INTERLAKEN_3125
- INTERLAKEN_6375
- INTERLAKEN
- INTERNAL_CONFIGURATION
- INTERNAL_FLASH_UPDATE_MODE
- INTERNAL
- INTERNAL_OSCILLATOR_DIVIDE_DOWN
- INTERNAL_SCRUBBING
- INTERNAL_VREF_MODE
- INVALID_DESIGN_SOURCE
- INVERT_BASE_CLOCK
- INVERTED_CLOCK
- IO_12_LANE_INPUT_DATA_DELAY_CHAIN
- IO_12_LANE_INPUT_DATA_DELAY
- IO_12_LANE_INPUT_STROBE_DELAY_CHAIN
- IO_12_LANE_INPUT_STROBE_DELAY
- IOBANK
- IOBANK_VCCIO
- IO_MAXIMUM_TOGGLE_RATE
- IO_PARTITION_PLACEMENT
- IO_PATHS_AND_MINIMUM_TPD_PATHS
- IO_PLACEMENT_OPTIMIZATION
- IOPLL
- IO_SSO_CHECKING
- IO_STANDARD
- IP_ADVISOR_FILE
- IPA_FILE
- IP_COMPONENT_AUTHOR
- IP_COMPONENT_DESCRIPTION
- IP_COMPONENT_DISPLAY_NAME
- IP_COMPONENT_DOCUMENTATION_LINK
- IP_COMPONENT_GROUP
- IP_COMPONENT_INTERNAL
- IP_COMPONENT_NAME
- IP_COMPONENT_PARAMETER
- IP_COMPONENT_REPORT_HIERARCHY
- IP_COMPONENT_SETTING
- IP_COMPONENT_VERSION
- IP_DEBUG_VISIBLE
- IP_FILE
- IP_GENERATED_DEVICE_FAMILY
- IP_QSYS_MODE
- IP_SEARCH_PATHS
- IP_SHOW_ANALYSIS_MESSAGES
- IP_SHOW_ELABORATION_MESSAGES
- IP_TARGETED_DEVICE_FAMILY
- IP_TARGETED_PART_TRAIT
- IP_TOOL_ENV
- IP_TOOL_HIERARCHY_LEVELS
- IP_TOOL_NAME
- IP_TOOL_VENDOR_NAME
- IP_TOOL_VERSION_CREATED
- IP_TOOL_VERSION
- IP_TOP_LEVEL_COMPONENT_NAME
- IP_TOP_LEVEL_ENTITY_NAME
- IPX_FILE
- ISC_FILE
- IS_DEBUG
- IS_FREEFORM
- ISL82XX
- ISP_CLAMP_STATE_DEFAULT
- ISP_CLAMP_STATE
- JAM_FILE
- JBC_FILE
- JESD204_A_B_12500
- JESD204_A_B_6375
- JOHNSON
- JTAG_BST_SUPPORT
- JTAG_BST_SUPPORT_MAX7000
- JTAG_PIN_SHARING
- JTAG_USER_CODE_DALI
- JTAG_USER_CODE_FLEX6K
- JTAG_USER_CODE
- K0H9
- KEEP_LCELL_FOLLOWING_PLL
- KEEP_LUT_SYN_ONLY
- KXL9
- LARGE
- LARGE_PERIPHERY_CLOCK
- LAST_QUARTUS_VERSION
- LATE_CLOCK_LATENCY
- LCELL_AS_VIO
- LCELL_INSERTION
- LCELL_PERIPHERY_ROUTER
- LEVEL1
- LEVEL2
- LEVEL3
- LIBRARY
- LIBRARY_SEARCH_ORDER
- LICENSE_FILE
- LIMIT_AHDL_INTEGERS_TO_32_BITS
- LINEAR_FORMAT
- LL_AUTO_SIZE
- LL_COLOR
- LL_CORE_ONLY
- LL_ENABLED
- LL_EXCLUDE
- LL_FSDA_LEVEL
- LL_FSDA_ROUTING_INTERFACE
- LL_HEIGHT
- LL_HORIZONTAL_FLIP
- LL_IGNORE_IO_BANK_FSDA_CONSTRAINT
- LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT
- LL_IGNORE_IO_PIN_FSDA_CONSTRAINT
- LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT
- LL_IMPORT_FILE
- LL_MEMBER_EXCEPTIONS
- LL_MEMBER_OF_FSDA_ROUTING_INTERFACE
- LL_MEMBER_OF
- LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE
- LL_MEMBER_OPTION
- LL_MEMBER_RESOURCE_EXCLUDE
- LL_MEMBER_STATE
- LL_NODE_LOCATION
- LL_OLD_BEHAVIOR
- LL_ORIGIN
- LL_OUTPUT_SIGNAL_FSDA_LEVEL
- LL_PARENT
- LL_PATH_EXCLUDE
- LL_PATH_INCLUDE
- LL_PRIORITY
- LL_PR_REGION
- LL_RCF_IMPORT_FILE
- LL_RECT
- LL_REGION_SECURITY_LEVEL
- LL_RESERVED_IS_LIMITED
- LL_RESERVED
- LL_RESERVED_MEMBERS_OF_IMMEDIATE_PARENT_REGION_HIERARCHY_ONLY
- LL_RESERVE
- LL_ROOT_REGION
- LL_ROUGH
- LL_ROUTING_REGION_EXPANSION_SIZE
- LL_ROUTING_REGION
- LL_SECURITY_ROUTING_INTERFACE
- LL_SIGNAL_SECURITY_LEVEL
- LL_SOFT
- LL_SOURCE_PARTITION_HIERARCHY
- LL_SOURCE_PARTITION
- LL_SOURCE_REGION
- LL_STATE
- LL_WIDTH
- LMF_FILE
- LOCAL
- LOCAL_LINE_DELAY_CHAIN
- LOCATION
- LOCATION_PIN_ASSIGNMENT
- LOCKED
- LOGIC_ANALYZER_INTERFACE_FILE
- LOGIC_ELEMENTS
- LOGIC
- LOGICLOCK_ASSIGNMENT
- LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT
- LOGICLOCK_INCREMENTAL_COMPILE_FILE
- LOGICLOCK_REGION
- LOGIC_MINIMIZATION_SCRIPT
- LOW_CAP_ADJUST_FLEX10KE
- LOW_POWER
- LOW_VCM
- LTM4677
- LUTRAM_INSTANCES_FOR_ASIC_PROTOTYPING
- LVDS_CLOCK_DATA_DESKEW_ADJUST
- LVDS_DESKEW
- LVDS_DIRECT_LOOPBACK_MODE
- LVDS_FIXED_CLOCK_DATA_PHASE
- LVDS
- LVDS_RX_REGISTER
- M10K
- M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
- M144K
- M144K_USE_DCD
- M20K
- M512
- MACRO_HEAD
- MACRO_MEMBER
- MACRO_TIMING
- MAP_FILE
- MAPPER_SYNTHESIS_ASSIGNMENT
- MASK
- MASK_REVISION
- MATCH_PLL_COMPENSATION_CLOCK
- MAX10FPGA_CONFIGURATION_SCHEME
- MAX3000A
- MAX7000AE
- MAX7000A
- MAX7000B
- MAX7000B_VCCIO_IOBANK1
- MAX7000B_VCCIO_IOBANK2
- MAX7000_DEVICE_IO_STANDARD
- MAX7000_ENABLE_JTAG_BST_SUPPORT
- MAX7000_FANIN_PER_CELL
- MAX7000_IGNORE_LCELL_BUFFERS
- MAX7000_IGNORE_SOFT_BUFFERS
- MAX7000_INDIVIDUAL_TURBO_BIT
- MAX7000_JTAG_USER_CODE
- MAX7000_OPTIMIZATION_TECHNIQUE
- MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH
- MAX7000S_JTAG_USER_CODE
- MAX7000S
- MAX7000_TECHNOLOGY_MAPPER
- MAX7000_USE_CHECKSUM_AS_USERCODE
- MAX7K_CLIQUE_TYPE
- MAX9000
- MAX_AUTO_GLOBAL_REGISTER_CONTROLS
- MAX_BALANCING_DSP_BLOCKS
- MAX_CLOCK_ARRIVAL_SKEW
- MAX_CLOCKS_ALLOWED
- MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION
- MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION
- MAX_CORE_JUNCTION_TEMP
- MAX_CORE_SUPPLY_VOLTAGE
- MAX_CURRENT_FOR_ELECTROMIGRATION
- MAX_CURRENT_FOR_VIO_ELECTROMIGRATION
- MAX_DATA_ARRIVAL_SKEW
- MAX_DELAY_FOR_CORE_PERIPHERY_TRANSFER
- MAX_DELAY_FOR_PERIPHERY_CORE_TRANSFER
- MAX_DELAY
- MAX_FANOUT
- MAX_GLOBAL_CLOCKS_ALLOWED
- MAX_IGNORED_ASGN_MSG
- MAXII_CARRY_CHAIN_LENGTH
- MAXII_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- MAXII_OPTIMIZATION_TECHNIQUE
- MAXIMUM_EFFORT
- MAXIMUM
- MAX_LABS
- MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED
- MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS
- MAX_PERIPHERY_CLOCKS_ALLOWED
- MAXPLUSII
- MAX_PROCESSORS_USED_FOR_MULTITHREADING
- MAX_RAM_BLOCKS_M4K
- MAX_RAM_BLOCKS_M512
- MAX_RAM_BLOCKS_MRAM
- MAX_REGIONAL_CLOCKS_ALLOWED
- MAX_SCC_SIZE
- MAX_WIRES_FOR_CORE_PERIPHERY_ROUTER
- MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER
- MAX_WIRES_FOR_PERIPHERY_CORE_ROUTER
- MAX_WIRES_FOR_PERIPHERY_CORE_TRANSFER
- MEDIUM
- MEGAFUNCTION_GENERATED_TRI
- MEGALAB_COLUMN
- MEGALAB
- MEGARAM
- MEMBER_OF
- MEM_INTERFACE_DELAY_CHAIN_CONFIG
- MEMORY_INTERFACE_DATA_PIN_GROUP
- MERCURY_CARRY_CHAIN_LENGTH
- MERCURY_CLIQUE_TYPE
- MERCURY_CONFIG_DEVICE_JTAG_USER_CODE
- MERCURY_CONFIGURATION_DEVICE
- MERCURY_CONFIGURATION_SCHEME
- MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- MERCURY_DEVICE_IO_STANDARD
- MERCURY_FITTER_TYPE
- MERCURY_JTAG_USER_CODE
- MERCURY_OPTIMIZATION_TECHNIQUE
- MERCURY_TECHNOLOGY_MAPPER
- MERGE_EQUIVALENT_BIDIRS
- MERGE_EQUIVALENT_INPUTS
- MERGE_HEX_FILE
- MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR
- MESSAGE_DISABLE
- MESSAGE_ENABLE
- MESSAGE_SUPPRESSION_RULE_FILE
- MFCU
- MID_POWER
- MIF_FILE
- MIGRATION_ASSIGNMENT
- MIGRATION_AUTO_PACKED_REGISTERS
- MIGRATION_AUTO_PORT_SWAP
- MIGRATION_CONSTRAIN_CORE_RESOURCES
- MIGRATION_DEVICES
- MIGRATION_DIFFERENT_SOURCE_FILE
- MIGRATION_ONLY
- MIGRATION_PORT_SWAPPING
- MIGRATION_RAM_INFORMATION
- MIGRATION_RAM_PACKING_INFORMATION
- MIGRATION_REGISTER_PACKING
- MILLIVOLTS
- MIN_CORE_JUNCTION_TEMP
- MIN_CORE_SUPPLY_VOLTAGE
- MIN_DELAY_FOR_CORE_PERIPHERY_TRANSFER
- MIN_DELAY_FOR_PERIPHERY_CORE_TRANSFER
- MIN_DELAY
- MINIMAL_BITS
- MINIMIZE_AREA
- MINIMIZE_AREA_WITH_CHAINS
- MINIMIZE_POWER_ONLY
- MINIMUM_DELAY_REQUIREMENT
- MINIMUM
- MINIMUM_SEU_INTERVAL
- MINIMUM_TPD_REQUIREMENT
- MINIMUM_WIDTH_CLOCK_ENABLE
- MINIMUM_WIDTH_SLOAD_SCLEAR
- MIN_MTBF_REQUIREMENT
- MIN_TCO_REQUIREMENT
- MIN_TPD_REQUIREMENT
- MINUS_DELTA10
- MINUS_DELTA11
- MINUS_DELTA12
- MINUS_DELTA13
- MINUS_DELTA14
- MINUS_DELTA15
- MINUS_DELTA1
- MINUS_DELTA2
- MINUS_DELTA3
- MINUS_DELTA4
- MINUS_DELTA5
- MINUS_DELTA6
- MINUS_DELTA7
- MINUS_DELTA8
- MINUS_DELTA9
- MIN_WIRES_FOR_CORE_PERIPHERY_TRANSFER
- MIN_WIRES_FOR_PERIPHERY_CORE_TRANSFER
- MISC_FILE
- MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE
- MLAB
- MLAB_TIMING_CONSTRAINTS_IN_FEED_THROUGH_DONT_CARE_MODE
- MODE_0
- MODE_10
- MODE_11
- MODE_12
- MODE_13
- MODE_14
- MODE_15
- MODE_1
- MODE_2
- MODE_3
- MODE_4
- MODE_5
- MODE_6
- MODE_7
- MODE_8
- MODE_9
- MODE_DEFAULT
- MODEL_1
- MODEL_2
- MODEL_3
- MODULE_BLOATING_FACTOR
- MOVE_TO_TOP_IO
- MP2_EXPORT_FILE
- MULTICYCLE_HOLD
- MULTICYCLE
- MULTIPLY_BASE_CLOCK_BY
- MULTIPLY_BASE_CLOCK_PERIOD_BY
- MULTITAP_FILE
- MUX_RESTRUCTURE
- MUX_USE_ROUTING_ASSIGNMENT
- NCEO_OPEN_DRAIN
- NCEO_RESERVED_CYCLONEII
- NCEO_RESERVED
- NCE_PIN
- NDQS_LOCAL_CLOCK_DELAY_CHAIN
- NEAR_END
- NEAR_GLOBAL_CLOCK
- NEAR_REGIONAL_CLOCK
- NEGATIVE_180
- NEGATIVE_90
- NEGATIVE_EDGE
- NETLIST_ONLY
- NETLIST_VIEWER_ASSIGNMENT
- NETO_ASSIGNMENT
- NEVER_ALLOW
- NEVER
- NEVER_REGENERATE_IP
- NEVER_REGENERATE_IP_SIM
- NEW_EXTRACTOR
- NO_AUTO_INST_DISCOVERY
- NO_BACK_ANNOTATION
- NO_BYTE_ENABLE
- NO_DC_GAIN
- NO_GLOBAL_ROUTE
- NOMINAL_CORE_SUPPLY_VOLTAGE
- NONDEFAULT_LIBS
- NONE
- NON_LOCAL
- NON_QPI_MODE
- NON_S1_MODE
- NONSYNCHSTRUCT_CAT
- NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE
- NONSYNCHSTRUCT_RULE_COMBLOOP
- NONSYNCHSTRUCT_RULE_DELAY_CHAIN
- NONSYNCHSTRUCT_RULE_DLATCH
- NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN
- NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED
- NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR
- NONSYNCHSTRUCT_RULE_REG_LOOP
- NONSYNCHSTRUCT_RULE_RIPPLE_CLK
- NONSYNCHSTRUCT_RULE_SRLATCH
- NORMAL_COMPILATION
- NORMAL_LCELL_INSERT
- NORMAL
- NO_SDC_PROMOTION
- NOT_A_CLOCK
- NOT_BOOST
- NOT_CLOCK
- NOT_GATE_PUSH_BACK
- NO_TO_OPTION_REQUIRED
- NOT_USED
- NO_VOLTAGE_BOOST
- NTFQ_MSG_ACF_ASSIGNMENTS_CHANGED
- NUMBER_OF_DESTINATION_TO_REPORT
- NUMBER_OF_EXAMPLE_NODES_REPORTED
- NUMBER_OF_INVERTED_REGISTERS_REPORTED
- NUMBER_OF_PATHS_TO_REPORT
- NUMBER_OF_PROTECTED_REGISTERS_REPORTED
- NUMBER_OF_REMOVED_REGISTERS_REPORTED
- NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT
- NUMBER_OF_SWEPT_NODES_REPORTED
- NUMBER_OF_SYNTHESIS_MIGRATION_ROWS
- NUM_PARALLEL_PROCESSORS
- NWS_NRS_NCS_CS_RESERVED
- OBJECT_FILE
- OBSAI_1536
- OBSAI_3072
- OBSAI_6144
- OBSAI_768
- OBSERVABLE
- OCP_AUTO_PARTITION
- OCP_FILE
- OCP_HW_EVAL
- OCP_PARTITION
- OCP_TIMEOUT_PARTITION
- OCT_100_OHMS
- OCT_120_OHMS
- OCT_150_OHMS
- OCT_AND_IMPEDANCE_MATCHING_CYCLONEII
- OCT_AND_IMPEDANCE_MATCHING
- OCT_AND_IMPEDANCE_MATCHING_STRATIXII
- OCT_CONTROL_BLOCK
- OCT_REGISTER
- OE_DELAY_CHAIN
- OE_DELAY
- OE_OPTION
- OFFSET_FROM_BASE_CLOCK
- OFFSET_MAIN
- OFFSET_PO1
- OFFSET_PRE
- ON_CHIP_BITSTREAM_DECOMPRESSION
- ONE_HOT
- OPTIMISTIC
- OPTIMIZATION_MODE
- OPTIMIZATION_TECHNIQUE_APEX20K
- OPTIMIZATION_TECHNIQUE_ARMSTRONG
- OPTIMIZATION_TECHNIQUE_CYCLONEII
- OPTIMIZATION_TECHNIQUE_CYCLONE
- OPTIMIZATION_TECHNIQUE_DALI
- OPTIMIZATION_TECHNIQUE_FLEX10K
- OPTIMIZATION_TECHNIQUE_FLEX6K
- OPTIMIZATION_TECHNIQUE
- OPTIMIZATION_TECHNIQUE_MAX7000
- OPTIMIZATION_TECHNIQUE_TSUNAMI
- OPTIMIZATION_TECHNIQUE_YEAGER
- OPTIMIZED_EFFORT
- OPTIMIZE_FAST_CORNER_TIMING
- OPTIMIZE_FOR_METASTABILITY
- OPTIMIZE_HOLD_TIMING
- OPTIMIZE_INTERNAL_TIMING
- OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING
- OPTIMIZE_IO_TIMING
- OPTIMIZE_MULTI_CORNER_TIMING
- OPTIMIZE_NETLIST_FOR_ROUTABILITY
- OPTIMIZE_PERSONA_ROUTABILITY
- OPTIMIZE_POWER_DURING_FITTING
- OPTIMIZE_POWER_DURING_SYNTHESIS
- OPTIMIZE_SIGNAL_INTEGRITY
- OPTIMIZE_SSN
- OPTIMIZE_TIMING
- OPTIONS_FOR_ENTITIES_ONLY
- OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
- OPTIONS_FOR_NODES_AND_ENTITIES
- ORIGINAL_INTERFACE_PORT_NAME
- ORIGINAL_QUARTUS_VERSION
- ORIGINATING_COMPANION_REVISION
- OSC_CLK_1_100MHZ
- OSC_CLK_1_125MHZ
- OSC_CLK_1_25MHZ
- OTHER_APF_RESERVED
- OTHER
- OTP_AUTO_PARTITION
- OTP_PARTITION
- OUTPUT_BUFFER_DELAY_CONTROL
- OUTPUT_BUFFER_DELAY
- OUTPUT_DELAY_CHAIN
- OUTPUT_DELAY
- OUTPUT_ENABLE_DELAY
- OUTPUT_ENABLE_GROUP
- OUTPUT_ENABLE_REGISTER_DUPLICATION
- OUTPUT_ENABLE_REGISTER
- OUTPUT_ENABLE_ROUTING
- OUTPUT_FILE_NAME
- OUTPUT_IO_TIMING_ENDPOINT
- OUTPUT_IO_TIMING_FAR_END_VMEAS
- OUTPUT_IO_TIMING_NEAR_END_VMEAS
- OUTPUT
- OUTPUT_MAX_DELAY
- OUTPUT_MIN_DELAY
- OUTPUT_OCT_VALUE
- OUTPUT_PIN_C_FAR
- OUTPUT_PIN_C_NEAR
- OUTPUT_PIN_C_PER_LENGTH
- OUTPUT_PIN_LENGTH
- OUTPUT_PIN_LOAD
- OUTPUT_PIN_L_PER_LENGTH
- OUTPUT_PIN_R_FAR_HIGH
- OUTPUT_PIN_R_FAR_LOW
- OUTPUT_PIN_R_FAR_SERIES
- OUTPUT_PIN_R_NEAR_HIGH
- OUTPUT_PIN_R_NEAR_LOW
- OUTPUT_PIN_R_NEAR_SERIES
- OUTPUT_PIN_V_TERMINATION
- OUTPUT_REGISTER
- OUTPUT_TERMINATION
- OUTPUT_TYPE
- OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS
- OWNED_BY_UPPER_PARTITION
- P0H9
- P0L9
- PACKAGE_SKEW_COMPENSATION
- PACK_ALL_IO_REGISTERS
- PAD_TO_CORE_DELAY
- PAD_TO_DDIO_REGISTER_DELAY
- PAD_TO_INPUT_REGISTER_DELAY
- PARALLEL_50_OHMS_WITH_CALIBRATION
- PARALLEL_EXPANDER_CHAIN_LENGTH
- PARALLEL
- PARALLEL_SYNTHESIS
- PARAMETER_ARRAY
- PARAMETER_BOOL
- PARAMETER_CHAR
- PARAMETER_ENUM
- PARAMETER
- PARAMETER_PHYSICAL
- PARAMETER_SIGNED_BIN
- PARAMETER_SIGNED_DEC
- PARAMETER_SIGNED_FLOAT
- PARAMETER_SIGNED_HEX
- PARAMETER_SIGNED_OCT
- PARAMETERS
- PARAMETER_STRING
- PARAMETER_UNKNOWN
- PARAMETER_UNSIGNED_BIN
- PARAMETER_UNSIGNED_DEC
- PARAMETER_UNSIGNED_FLOAT
- PARAMETER_UNSIGNED_HEX
- PARAMETER_UNSIGNED_OCT
- PARAMETER_UNSIZED_BIT_LITERAL
- PARTIAL_RECONFIGURATION_PARTITION
- PARTIAL_SRAM_OBJECT_FILE
- PARTITION_ALWAYS_USE_QXP_NETLIST
- PARTITION_ASD_REGION_ID
- PARTITION_ASD_REGION
- PARTITION_BACK_ANNOTATION
- PARTITION_COLOR
- PARTITION_COLOUR
- PARTITION_ENABLE_STRICT_PRESERVATION
- PARTITION_EXTRACT_HARD_BLOCK_NODES
- PARTITION_FITTER_PRESERVATION_LEVEL
- PARTITION_HIERARCHY
- PARTITION_IGNORE_SOURCE_FILE_CHANGES
- PARTITION_IMPORT_ASSIGNMENTS
- PARTITION_IMPORT_EXISTING_ASSIGNMENTS
- PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS
- PARTITION_IMPORT_FILE
- PARTITION_IMPORT_NEW_ASSIGNMENTS
- PARTITION_IMPORT_PIN_ASSIGNMENTS
- PARTITION_IMPORT_PROMOTE_ASSIGNMENTS
- PARTITION_LAST_IMPORTED_FILE
- PARTITION
- PARTITION_NETLIST_TYPE
- PARTITION_ONLY
- PARTITION_PRESERVE_HIGH_SPEED_TILES
- PARTITION_SOURCE
- PARTITION_TYPE
- PASSIVE_PARALLEL_ASYNCHRONOUS
- PASSIVE_PARALLEL_SYNCHRONOUS
- PASSIVE_PARALLEL_X16
- PASSIVE_PARALLEL_X32
- PASSIVE_PARALLEL_X8
- PASSIVE_PROGRAMMING_FILE_NAME
- PASSIVE_RESISTOR
- PASSIVE_SERIAL_ASYNCHRONOUS
- PASSIVE_SERIAL
- PBIP_FILE
- PCB_LAYERS
- PCIE_CABLE
- PCIE_GEN1_3P5DB
- PCIE_GEN1
- PCIE_GEN2_3P5DB
- PCIE_GEN2_6DB
- PCIE_GEN2
- PCIE_GEN3
- PCIE_PRE_EMPH_GEN1
- PCIE_PRE_EMPH_GEN2_3_5DB_DEEMPH
- PCIE_PRE_EMPH_GEN2_6DB_DEEMPH
- PCIE_PRE_EMPH_GEN2_LOW_MARGIN
- PCIE_PRE_EMPH_GEN2_LOW_SWING
- PCIE_VOD_GEN1
- PCIE_VOD_GEN2_3_5DB_DEEMPH
- PCIE_VOD_GEN2_6DB_DEEMPH
- PCIE_VOD_GEN2_LOW_MARGIN
- PCIE_VOD_GEN2_LOW_SWING
- PCI_IO
- PDC_FILE
- PERIPHERAL
- PERIPHERY_CLOCK
- PERIPHERY_REUSE_CORE
- PERIPHERY_SEED
- PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION
- PERIPH_FITTER_SCRIPT
- PERIPH_REPORT_SCRIPT
- PERSONA_FILE
- PESSIMISTIC
- PEXP_LENGTH
- PEXP_LENGTH_MAX7000
- PHASE_FROM_BASE_CLOCK
- PHASE_OF_0_DEGREES
- PHASE_OF_72_DEGREES
- PHASE_OF_90_DEGREES
- PHYSICAL_SHIFT_REGISTER_INFERENCE
- PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING_DISABLE_DESTINATION_CHECK
- PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
- PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING_REG_REACH
- PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
- PHYSICAL_SYNTHESIS_COMBO_LOGIC
- PHYSICAL_SYNTHESIS_EFFORT
- PHYSICAL_SYNTHESIS
- PHYSICAL_SYNTHESIS_LOG_FILE
- PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA
- PHYSICAL_SYNTHESIS_PIPELINE
- PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
- PHYSICAL_SYNTHESIS_REGISTER_RETIMING
- PIN_CONNECT_FROM_NODE
- PIN_FILE
- PIN_PLANNER_DISPLAY_ASSIGNMENT_VALUE_FROM_POSITIVE_PIN_TO_NEGATIVE_PIN
- PIN_PLANNER_FILE
- PIN_PLANNER_GROUP_EXCEPTION
- PIN_PLANNER_GROUP_MEMBER
- PIN_PLANNER_GROUP_SETTINGS
- PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILE
- PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILES
- PLACEMENT_AND_ROUTING_AND_TILE
- PLACEMENT_AND_ROUTING
- PLACEMENT_EFFORT_MULTIPLIER
- PLACEMENT
- PLACE_REGION
- PLD_TO_STRIPE_INTERRUPTS_EPXA4_10
- PLL_APLLY_PFD_ISSUE_WORKAROUND
- PLL_AUTO_RESET
- PLL_BANDWIDTH_PRESET
- PLL_C_COUNTER_DELAY_CHAIN
- PLL_CHANNEL_SPACING
- PLL_COMPENSATE
- PLL_COMPENSATION_MODE
- PLL_DISABLE_COUNTER_SETTINGS_OPTIMIZATION
- PLL_ENFORCE_USER_PHASE_SHIFT
- PLL_EXTERNAL_FEEDBACK_BOARD_DELAY
- PLL_FEEDBACK_CLOCK_SIGNAL
- PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY
- PLL_FORCE_OUTPUT_COUNTER
- PLL_IGNORE_MIGRATION_DEVICES
- PLL_LOCK_10K
- PLL_LOCK
- PLL_LVDS_DELAY_CHAIN
- PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING
- PLL_OUTPUT_CLOCK_FREQUENCY
- PLL_PFD_CLOCK_FREQUENCY
- PLL_PHASE_RECONFIG_COUNTER_REMAP_LCELL
- PLL_PRE_C_COUNTER_DELAY_CHAIN
- PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL
- PLL_TYPE
- PLL_VCO_CLOCK_FREQUENCY
- PLUS_DELTA10
- PLUS_DELTA11
- PLUS_DELTA12
- PLUS_DELTA13
- PLUS_DELTA14
- PLUS_DELTA15
- PLUS_DELTA1
- PLUS_DELTA2
- PLUS_DELTA3
- PLUS_DELTA4
- PLUS_DELTA5
- PLUS_DELTA6
- PLUS_DELTA7
- PLUS_DELTA8
- PLUS_DELTA9
- PMBUS_MASTER
- PMBUS_SLAVE
- POF_VERIFY_PROTECT
- POR_SCHEME
- POSITIVE_180
- POSITIVE_90
- POSITIVE_EDGE
- POST_BUILD_COMMAND_LINE
- POST_CONFIG
- POST_FIT_CONNECT_FROM_SLD_NODE_ENTITY_PORT
- POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT
- POST_FIT
- POST_FIT_WITH_ROUTING
- POST_FLOW_SCRIPT_FILE
- POST_MAPPING_RESYNTHESIS
- POST_MODULE_SCRIPT_FILE
- POST_SYNTH
- POWER_APPLY_THERMAL_MARGIN
- POWER_AUTO_COMPUTE_TJ
- POWER_BOARD_TEMPERATURE
- POWER_BOARD_THERMAL_MODEL
- POWER_COOLING_FOR_MAX_TJ
- POWER_DEFAULT_INPUT_IO_TOGGLE_RATE
- POWER_DEFAULT_TOGGLE_RATE
- POWER_ESTIMATION_ASSIGNMENT
- POWER_ESTIMATION_END_TIME
- POWER_ESTIMATION_START_TIME
- POWER_GLITCH_FACTOR
- POWER_HPS_DYNAMIC_POWER_DUAL
- POWER_HPS_DYNAMIC_POWER_SINGLE
- POWER_HPS_ENABLE
- POWER_HPS_JUNCTION_TEMPERATURE
- POWER_HPS_PROC_FREQ
- POWER_HPS_STATIC_POWER
- POWER_HPS_TOTAL_POWER
- POWER_HSSI_LEFT
- POWER_HSSI
- POWER_HSSI_RIGHT
- POWER_HSSI_VCCHIP_LEFT
- POWER_HSSI_VCCHIP_RIGHT
- POWER_INPUT_FILE
- POWER_INPUT_FILE_NAME
- POWER_INPUT_FILE_SETTINGS
- POWER_INPUT_FILE_TYPE
- POWER
- POWER_MAX_TJ_VALUE
- POWER_OCS_VALUE
- POWER_OJB_VALUE
- POWER_OJC_VALUE
- POWER_OSA_VALUE
- POWER_OUTPUT_SAF_NAME
- POWER_PRESET_COOLING_SOLUTION
- POWER_READ_INPUT_FILE
- POWER_REPORT_POWER_DISSIPATION
- POWER_REPORT_SIGNAL_ACTIVITY
- POWER_STATIC_PROBABILITY
- POWER_STATIC_TOGGLE_RATE
- POWER_TJ_VALUE
- POWER_TOGGLE_RATE
- POWER_TOGGLE_RATE_PERCENTAGE
- POWER_UP_HIGH
- POWER_UP_LEVEL
- POWER_USE_CUSTOM_COOLING_SOLUTION
- POWER_USE_DEVICE_CHARACTERISTICS
- POWER_USE_INPUT_FILES
- POWER_USE_PVA
- POWER_USE_TA_VALUE
- POWER_USE_VOLTAGE
- POWER_VCCA_FPLL_USER_VOLTAGE
- POWER_VCCA_GTBR_USER_VOLTAGE
- POWER_VCCA_GTB_USER_VOLTAGE
- POWER_VCCA_GXBL_USER_OPTION
- POWER_VCCA_GXBL_USER_VOLTAGE
- POWER_VCCA_GXBR_USER_OPTION
- POWER_VCCA_GXBR_USER_VOLTAGE
- POWER_VCCA_GXB_USER_OPTION
- POWER_VCCA_GXB_USER_VOLTAGE
- POWER_VCCA_L_USER_OPTION
- POWER_VCCA_L_USER_VOLTAGE
- POWER_VCCA_PLL_USER_VOLTAGE
- POWER_VCCA_R_USER_OPTION
- POWER_VCCA_R_USER_VOLTAGE
- POWER_VCCA_USER_VOLTAGE
- POWER_VCCAUX_SHARED_USER_VOLTAGE
- POWER_VCCAUX_USER_OPTION
- POWER_VCCAUX_USER_VOLTAGE
- POWER_VCCBAT_USER_VOLTAGE
- POWER_VCCCB_USER_OPTION
- POWER_VCCCB_USER_VOLTAGE
- POWER_VCCD_FPLL_USER_VOLTAGE
- POWER_VCCD_PLL_USER_VOLTAGE
- POWER_VCCD_USER_VOLTAGE
- POWER_VCCE_GXBL_USER_VOLTAGE
- POWER_VCCE_GXBR_USER_VOLTAGE
- POWER_VCCE_GXB_USER_VOLTAGE
- POWER_VCCEH_GXBL_USER_VOLTAGE
- POWER_VCCEH_GXBR_USER_VOLTAGE
- POWER_VCCEH_GXB_USER_VOLTAGE
- POWER_VCCERAM_USER_VOLTAGE
- POWER_VCCE_USER_VOLTAGE
- POWER_VCCH_GTBR_USER_VOLTAGE
- POWER_VCCH_GTB_USER_VOLTAGE
- POWER_VCCH_GXBL_USER_OPTION
- POWER_VCCH_GXBL_USER_VOLTAGE
- POWER_VCCH_GXBR_USER_OPTION
- POWER_VCCH_GXBR_USER_VOLTAGE
- POWER_VCCH_GXB_USER_OPTION
- POWER_VCCH_GXB_USER_VOLTAGE
- POWER_VCCHIP_L_USER_VOLTAGE
- POWER_VCCHIP_R_USER_VOLTAGE
- POWER_VCCHIP_USER_VOLTAGE
- POWER_VCCH_L_USER_VOLTAGE
- POWER_VCC_HPS_USER_VOLTAGE
- POWER_VCCH_R_USER_VOLTAGE
- POWER_VCCHSSI_L_USER_VOLTAGE
- POWER_VCCHSSI_R_USER_VOLTAGE
- POWER_VCCINT_USER_VOLTAGE
- POWER_VCCIO_HPS_USER_VOLTAGE
- POWER_VCCIOREF_HPS_USER_VOLTAGE
- POWER_VCCIO_USER_OPTION
- POWER_VCCIO_USER_VOLTAGE
- POWER_VCCL_GTBL_USER_VOLTAGE
- POWER_VCCL_GTBR_USER_VOLTAGE
- POWER_VCCL_GTB_USER_VOLTAGE
- POWER_VCCL_GXBL_USER_VOLTAGE
- POWER_VCCL_GXBR_USER_VOLTAGE
- POWER_VCCL_GXB_USER_OPTION
- POWER_VCCL_GXB_USER_VOLTAGE
- POWER_VCCL_HPS_USER_VOLTAGE
- POWER_VCCL_USER_VOLTAGE
- POWER_VCCPD_USER_OPTION
- POWER_VCCPD_USER_VOLTAGE
- POWER_VCCPGM_USER_VOLTAGE
- POWER_VCCPLL_HPS_USER_VOLTAGE
- POWER_VCCPT_USER_VOLTAGE
- POWER_VCCP_USER_VOLTAGE
- POWER_VCCR_GTBL_USER_VOLTAGE
- POWER_VCCR_GTBR_USER_VOLTAGE
- POWER_VCCR_GTB_USER_VOLTAGE
- POWER_VCCR_GXBL_USER_OPTION
- POWER_VCCR_GXBL_USER_VOLTAGE
- POWER_VCCR_GXBR_USER_OPTION
- POWER_VCCR_GXBR_USER_VOLTAGE
- POWER_VCCR_GXB_USER_OPTION
- POWER_VCCR_GXB_USER_VOLTAGE
- POWER_VCCR_L_USER_VOLTAGE
- POWER_VCCR_R_USER_VOLTAGE
- POWER_VCCRSTCLK_HPS_USER_VOLTAGE
- POWER_VCCR_USER_VOLTAGE
- POWER_VCCT_GTBL_USER_VOLTAGE
- POWER_VCCT_GTBR_USER_VOLTAGE
- POWER_VCCT_GTB_USER_VOLTAGE
- POWER_VCCT_GXBL_USER_OPTION
- POWER_VCCT_GXBL_USER_VOLTAGE
- POWER_VCCT_GXBR_USER_OPTION
- POWER_VCCT_GXBR_USER_VOLTAGE
- POWER_VCCT_GXB_USER_OPTION
- POWER_VCCT_GXB_USER_VOLTAGE
- POWER_VCCT_L_USER_VOLTAGE
- POWER_VCCT_R_USER_VOLTAGE
- POWER_VCCT_USER_VOLTAGE
- POWER_VCC_USER_VOLTAGE
- POWER_VCD_FILE_END_TIME
- POWER_VCD_FILE_START_TIME
- POWER_VCD_FILTER_GLITCHES
- POWER_WILDCARDS
- PPF_FILE
- PPLQ_GROUP_EXCEPTION
- PPLQ_GROUP
- PPLQ_GROUP_MEMBER
- PR_ALLOW_GLOBAL_LIMS
- PR_BASE
- PR_BASE_MSF
- PR_BASE_SOF
- PR_DONE_OPEN_DRAIN
- PRE_CONFIG
- PRE_FLOW_SCRIPT_FILE
- PRE_MAPPING_RESYNTHESIS
- PR_ERROR_OPEN_DRAIN
- PRESERVED_HANGING_NODES
- PRESERVE_FANOUT_FREE_NODE
- PRESERVE_FANOUT_FREE_WYSIWYG
- PRESERVE_HIERARCHICAL_BOUNDARY
- PRESERVE
- PRESERVE_PLL_COUNTER_ORDER
- PRESERVE_PORT_NAME
- PRESERVE_REGISTER
- PRESERVE_REGISTER_SYN_ONLY
- PRESERVE_SYNONYMS
- PRESERVE_UNUSED_XCVR_CHANNEL
- PR_IMPL
- PRINT_DEBUG_MSG_AND_EXIT
- PRIORITY_SEU_AREA
- PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10
- PROCESSOR
- PRODUCT_TERM
- PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES
- PROGRAMMABLE_POWER_TECHNOLOGY_SETTING
- PROGRAMMABLE_PREEMPHASIS
- PROGRAMMABLE_VOD
- PROGRAMMER_ASSIGNMENT
- PROGRAMMER_OBJECT_FILE
- PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT
- PROGRAMMING_BITSTREAM_ENCRYPTION_UPDATE_RATIO
- PROGRAMMING_FILE_TYPE
- PROGRAMMING_MODE_APEX20KF
- PROGRAMMING_MODE_APEX20K
- PROGRAMMING_MODE_ARMSTRONG
- PROGRAMMING_MODE_CUDA
- PROGRAMMING_MODE_CYCLONEII
- PROGRAMMING_MODE_DALI
- PROGRAMMING_MODE_EXCALIBUR
- PROGRAMMING_MODE_FLEX10K
- PROGRAMMING_MODE_FLEX6K
- PROGRAMMING_MODE
- PROGRAMMING_MODE_TITAN
- PROGRAMMING_MODE_TORNADO
- PROGRAMMING_MODE_YEAGER
- PROGRAMMING_MODE_ZIPPLEBACK
- PROJECT_ASSIGNMENT
- PROJECT_CREATION_TIME_DATE
- PROJECT_INFO
- PROJECT_IP_GEN_PARALLEL_ENABLED
- PROJECT_IP_GEN_SIM_FILESETS_WITH_SYNTHESIS
- PROJECT_IP_REGENERATION_POLICY
- PROJECT_IP_SEARCH_PATHS
- PROJECT_IP_SIM_REGENERATION_POLICY
- PROJECT_MIGRATION_TIMESTAMP
- PROJECT_OUTPUT_DIRECTORY
- PROJECT_SHOW_ENTITY_NAME
- PROJECT_SOURCE_FILE
- PROJECT_THUNDER_BAY
- PROJECT_USE_SIMPLIFIED_NAMES
- PRO_ONLY
- PROPAGATE_CONSTANTS_ON_INPUTS
- PROPAGATE_INVERSIONS_ON_INPUTS
- PR_PARTITION
- PR_PINS_OPEN_DRAIN
- PRPOF_ID_CHECK
- PRPOF_ID
- PRPOF_ID_VALUE
- PR_READY_OPEN_DRAIN
- PR_SECURITY_VALIDATION
- PR_SKIP_BASE_CHECK
- PR_SYN
- PULL_DN
- PULLDOWN_DRIVE_STRENGTH_BITS
- PULL_DOWN
- PULL_RESISTOR
- PULLUP_DRIVE_STRENGTH_BITS
- PULL_UP
- PULL_UP_TO_VCCELA
- PULSE_WIDTH_0
- PULSE_WIDTH_1
- PULSE_WIDTH_2_LARGE
- PULSE_WIDTH_2
- PULSE_WIDTH_NONE
- PWRMGT_ADV_CLOCK_DATA_FALL_TIME
- PWRMGT_ADV_CLOCK_DATA_RISE_TIME
- PWRMGT_ADV_DATA_HOLD_TIME
- PWRMGT_ADV_DATA_SETUP_TIME
- PWRMGT_ADV_FPGA_RELEASE_DELAY
- PWRMGT_ADV_INITIAL_DELAY
- PWRMGT_ADV_VOLTAGE_STABLE_DELAY
- PWRMGT_ADV_VOUT_READING_ERR_MARGIN
- PWRMGT_BUS_SPEED_MODE
- PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE
- PWRMGT_DIRECT_FORMAT_COEFFICIENT_B
- PWRMGT_DIRECT_FORMAT_COEFFICIENT_M
- PWRMGT_DIRECT_FORMAT_COEFFICIENT_R
- PWRMGT_LINEAR_FORMAT_N
- PWRMGT_PAGE_COMMAND_ENABLE
- PWRMGT_SLAVE_DEVICE0_ADDRESS
- PWRMGT_SLAVE_DEVICE1_ADDRESS
- PWRMGT_SLAVE_DEVICE2_ADDRESS
- PWRMGT_SLAVE_DEVICE3_ADDRESS
- PWRMGT_SLAVE_DEVICE4_ADDRESS
- PWRMGT_SLAVE_DEVICE5_ADDRESS
- PWRMGT_SLAVE_DEVICE6_ADDRESS
- PWRMGT_SLAVE_DEVICE7_ADDRESS
- PWRMGT_SLAVE_DEVICE_TYPE
- PWRMGT_TABLE_VERSION
- PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT
- PWRMGT_VOLTAGE_OUTPUT_FORMAT
- QAR_FILE
- QARLOG_FILE
- QDB_FILE
- QDB_FILE_PARTITION
- QDB_PATH
- QDFS_USE_CHERRY
- QDR_D_PIN_GROUP
- QHD_MODE
- QIC_EXPORT_FILE
- QIC_EXPORT_FLATTEN
- QIC_EXPORT_NETLIST_TYPE
- QIC_EXPORT_PARTITION_NAME
- QIC_EXPORT_ROUTING
- QIC_USE_BINARY_DATABASES
- QID_ASSIGNMENT
- QII_AUTO_PACKED_REGISTERS
- QIP_FILE
- QKY_FILE
- QPI_MODE
- QSGMII_5000
- QSYS_FILE
- QUARTUS_ACF_FILE
- QUARTUS_COMPILER_SETTINGS_FILE
- QUARTUS_ENTITY_SETTINGS_FILE
- QUARTUS_GUI_SIGNATURE_ID
- QUARTUSII
- QUARTUS_PROJECT_FILE
- QUARTUS_PROJECT_SETTINGS_FILE
- QUARTUS_PTF_FILE
- QUARTUS_SBD_FILE
- QUARTUS_SIMULATOR_SETTINGS_FILE
- QUARTUS_SOFTWARE_SETTINGS_FILE
- QUARTUS_STANDARD_DELAY_FILE
- QUARTUS_WORKSPACE_FILE
- QVAR_FILE
- QXP_FILE
- R_ADAPT_DFE_CONTROL_SEL_0
- R_ADAPT_DFE_CONTROL_SEL_1
- R_ADAPT_DFE_CONTROL_SEL_2
- R_ADAPT_DFE_CONTROL_SEL_3
- R_ADAPT_DFE_SEL_0
- R_ADAPT_DFE_SEL_1
- R_ADAPT_VGA_SEL_0
- R_ADAPT_VGA_SEL_1
- R_ADAPT_VREF_SEL_0
- R_ADAPT_VREF_SEL_1
- R_ADAPT_VREF_SEL_2
- R_ADAPT_VREF_SEL_3
- RADP_CTLE_ACGAIN_4S_0
- RADP_CTLE_ACGAIN_4S_10
- RADP_CTLE_ACGAIN_4S_11
- RADP_CTLE_ACGAIN_4S_12
- RADP_CTLE_ACGAIN_4S_13
- RADP_CTLE_ACGAIN_4S_14
- RADP_CTLE_ACGAIN_4S_15
- RADP_CTLE_ACGAIN_4S_16
- RADP_CTLE_ACGAIN_4S_17
- RADP_CTLE_ACGAIN_4S_18
- RADP_CTLE_ACGAIN_4S_19
- RADP_CTLE_ACGAIN_4S_1
- RADP_CTLE_ACGAIN_4S_20
- RADP_CTLE_ACGAIN_4S_21
- RADP_CTLE_ACGAIN_4S_22
- RADP_CTLE_ACGAIN_4S_23
- RADP_CTLE_ACGAIN_4S_24
- RADP_CTLE_ACGAIN_4S_25
- RADP_CTLE_ACGAIN_4S_26
- RADP_CTLE_ACGAIN_4S_27
- RADP_CTLE_ACGAIN_4S_28
- RADP_CTLE_ACGAIN_4S_2
- RADP_CTLE_ACGAIN_4S_3
- RADP_CTLE_ACGAIN_4S_4
- RADP_CTLE_ACGAIN_4S_5
- RADP_CTLE_ACGAIN_4S_6
- RADP_CTLE_ACGAIN_4S_7
- RADP_CTLE_ACGAIN_4S_8
- RADP_CTLE_ACGAIN_4S_9
- RADP_CTLE_EQZ_1S_SEL_0
- RADP_CTLE_EQZ_1S_SEL_10
- RADP_CTLE_EQZ_1S_SEL_11
- RADP_CTLE_EQZ_1S_SEL_12
- RADP_CTLE_EQZ_1S_SEL_13
- RADP_CTLE_EQZ_1S_SEL_14
- RADP_CTLE_EQZ_1S_SEL_15
- RADP_CTLE_EQZ_1S_SEL_1
- RADP_CTLE_EQZ_1S_SEL_2
- RADP_CTLE_EQZ_1S_SEL_3
- RADP_CTLE_EQZ_1S_SEL_4
- RADP_CTLE_EQZ_1S_SEL_5
- RADP_CTLE_EQZ_1S_SEL_6
- RADP_CTLE_EQZ_1S_SEL_7
- RADP_CTLE_EQZ_1S_SEL_8
- RADP_CTLE_EQZ_1S_SEL_9
- RADP_DFE_FLTAP_POSITION_0
- RADP_DFE_FLTAP_POSITION_10
- RADP_DFE_FLTAP_POSITION_11
- RADP_DFE_FLTAP_POSITION_12
- RADP_DFE_FLTAP_POSITION_13
- RADP_DFE_FLTAP_POSITION_14
- RADP_DFE_FLTAP_POSITION_15
- RADP_DFE_FLTAP_POSITION_16
- RADP_DFE_FLTAP_POSITION_17
- RADP_DFE_FLTAP_POSITION_18
- RADP_DFE_FLTAP_POSITION_19
- RADP_DFE_FLTAP_POSITION_1
- RADP_DFE_FLTAP_POSITION_20
- RADP_DFE_FLTAP_POSITION_21
- RADP_DFE_FLTAP_POSITION_22
- RADP_DFE_FLTAP_POSITION_23
- RADP_DFE_FLTAP_POSITION_24
- RADP_DFE_FLTAP_POSITION_25
- RADP_DFE_FLTAP_POSITION_26
- RADP_DFE_FLTAP_POSITION_27
- RADP_DFE_FLTAP_POSITION_28
- RADP_DFE_FLTAP_POSITION_29
- RADP_DFE_FLTAP_POSITION_2
- RADP_DFE_FLTAP_POSITION_30
- RADP_DFE_FLTAP_POSITION_31
- RADP_DFE_FLTAP_POSITION_32
- RADP_DFE_FLTAP_POSITION_33
- RADP_DFE_FLTAP_POSITION_34
- RADP_DFE_FLTAP_POSITION_35
- RADP_DFE_FLTAP_POSITION_36
- RADP_DFE_FLTAP_POSITION_37
- RADP_DFE_FLTAP_POSITION_38
- RADP_DFE_FLTAP_POSITION_39
- RADP_DFE_FLTAP_POSITION_3
- RADP_DFE_FLTAP_POSITION_40
- RADP_DFE_FLTAP_POSITION_41
- RADP_DFE_FLTAP_POSITION_42
- RADP_DFE_FLTAP_POSITION_43
- RADP_DFE_FLTAP_POSITION_44
- RADP_DFE_FLTAP_POSITION_45
- RADP_DFE_FLTAP_POSITION_46
- RADP_DFE_FLTAP_POSITION_47
- RADP_DFE_FLTAP_POSITION_48
- RADP_DFE_FLTAP_POSITION_49
- RADP_DFE_FLTAP_POSITION_4
- RADP_DFE_FLTAP_POSITION_50
- RADP_DFE_FLTAP_POSITION_51
- RADP_DFE_FLTAP_POSITION_52
- RADP_DFE_FLTAP_POSITION_53
- RADP_DFE_FLTAP_POSITION_54
- RADP_DFE_FLTAP_POSITION_55
- RADP_DFE_FLTAP_POSITION_5
- RADP_DFE_FLTAP_POSITION_6
- RADP_DFE_FLTAP_POSITION_7
- RADP_DFE_FLTAP_POSITION_8
- RADP_DFE_FLTAP_POSITION_9
- RADP_DFE_FXTAP10_0
- RADP_DFE_FXTAP10_10
- RADP_DFE_FXTAP10_11
- RADP_DFE_FXTAP10_12
- RADP_DFE_FXTAP10_13
- RADP_DFE_FXTAP10_14
- RADP_DFE_FXTAP10_15
- RADP_DFE_FXTAP10_16
- RADP_DFE_FXTAP10_17
- RADP_DFE_FXTAP10_18
- RADP_DFE_FXTAP10_19
- RADP_DFE_FXTAP10_1
- RADP_DFE_FXTAP10_20
- RADP_DFE_FXTAP10_21
- RADP_DFE_FXTAP10_22
- RADP_DFE_FXTAP10_23
- RADP_DFE_FXTAP10_24
- RADP_DFE_FXTAP10_25
- RADP_DFE_FXTAP10_26
- RADP_DFE_FXTAP10_27
- RADP_DFE_FXTAP10_28
- RADP_DFE_FXTAP10_29
- RADP_DFE_FXTAP10_2
- RADP_DFE_FXTAP10_30
- RADP_DFE_FXTAP10_31
- RADP_DFE_FXTAP10_32
- RADP_DFE_FXTAP10_33
- RADP_DFE_FXTAP10_34
- RADP_DFE_FXTAP10_35
- RADP_DFE_FXTAP10_36
- RADP_DFE_FXTAP10_37
- RADP_DFE_FXTAP10_38
- RADP_DFE_FXTAP10_39
- RADP_DFE_FXTAP10_3
- RADP_DFE_FXTAP10_40
- RADP_DFE_FXTAP10_41
- RADP_DFE_FXTAP10_42
- RADP_DFE_FXTAP10_43
- RADP_DFE_FXTAP10_44
- RADP_DFE_FXTAP10_45
- RADP_DFE_FXTAP10_46
- RADP_DFE_FXTAP10_47
- RADP_DFE_FXTAP10_48
- RADP_DFE_FXTAP10_49
- RADP_DFE_FXTAP10_4
- RADP_DFE_FXTAP10_50
- RADP_DFE_FXTAP10_51
- RADP_DFE_FXTAP10_52
- RADP_DFE_FXTAP10_53
- RADP_DFE_FXTAP10_54
- RADP_DFE_FXTAP10_55
- RADP_DFE_FXTAP10_56
- RADP_DFE_FXTAP10_57
- RADP_DFE_FXTAP10_58
- RADP_DFE_FXTAP10_59
- RADP_DFE_FXTAP10_5
- RADP_DFE_FXTAP10_60
- RADP_DFE_FXTAP10_61
- RADP_DFE_FXTAP10_62
- RADP_DFE_FXTAP10_63
- RADP_DFE_FXTAP10_6
- RADP_DFE_FXTAP10_7
- RADP_DFE_FXTAP10_8
- RADP_DFE_FXTAP10_9
- RADP_DFE_FXTAP1_0
- RADP_DFE_FXTAP10_SGN_0
- RADP_DFE_FXTAP10_SGN_1
- RADP_DFE_FXTAP1_100
- RADP_DFE_FXTAP1_101
- RADP_DFE_FXTAP1_102
- RADP_DFE_FXTAP1_103
- RADP_DFE_FXTAP1_104
- RADP_DFE_FXTAP1_105
- RADP_DFE_FXTAP1_106
- RADP_DFE_FXTAP1_107
- RADP_DFE_FXTAP1_108
- RADP_DFE_FXTAP1_109
- RADP_DFE_FXTAP1_10
- RADP_DFE_FXTAP11_0
- RADP_DFE_FXTAP1_110
- RADP_DFE_FXTAP11_10
- RADP_DFE_FXTAP1_111
- RADP_DFE_FXTAP11_11
- RADP_DFE_FXTAP1_112
- RADP_DFE_FXTAP11_12
- RADP_DFE_FXTAP1_113
- RADP_DFE_FXTAP11_13
- RADP_DFE_FXTAP1_114
- RADP_DFE_FXTAP11_14
- RADP_DFE_FXTAP1_115
- RADP_DFE_FXTAP11_15
- RADP_DFE_FXTAP1_116
- RADP_DFE_FXTAP11_16
- RADP_DFE_FXTAP1_117
- RADP_DFE_FXTAP11_17
- RADP_DFE_FXTAP1_118
- RADP_DFE_FXTAP11_18
- RADP_DFE_FXTAP1_119
- RADP_DFE_FXTAP11_19
- RADP_DFE_FXTAP1_11
- RADP_DFE_FXTAP11_1
- RADP_DFE_FXTAP1_120
- RADP_DFE_FXTAP11_20
- RADP_DFE_FXTAP1_121
- RADP_DFE_FXTAP11_21
- RADP_DFE_FXTAP1_122
- RADP_DFE_FXTAP11_22
- RADP_DFE_FXTAP1_123
- RADP_DFE_FXTAP11_23
- RADP_DFE_FXTAP1_124
- RADP_DFE_FXTAP11_24
- RADP_DFE_FXTAP1_125
- RADP_DFE_FXTAP11_25
- RADP_DFE_FXTAP1_126
- RADP_DFE_FXTAP11_26
- RADP_DFE_FXTAP1_127
- RADP_DFE_FXTAP11_27
- RADP_DFE_FXTAP11_28
- RADP_DFE_FXTAP11_29
- RADP_DFE_FXTAP1_12
- RADP_DFE_FXTAP11_2
- RADP_DFE_FXTAP11_30
- RADP_DFE_FXTAP11_31
- RADP_DFE_FXTAP11_32
- RADP_DFE_FXTAP11_33
- RADP_DFE_FXTAP11_34
- RADP_DFE_FXTAP11_35
- RADP_DFE_FXTAP11_36
- RADP_DFE_FXTAP11_37
- RADP_DFE_FXTAP11_38
- RADP_DFE_FXTAP11_39
- RADP_DFE_FXTAP1_13
- RADP_DFE_FXTAP11_3
- RADP_DFE_FXTAP11_40
- RADP_DFE_FXTAP11_41
- RADP_DFE_FXTAP11_42
- RADP_DFE_FXTAP11_43
- RADP_DFE_FXTAP11_44
- RADP_DFE_FXTAP11_45
- RADP_DFE_FXTAP11_46
- RADP_DFE_FXTAP11_47
- RADP_DFE_FXTAP11_48
- RADP_DFE_FXTAP11_49
- RADP_DFE_FXTAP1_14
- RADP_DFE_FXTAP11_4
- RADP_DFE_FXTAP11_50
- RADP_DFE_FXTAP11_51
- RADP_DFE_FXTAP11_52
- RADP_DFE_FXTAP11_53
- RADP_DFE_FXTAP11_54
- RADP_DFE_FXTAP11_55
- RADP_DFE_FXTAP11_56
- RADP_DFE_FXTAP11_57
- RADP_DFE_FXTAP11_58
- RADP_DFE_FXTAP11_59
- RADP_DFE_FXTAP1_15
- RADP_DFE_FXTAP11_5
- RADP_DFE_FXTAP11_60
- RADP_DFE_FXTAP11_61
- RADP_DFE_FXTAP11_62
- RADP_DFE_FXTAP11_63
- RADP_DFE_FXTAP1_16
- RADP_DFE_FXTAP11_6
- RADP_DFE_FXTAP1_17
- RADP_DFE_FXTAP11_7
- RADP_DFE_FXTAP1_18
- RADP_DFE_FXTAP11_8
- RADP_DFE_FXTAP1_19
- RADP_DFE_FXTAP11_9
- RADP_DFE_FXTAP1_1
- RADP_DFE_FXTAP11_SGN_0
- RADP_DFE_FXTAP11_SGN_1
- RADP_DFE_FXTAP1_20
- RADP_DFE_FXTAP1_21
- RADP_DFE_FXTAP1_22
- RADP_DFE_FXTAP1_23
- RADP_DFE_FXTAP1_24
- RADP_DFE_FXTAP1_25
- RADP_DFE_FXTAP1_26
- RADP_DFE_FXTAP1_27
- RADP_DFE_FXTAP1_28
- RADP_DFE_FXTAP1_29
- RADP_DFE_FXTAP1_2
- RADP_DFE_FXTAP1_30
- RADP_DFE_FXTAP1_31
- RADP_DFE_FXTAP1_32
- RADP_DFE_FXTAP1_33
- RADP_DFE_FXTAP1_34
- RADP_DFE_FXTAP1_35
- RADP_DFE_FXTAP1_36
- RADP_DFE_FXTAP1_37
- RADP_DFE_FXTAP1_38
- RADP_DFE_FXTAP1_39
- RADP_DFE_FXTAP1_3
- RADP_DFE_FXTAP1_40
- RADP_DFE_FXTAP1_41
- RADP_DFE_FXTAP1_42
- RADP_DFE_FXTAP1_43
- RADP_DFE_FXTAP1_44
- RADP_DFE_FXTAP1_45
- RADP_DFE_FXTAP1_46
- RADP_DFE_FXTAP1_47
- RADP_DFE_FXTAP1_48
- RADP_DFE_FXTAP1_49
- RADP_DFE_FXTAP1_4
- RADP_DFE_FXTAP1_50
- RADP_DFE_FXTAP1_51
- RADP_DFE_FXTAP1_52
- RADP_DFE_FXTAP1_53
- RADP_DFE_FXTAP1_54
- RADP_DFE_FXTAP1_55
- RADP_DFE_FXTAP1_56
- RADP_DFE_FXTAP1_57
- RADP_DFE_FXTAP1_58
- RADP_DFE_FXTAP1_59
- RADP_DFE_FXTAP1_5
- RADP_DFE_FXTAP1_60
- RADP_DFE_FXTAP1_61
- RADP_DFE_FXTAP1_62
- RADP_DFE_FXTAP1_63
- RADP_DFE_FXTAP1_64
- RADP_DFE_FXTAP1_65
- RADP_DFE_FXTAP1_66
- RADP_DFE_FXTAP1_67
- RADP_DFE_FXTAP1_68
- RADP_DFE_FXTAP1_69
- RADP_DFE_FXTAP1_6
- RADP_DFE_FXTAP1_70
- RADP_DFE_FXTAP1_71
- RADP_DFE_FXTAP1_72
- RADP_DFE_FXTAP1_73
- RADP_DFE_FXTAP1_74
- RADP_DFE_FXTAP1_75
- RADP_DFE_FXTAP1_76
- RADP_DFE_FXTAP1_77
- RADP_DFE_FXTAP1_78
- RADP_DFE_FXTAP1_79
- RADP_DFE_FXTAP1_7
- RADP_DFE_FXTAP1_80
- RADP_DFE_FXTAP1_81
- RADP_DFE_FXTAP1_82
- RADP_DFE_FXTAP1_83
- RADP_DFE_FXTAP1_84
- RADP_DFE_FXTAP1_85
- RADP_DFE_FXTAP1_86
- RADP_DFE_FXTAP1_87
- RADP_DFE_FXTAP1_88
- RADP_DFE_FXTAP1_89
- RADP_DFE_FXTAP1_8
- RADP_DFE_FXTAP1_90
- RADP_DFE_FXTAP1_91
- RADP_DFE_FXTAP1_92
- RADP_DFE_FXTAP1_93
- RADP_DFE_FXTAP1_94
- RADP_DFE_FXTAP1_95
- RADP_DFE_FXTAP1_96
- RADP_DFE_FXTAP1_97
- RADP_DFE_FXTAP1_98
- RADP_DFE_FXTAP1_99
- RADP_DFE_FXTAP1_9
- RADP_DFE_FXTAP2_0
- RADP_DFE_FXTAP2_100
- RADP_DFE_FXTAP2_101
- RADP_DFE_FXTAP2_102
- RADP_DFE_FXTAP2_103
- RADP_DFE_FXTAP2_104
- RADP_DFE_FXTAP2_105
- RADP_DFE_FXTAP2_106
- RADP_DFE_FXTAP2_107
- RADP_DFE_FXTAP2_108
- RADP_DFE_FXTAP2_109
- RADP_DFE_FXTAP2_10
- RADP_DFE_FXTAP2_110
- RADP_DFE_FXTAP2_111
- RADP_DFE_FXTAP2_112
- RADP_DFE_FXTAP2_113
- RADP_DFE_FXTAP2_114
- RADP_DFE_FXTAP2_115
- RADP_DFE_FXTAP2_116
- RADP_DFE_FXTAP2_117
- RADP_DFE_FXTAP2_118
- RADP_DFE_FXTAP2_119
- RADP_DFE_FXTAP2_11
- RADP_DFE_FXTAP2_120
- RADP_DFE_FXTAP2_121
- RADP_DFE_FXTAP2_122
- RADP_DFE_FXTAP2_123
- RADP_DFE_FXTAP2_124
- RADP_DFE_FXTAP2_125
- RADP_DFE_FXTAP2_126
- RADP_DFE_FXTAP2_127
- RADP_DFE_FXTAP2_12
- RADP_DFE_FXTAP2_13
- RADP_DFE_FXTAP2_14
- RADP_DFE_FXTAP2_15
- RADP_DFE_FXTAP2_16
- RADP_DFE_FXTAP2_17
- RADP_DFE_FXTAP2_18
- RADP_DFE_FXTAP2_19
- RADP_DFE_FXTAP2_1
- RADP_DFE_FXTAP2_20
- RADP_DFE_FXTAP2_21
- RADP_DFE_FXTAP2_22
- RADP_DFE_FXTAP2_23
- RADP_DFE_FXTAP2_24
- RADP_DFE_FXTAP2_25
- RADP_DFE_FXTAP2_26
- RADP_DFE_FXTAP2_27
- RADP_DFE_FXTAP2_28
- RADP_DFE_FXTAP2_29
- RADP_DFE_FXTAP2_2
- RADP_DFE_FXTAP2_30
- RADP_DFE_FXTAP2_31
- RADP_DFE_FXTAP2_32
- RADP_DFE_FXTAP2_33
- RADP_DFE_FXTAP2_34
- RADP_DFE_FXTAP2_35
- RADP_DFE_FXTAP2_36
- RADP_DFE_FXTAP2_37
- RADP_DFE_FXTAP2_38
- RADP_DFE_FXTAP2_39
- RADP_DFE_FXTAP2_3
- RADP_DFE_FXTAP2_40
- RADP_DFE_FXTAP2_41
- RADP_DFE_FXTAP2_42
- RADP_DFE_FXTAP2_43
- RADP_DFE_FXTAP2_44
- RADP_DFE_FXTAP2_45
- RADP_DFE_FXTAP2_46
- RADP_DFE_FXTAP2_47
- RADP_DFE_FXTAP2_48
- RADP_DFE_FXTAP2_49
- RADP_DFE_FXTAP2_4
- RADP_DFE_FXTAP2_50
- RADP_DFE_FXTAP2_51
- RADP_DFE_FXTAP2_52
- RADP_DFE_FXTAP2_53
- RADP_DFE_FXTAP2_54
- RADP_DFE_FXTAP2_55
- RADP_DFE_FXTAP2_56
- RADP_DFE_FXTAP2_57
- RADP_DFE_FXTAP2_58
- RADP_DFE_FXTAP2_59
- RADP_DFE_FXTAP2_5
- RADP_DFE_FXTAP2_60
- RADP_DFE_FXTAP2_61
- RADP_DFE_FXTAP2_62
- RADP_DFE_FXTAP2_63
- RADP_DFE_FXTAP2_64
- RADP_DFE_FXTAP2_65
- RADP_DFE_FXTAP2_66
- RADP_DFE_FXTAP2_67
- RADP_DFE_FXTAP2_68
- RADP_DFE_FXTAP2_69
- RADP_DFE_FXTAP2_6
- RADP_DFE_FXTAP2_70
- RADP_DFE_FXTAP2_71
- RADP_DFE_FXTAP2_72
- RADP_DFE_FXTAP2_73
- RADP_DFE_FXTAP2_74
- RADP_DFE_FXTAP2_75
- RADP_DFE_FXTAP2_76
- RADP_DFE_FXTAP2_77
- RADP_DFE_FXTAP2_78
- RADP_DFE_FXTAP2_79
- RADP_DFE_FXTAP2_7
- RADP_DFE_FXTAP2_80
- RADP_DFE_FXTAP2_81
- RADP_DFE_FXTAP2_82
- RADP_DFE_FXTAP2_83
- RADP_DFE_FXTAP2_84
- RADP_DFE_FXTAP2_85
- RADP_DFE_FXTAP2_86
- RADP_DFE_FXTAP2_87
- RADP_DFE_FXTAP2_88
- RADP_DFE_FXTAP2_89
- RADP_DFE_FXTAP2_8
- RADP_DFE_FXTAP2_90
- RADP_DFE_FXTAP2_91
- RADP_DFE_FXTAP2_92
- RADP_DFE_FXTAP2_93
- RADP_DFE_FXTAP2_94
- RADP_DFE_FXTAP2_95
- RADP_DFE_FXTAP2_96
- RADP_DFE_FXTAP2_97
- RADP_DFE_FXTAP2_98
- RADP_DFE_FXTAP2_99
- RADP_DFE_FXTAP2_9
- RADP_DFE_FXTAP2_SGN_0
- RADP_DFE_FXTAP2_SGN_1
- RADP_DFE_FXTAP3_0
- RADP_DFE_FXTAP3_100
- RADP_DFE_FXTAP3_101
- RADP_DFE_FXTAP3_102
- RADP_DFE_FXTAP3_103
- RADP_DFE_FXTAP3_104
- RADP_DFE_FXTAP3_105
- RADP_DFE_FXTAP3_106
- RADP_DFE_FXTAP3_107
- RADP_DFE_FXTAP3_108
- RADP_DFE_FXTAP3_109
- RADP_DFE_FXTAP3_10
- RADP_DFE_FXTAP3_110
- RADP_DFE_FXTAP3_111
- RADP_DFE_FXTAP3_112
- RADP_DFE_FXTAP3_113
- RADP_DFE_FXTAP3_114
- RADP_DFE_FXTAP3_115
- RADP_DFE_FXTAP3_116
- RADP_DFE_FXTAP3_117
- RADP_DFE_FXTAP3_118
- RADP_DFE_FXTAP3_119
- RADP_DFE_FXTAP3_11
- RADP_DFE_FXTAP3_120
- RADP_DFE_FXTAP3_121
- RADP_DFE_FXTAP3_122
- RADP_DFE_FXTAP3_123
- RADP_DFE_FXTAP3_124
- RADP_DFE_FXTAP3_125
- RADP_DFE_FXTAP3_126
- RADP_DFE_FXTAP3_127
- RADP_DFE_FXTAP3_12
- RADP_DFE_FXTAP3_13
- RADP_DFE_FXTAP3_14
- RADP_DFE_FXTAP3_15
- RADP_DFE_FXTAP3_16
- RADP_DFE_FXTAP3_17
- RADP_DFE_FXTAP3_18
- RADP_DFE_FXTAP3_19
- RADP_DFE_FXTAP3_1
- RADP_DFE_FXTAP3_20
- RADP_DFE_FXTAP3_21
- RADP_DFE_FXTAP3_22
- RADP_DFE_FXTAP3_23
- RADP_DFE_FXTAP3_24
- RADP_DFE_FXTAP3_25
- RADP_DFE_FXTAP3_26
- RADP_DFE_FXTAP3_27
- RADP_DFE_FXTAP3_28
- RADP_DFE_FXTAP3_29
- RADP_DFE_FXTAP3_2
- RADP_DFE_FXTAP3_30
- RADP_DFE_FXTAP3_31
- RADP_DFE_FXTAP3_32
- RADP_DFE_FXTAP3_33
- RADP_DFE_FXTAP3_34
- RADP_DFE_FXTAP3_35
- RADP_DFE_FXTAP3_36
- RADP_DFE_FXTAP3_37
- RADP_DFE_FXTAP3_38
- RADP_DFE_FXTAP3_39
- RADP_DFE_FXTAP3_3
- RADP_DFE_FXTAP3_40
- RADP_DFE_FXTAP3_41
- RADP_DFE_FXTAP3_42
- RADP_DFE_FXTAP3_43
- RADP_DFE_FXTAP3_44
- RADP_DFE_FXTAP3_45
- RADP_DFE_FXTAP3_46
- RADP_DFE_FXTAP3_47
- RADP_DFE_FXTAP3_48
- RADP_DFE_FXTAP3_49
- RADP_DFE_FXTAP3_4
- RADP_DFE_FXTAP3_50
- RADP_DFE_FXTAP3_51
- RADP_DFE_FXTAP3_52
- RADP_DFE_FXTAP3_53
- RADP_DFE_FXTAP3_54
- RADP_DFE_FXTAP3_55
- RADP_DFE_FXTAP3_56
- RADP_DFE_FXTAP3_57
- RADP_DFE_FXTAP3_58
- RADP_DFE_FXTAP3_59
- RADP_DFE_FXTAP3_5
- RADP_DFE_FXTAP3_60
- RADP_DFE_FXTAP3_61
- RADP_DFE_FXTAP3_62
- RADP_DFE_FXTAP3_63
- RADP_DFE_FXTAP3_64
- RADP_DFE_FXTAP3_65
- RADP_DFE_FXTAP3_66
- RADP_DFE_FXTAP3_67
- RADP_DFE_FXTAP3_68
- RADP_DFE_FXTAP3_69
- RADP_DFE_FXTAP3_6
- RADP_DFE_FXTAP3_70
- RADP_DFE_FXTAP3_71
- RADP_DFE_FXTAP3_72
- RADP_DFE_FXTAP3_73
- RADP_DFE_FXTAP3_74
- RADP_DFE_FXTAP3_75
- RADP_DFE_FXTAP3_76
- RADP_DFE_FXTAP3_77
- RADP_DFE_FXTAP3_78
- RADP_DFE_FXTAP3_79
- RADP_DFE_FXTAP3_7
- RADP_DFE_FXTAP3_80
- RADP_DFE_FXTAP3_81
- RADP_DFE_FXTAP3_82
- RADP_DFE_FXTAP3_83
- RADP_DFE_FXTAP3_84
- RADP_DFE_FXTAP3_85
- RADP_DFE_FXTAP3_86
- RADP_DFE_FXTAP3_87
- RADP_DFE_FXTAP3_88
- RADP_DFE_FXTAP3_89
- RADP_DFE_FXTAP3_8
- RADP_DFE_FXTAP3_90
- RADP_DFE_FXTAP3_91
- RADP_DFE_FXTAP3_92
- RADP_DFE_FXTAP3_93
- RADP_DFE_FXTAP3_94
- RADP_DFE_FXTAP3_95
- RADP_DFE_FXTAP3_96
- RADP_DFE_FXTAP3_97
- RADP_DFE_FXTAP3_98
- RADP_DFE_FXTAP3_99
- RADP_DFE_FXTAP3_9
- RADP_DFE_FXTAP3_SGN_0
- RADP_DFE_FXTAP3_SGN_1
- RADP_DFE_FXTAP4_0
- RADP_DFE_FXTAP4_10
- RADP_DFE_FXTAP4_11
- RADP_DFE_FXTAP4_12
- RADP_DFE_FXTAP4_13
- RADP_DFE_FXTAP4_14
- RADP_DFE_FXTAP4_15
- RADP_DFE_FXTAP4_16
- RADP_DFE_FXTAP4_17
- RADP_DFE_FXTAP4_18
- RADP_DFE_FXTAP4_19
- RADP_DFE_FXTAP4_1
- RADP_DFE_FXTAP4_20
- RADP_DFE_FXTAP4_21
- RADP_DFE_FXTAP4_22
- RADP_DFE_FXTAP4_23
- RADP_DFE_FXTAP4_24
- RADP_DFE_FXTAP4_25
- RADP_DFE_FXTAP4_26
- RADP_DFE_FXTAP4_27
- RADP_DFE_FXTAP4_28
- RADP_DFE_FXTAP4_29
- RADP_DFE_FXTAP4_2
- RADP_DFE_FXTAP4_30
- RADP_DFE_FXTAP4_31
- RADP_DFE_FXTAP4_32
- RADP_DFE_FXTAP4_33
- RADP_DFE_FXTAP4_34
- RADP_DFE_FXTAP4_35
- RADP_DFE_FXTAP4_36
- RADP_DFE_FXTAP4_37
- RADP_DFE_FXTAP4_38
- RADP_DFE_FXTAP4_39
- RADP_DFE_FXTAP4_3
- RADP_DFE_FXTAP4_40
- RADP_DFE_FXTAP4_41
- RADP_DFE_FXTAP4_42
- RADP_DFE_FXTAP4_43
- RADP_DFE_FXTAP4_44
- RADP_DFE_FXTAP4_45
- RADP_DFE_FXTAP4_46
- RADP_DFE_FXTAP4_47
- RADP_DFE_FXTAP4_48
- RADP_DFE_FXTAP4_49
- RADP_DFE_FXTAP4_4
- RADP_DFE_FXTAP4_50
- RADP_DFE_FXTAP4_51
- RADP_DFE_FXTAP4_52
- RADP_DFE_FXTAP4_53
- RADP_DFE_FXTAP4_54
- RADP_DFE_FXTAP4_55
- RADP_DFE_FXTAP4_56
- RADP_DFE_FXTAP4_57
- RADP_DFE_FXTAP4_58
- RADP_DFE_FXTAP4_59
- RADP_DFE_FXTAP4_5
- RADP_DFE_FXTAP4_60
- RADP_DFE_FXTAP4_61
- RADP_DFE_FXTAP4_62
- RADP_DFE_FXTAP4_63
- RADP_DFE_FXTAP4_6
- RADP_DFE_FXTAP4_7
- RADP_DFE_FXTAP4_8
- RADP_DFE_FXTAP4_9
- RADP_DFE_FXTAP4_SGN_0
- RADP_DFE_FXTAP4_SGN_1
- RADP_DFE_FXTAP5_0
- RADP_DFE_FXTAP5_10
- RADP_DFE_FXTAP5_11
- RADP_DFE_FXTAP5_12
- RADP_DFE_FXTAP5_13
- RADP_DFE_FXTAP5_14
- RADP_DFE_FXTAP5_15
- RADP_DFE_FXTAP5_16
- RADP_DFE_FXTAP5_17
- RADP_DFE_FXTAP5_18
- RADP_DFE_FXTAP5_19
- RADP_DFE_FXTAP5_1
- RADP_DFE_FXTAP5_20
- RADP_DFE_FXTAP5_21
- RADP_DFE_FXTAP5_22
- RADP_DFE_FXTAP5_23
- RADP_DFE_FXTAP5_24
- RADP_DFE_FXTAP5_25
- RADP_DFE_FXTAP5_26
- RADP_DFE_FXTAP5_27
- RADP_DFE_FXTAP5_28
- RADP_DFE_FXTAP5_29
- RADP_DFE_FXTAP5_2
- RADP_DFE_FXTAP5_30
- RADP_DFE_FXTAP5_31
- RADP_DFE_FXTAP5_32
- RADP_DFE_FXTAP5_33
- RADP_DFE_FXTAP5_34
- RADP_DFE_FXTAP5_35
- RADP_DFE_FXTAP5_36
- RADP_DFE_FXTAP5_37
- RADP_DFE_FXTAP5_38
- RADP_DFE_FXTAP5_39
- RADP_DFE_FXTAP5_3
- RADP_DFE_FXTAP5_40
- RADP_DFE_FXTAP5_41
- RADP_DFE_FXTAP5_42
- RADP_DFE_FXTAP5_43
- RADP_DFE_FXTAP5_44
- RADP_DFE_FXTAP5_45
- RADP_DFE_FXTAP5_46
- RADP_DFE_FXTAP5_47
- RADP_DFE_FXTAP5_48
- RADP_DFE_FXTAP5_49
- RADP_DFE_FXTAP5_4
- RADP_DFE_FXTAP5_50
- RADP_DFE_FXTAP5_51
- RADP_DFE_FXTAP5_52
- RADP_DFE_FXTAP5_53
- RADP_DFE_FXTAP5_54
- RADP_DFE_FXTAP5_55
- RADP_DFE_FXTAP5_56
- RADP_DFE_FXTAP5_57
- RADP_DFE_FXTAP5_58
- RADP_DFE_FXTAP5_59
- RADP_DFE_FXTAP5_5
- RADP_DFE_FXTAP5_60
- RADP_DFE_FXTAP5_61
- RADP_DFE_FXTAP5_62
- RADP_DFE_FXTAP5_63
- RADP_DFE_FXTAP5_6
- RADP_DFE_FXTAP5_7
- RADP_DFE_FXTAP5_8
- RADP_DFE_FXTAP5_9
- RADP_DFE_FXTAP5_SGN_0
- RADP_DFE_FXTAP5_SGN_1
- RADP_DFE_FXTAP6_0
- RADP_DFE_FXTAP6_10
- RADP_DFE_FXTAP6_11
- RADP_DFE_FXTAP6_12
- RADP_DFE_FXTAP6_13
- RADP_DFE_FXTAP6_14
- RADP_DFE_FXTAP6_15
- RADP_DFE_FXTAP6_16
- RADP_DFE_FXTAP6_17
- RADP_DFE_FXTAP6_18
- RADP_DFE_FXTAP6_19
- RADP_DFE_FXTAP6_1
- RADP_DFE_FXTAP6_20
- RADP_DFE_FXTAP6_21
- RADP_DFE_FXTAP6_22
- RADP_DFE_FXTAP6_23
- RADP_DFE_FXTAP6_24
- RADP_DFE_FXTAP6_25
- RADP_DFE_FXTAP6_26
- RADP_DFE_FXTAP6_27
- RADP_DFE_FXTAP6_28
- RADP_DFE_FXTAP6_29
- RADP_DFE_FXTAP6_2
- RADP_DFE_FXTAP6_30
- RADP_DFE_FXTAP6_31
- RADP_DFE_FXTAP6_3
- RADP_DFE_FXTAP6_4
- RADP_DFE_FXTAP6_5
- RADP_DFE_FXTAP6_6
- RADP_DFE_FXTAP6_7
- RADP_DFE_FXTAP6_8
- RADP_DFE_FXTAP6_9
- RADP_DFE_FXTAP6_SGN_0
- RADP_DFE_FXTAP6_SGN_1
- RADP_DFE_FXTAP7_0
- RADP_DFE_FXTAP7_10
- RADP_DFE_FXTAP7_11
- RADP_DFE_FXTAP7_12
- RADP_DFE_FXTAP7_13
- RADP_DFE_FXTAP7_14
- RADP_DFE_FXTAP7_15
- RADP_DFE_FXTAP7_16
- RADP_DFE_FXTAP7_17
- RADP_DFE_FXTAP7_18
- RADP_DFE_FXTAP7_19
- RADP_DFE_FXTAP7_1
- RADP_DFE_FXTAP7_20
- RADP_DFE_FXTAP7_21
- RADP_DFE_FXTAP7_22
- RADP_DFE_FXTAP7_23
- RADP_DFE_FXTAP7_24
- RADP_DFE_FXTAP7_25
- RADP_DFE_FXTAP7_26
- RADP_DFE_FXTAP7_27
- RADP_DFE_FXTAP7_28
- RADP_DFE_FXTAP7_29
- RADP_DFE_FXTAP7_2
- RADP_DFE_FXTAP7_30
- RADP_DFE_FXTAP7_31
- RADP_DFE_FXTAP7_3
- RADP_DFE_FXTAP7_4
- RADP_DFE_FXTAP7_5
- RADP_DFE_FXTAP7_6
- RADP_DFE_FXTAP7_7
- RADP_DFE_FXTAP7_8
- RADP_DFE_FXTAP7_9
- RADP_DFE_FXTAP7_SGN_0
- RADP_DFE_FXTAP7_SGN_1
- RADP_DFE_FXTAP8_0
- RADP_DFE_FXTAP8_10
- RADP_DFE_FXTAP8_11
- RADP_DFE_FXTAP8_12
- RADP_DFE_FXTAP8_13
- RADP_DFE_FXTAP8_14
- RADP_DFE_FXTAP8_15
- RADP_DFE_FXTAP8_16
- RADP_DFE_FXTAP8_17
- RADP_DFE_FXTAP8_18
- RADP_DFE_FXTAP8_19
- RADP_DFE_FXTAP8_1
- RADP_DFE_FXTAP8_20
- RADP_DFE_FXTAP8_21
- RADP_DFE_FXTAP8_22
- RADP_DFE_FXTAP8_23
- RADP_DFE_FXTAP8_24
- RADP_DFE_FXTAP8_25
- RADP_DFE_FXTAP8_26
- RADP_DFE_FXTAP8_27
- RADP_DFE_FXTAP8_28
- RADP_DFE_FXTAP8_29
- RADP_DFE_FXTAP8_2
- RADP_DFE_FXTAP8_30
- RADP_DFE_FXTAP8_31
- RADP_DFE_FXTAP8_32
- RADP_DFE_FXTAP8_33
- RADP_DFE_FXTAP8_34
- RADP_DFE_FXTAP8_35
- RADP_DFE_FXTAP8_36
- RADP_DFE_FXTAP8_37
- RADP_DFE_FXTAP8_38
- RADP_DFE_FXTAP8_39
- RADP_DFE_FXTAP8_3
- RADP_DFE_FXTAP8_40
- RADP_DFE_FXTAP8_41
- RADP_DFE_FXTAP8_42
- RADP_DFE_FXTAP8_43
- RADP_DFE_FXTAP8_44
- RADP_DFE_FXTAP8_45
- RADP_DFE_FXTAP8_46
- RADP_DFE_FXTAP8_47
- RADP_DFE_FXTAP8_48
- RADP_DFE_FXTAP8_49
- RADP_DFE_FXTAP8_4
- RADP_DFE_FXTAP8_50
- RADP_DFE_FXTAP8_51
- RADP_DFE_FXTAP8_52
- RADP_DFE_FXTAP8_53
- RADP_DFE_FXTAP8_54
- RADP_DFE_FXTAP8_55
- RADP_DFE_FXTAP8_56
- RADP_DFE_FXTAP8_57
- RADP_DFE_FXTAP8_58
- RADP_DFE_FXTAP8_59
- RADP_DFE_FXTAP8_5
- RADP_DFE_FXTAP8_60
- RADP_DFE_FXTAP8_61
- RADP_DFE_FXTAP8_62
- RADP_DFE_FXTAP8_63
- RADP_DFE_FXTAP8_6
- RADP_DFE_FXTAP8_7
- RADP_DFE_FXTAP8_8
- RADP_DFE_FXTAP8_9
- RADP_DFE_FXTAP8_SGN_0
- RADP_DFE_FXTAP8_SGN_1
- RADP_DFE_FXTAP9_0
- RADP_DFE_FXTAP9_10
- RADP_DFE_FXTAP9_11
- RADP_DFE_FXTAP9_12
- RADP_DFE_FXTAP9_13
- RADP_DFE_FXTAP9_14
- RADP_DFE_FXTAP9_15
- RADP_DFE_FXTAP9_16
- RADP_DFE_FXTAP9_17
- RADP_DFE_FXTAP9_18
- RADP_DFE_FXTAP9_19
- RADP_DFE_FXTAP9_1
- RADP_DFE_FXTAP9_20
- RADP_DFE_FXTAP9_21
- RADP_DFE_FXTAP9_22
- RADP_DFE_FXTAP9_23
- RADP_DFE_FXTAP9_24
- RADP_DFE_FXTAP9_25
- RADP_DFE_FXTAP9_26
- RADP_DFE_FXTAP9_27
- RADP_DFE_FXTAP9_28
- RADP_DFE_FXTAP9_29
- RADP_DFE_FXTAP9_2
- RADP_DFE_FXTAP9_30
- RADP_DFE_FXTAP9_31
- RADP_DFE_FXTAP9_32
- RADP_DFE_FXTAP9_33
- RADP_DFE_FXTAP9_34
- RADP_DFE_FXTAP9_35
- RADP_DFE_FXTAP9_36
- RADP_DFE_FXTAP9_37
- RADP_DFE_FXTAP9_38
- RADP_DFE_FXTAP9_39
- RADP_DFE_FXTAP9_3
- RADP_DFE_FXTAP9_40
- RADP_DFE_FXTAP9_41
- RADP_DFE_FXTAP9_42
- RADP_DFE_FXTAP9_43
- RADP_DFE_FXTAP9_44
- RADP_DFE_FXTAP9_45
- RADP_DFE_FXTAP9_46
- RADP_DFE_FXTAP9_47
- RADP_DFE_FXTAP9_48
- RADP_DFE_FXTAP9_49
- RADP_DFE_FXTAP9_4
- RADP_DFE_FXTAP9_50
- RADP_DFE_FXTAP9_51
- RADP_DFE_FXTAP9_52
- RADP_DFE_FXTAP9_53
- RADP_DFE_FXTAP9_54
- RADP_DFE_FXTAP9_55
- RADP_DFE_FXTAP9_56
- RADP_DFE_FXTAP9_57
- RADP_DFE_FXTAP9_58
- RADP_DFE_FXTAP9_59
- RADP_DFE_FXTAP9_5
- RADP_DFE_FXTAP9_60
- RADP_DFE_FXTAP9_61
- RADP_DFE_FXTAP9_62
- RADP_DFE_FXTAP9_63
- RADP_DFE_FXTAP9_6
- RADP_DFE_FXTAP9_7
- RADP_DFE_FXTAP9_8
- RADP_DFE_FXTAP9_9
- RADP_DFE_FXTAP9_SGN_0
- RADP_DFE_FXTAP9_SGN_1
- RADP_LFEQ_FB_SEL_0
- RADP_LFEQ_FB_SEL_1
- RADP_LFEQ_FB_SEL_2
- RADP_LFEQ_FB_SEL_3
- RADP_LFEQ_FB_SEL_4
- RADP_LFEQ_FB_SEL_5
- RADP_LFEQ_FB_SEL_6
- RADP_LFEQ_FB_SEL_7
- RADP_ONETIME_DFE_0
- RADP_ONETIME_DFE_1
- RADP_VGA_SEL_0
- RADP_VGA_SEL_1
- RADP_VGA_SEL_2
- RADP_VGA_SEL_3
- RADP_VGA_SEL_4
- RADP_VGA_SEL_5
- RADP_VGA_SEL_6
- RADP_VGA_SEL_7
- RADP_VREF_SEL_0
- RADP_VREF_SEL_10
- RADP_VREF_SEL_11
- RADP_VREF_SEL_12
- RADP_VREF_SEL_13
- RADP_VREF_SEL_14
- RADP_VREF_SEL_15
- RADP_VREF_SEL_16
- RADP_VREF_SEL_17
- RADP_VREF_SEL_18
- RADP_VREF_SEL_19
- RADP_VREF_SEL_1
- RADP_VREF_SEL_20
- RADP_VREF_SEL_21
- RADP_VREF_SEL_22
- RADP_VREF_SEL_23
- RADP_VREF_SEL_24
- RADP_VREF_SEL_25
- RADP_VREF_SEL_26
- RADP_VREF_SEL_27
- RADP_VREF_SEL_28
- RADP_VREF_SEL_29
- RADP_VREF_SEL_2
- RADP_VREF_SEL_30
- RADP_VREF_SEL_31
- RADP_VREF_SEL_3
- RADP_VREF_SEL_4
- RADP_VREF_SEL_5
- RADP_VREF_SEL_6
- RADP_VREF_SEL_7
- RADP_VREF_SEL_8
- RADP_VREF_SEL_9
- RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
- RAM_CTL
- RAM_REGISTER_DUPLICATION
- RAMSTYLE_ATTRIBUTE
- RAM_USE_DCD
- RANDOM
- RANDOM_PIN
- RANDOM_PIN_SEED
- RAPID_RECOMPILE_ASSIGNMENT_CHECKING
- RAPID_RECOMPILE_MODE
- RAPID_RECOMPILE_SYNTHESIS_MODE
- RAW_BINARY_FILE
- RBCGEN_CRITICAL_WARNING_TO_ERROR
- RBF_FILE_GENERATION_FOR_SUPR
- RDYNBUSY_RESERVED
- READ
- READ_OR_WRITE_IN_BYTE_ADDRESS
- REALISTIC
- RECOMMENDED
- RECOMPILE_QUESTION
- RECONFIGURABLE
- RECONFIGURABLE_REVISION
- REFCLK_COUNTER_OUT
- REFCLK_COUPLING_OCT
- REGENERATE_IP_IF_HDL_QSYS_MISMATCH
- REGIONAL_CLOCK
- REGION_NAME
- REGISTER_LOCATION_TYPE
- REGISTER_PACKING_ARMSTRONG
- REGISTER_PACKING
- REGISTER_PACKING_TSUNAMI
- REGISTERS_ONLY
- RELATIVE_NEUTRON_FLUX
- RELEASE_CLEARS_BEFORE_TRI
- RELEASE_CLEARS_BEFORE_TRI_STATES
- REMOTE
- REMOVE_DUPLICATE_LOGIC
- REMOVE_DUPLICATE_REGISTERS
- REMOVE_FANOUT_FREE_REGISTERS
- REMOVE
- REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS
- REMOVE_REDUNDANT_LOGIC_CELLS
- REMOVE_REDUNDANT_USER_CELLS
- REPLACE_CONFLICTING
- REPORT_AS_DQS
- REPORT_CONNECTIVITY_CHECKS
- REPORT_DELAY
- REPORT_IO_PATHS_SEPARATELY
- REPORT_PARAMETER_SETTINGS
- REPORT_PARAMETER_SETTINGS_PRO
- REPORT_PR_INITIAL_VALUES_AS_ERROR
- REPORT_SOURCE_ASSIGNMENTS
- REPORT_SOURCE_ASSIGNMENTS_PRO
- REQUIRED_DUTY_CYCLE
- REQUIRED_FMAX
- RESERVE_ALL_UNUSED_PINS
- RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND
- RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP
- RESERVE_ASDO_AFTER_CONFIGURATION
- RESERVE_AVST_CLK_AFTER_CONFIGURATION
- RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION
- RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
- RESERVE_AVST_VALID_AFTER_CONFIGURATION
- RESERVED1
- RESERVED2
- RESERVED3
- RESERVED_ALL_UNUSED_PINS
- RESERVED_ALL_UNUSED_PINS_NO_OUTPUT_GND
- RESERVE_DATA0_AFTER_CONFIGURATION
- RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION
- RESERVE_DATA1_AFTER_CONFIGURATION
- RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
- RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION
- RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION
- RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION
- RESERVE_DCLK_AFTER_CONFIGURATION
- RESERVED_CORE
- RESERVED
- RESERVED_PIN
- RESERVE_FLASH_NCE_AFTER_CONFIGURATION
- RESERVE_FLEXIBLE_CLOCK_NETWORK
- RESERVE_NCEO_AFTER_CONFIGURATION
- RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION
- RESERVE_OTHER_APF_PINS_AFTER_CONFIGURATION
- RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION
- RESERVE_PIN
- RESERVE_PLACE_REGION
- RESERVE_PR_PINS
- RESERVE_RDYNBUSY_AFTER_CONFIGURATION
- RESERVE_ROUTE_REGION
- RESERVE_ROUTING_OUTPUT_FLEXIBILITY
- RESERVE_SDO_AFTER_CONFIGURATION
- RESET_CAT
- RESET_RULE_ALL
- RESET_RULE_COMB_ASYNCH_RESET
- RESET_RULE_IMSYNCH_ASYNCH_DOMAIN
- RESET_RULE_IMSYNCH_EXRESET
- RESET_RULE_INPINS_RESETNET
- RESET_RULE_REG_ASNYCH
- RESET_RULE_UNSYNCH_ASYNCH_DOMAIN
- RESET_RULE_UNSYNCH_EXRESET
- RESOLVE_FILENAME
- RESOURCE_ALLOCATION
- RESYNTHESIS_EXTRA_DEBUGGING_INFORMATION
- RESYNTHESIS_OPTIMIZATION_EFFORT
- RESYNTHESIS_PHYSICAL_SYNTHESIS
- RESYNTHESIS_RETIMING
- RETAIN_COMB_LOGIC_OUTSIDE_CLOUD
- RETIMER_ASSIGNMENT
- RETIMER_FAST_FORWARD_ASSIGNMENT
- REVISION_BASED_FILE_NAME
- REVISION_CONTROL_DIR
- REVISION_CONTROL_SYSTEM
- REVISION_CONTROL_TCL
- REVISION_CONTROL_TCL_SCRIPT
- REVISION_TYPE
- R_EXT0
- RISE
- ROOT
- ROUTER_CLOCKING_TOPOLOGY_ANALYSIS
- ROUTER_EFFORT_MULTIPLIER
- ROUTE_REGION
- ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION
- ROUTER_REGISTER_DUPLICATION
- ROUTER_TIMING_OPTIMIZATION_LEVEL
- ROUTING_BACK_ANNOTATE
- ROUTING_BACK_ANNOTATION_FILE
- ROUTING_BACK_ANNOTATION_MODE
- ROW_GLOBAL
- ROW_GLOBAL_SIGNAL
- R_R1
- R_R2
- RR_HYBRID
- RTERM_CODE0
- RTERM_CODE10
- RTERM_CODE11
- RTERM_CODE12
- RTERM_CODE13
- RTERM_CODE14
- RTERM_CODE15
- RTERM_CODE1
- RTERM_CODE2
- RTERM_CODE3
- RTERM_CODE4
- RTERM_CODE5
- RTERM_CODE6
- RTERM_CODE7
- RTERM_CODE8
- RTERM_CODE9
- RTLV_GROUP_COMB_LOGIC_IN_CLOUD
- RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV
- RTLV_GROUP_RELATED_NODES
- RTLV_GROUP_RELATED_NODES_TMV
- RTLV_PRESERVED_HANGING_NODES
- RTLV_REMOVE_FANOUT_FREE_REGISTERS
- RTLV_RETAIN_COMB_LOGIC_OUTSIDE_CLOUD
- RTLV_SIMPLIFIED_LOGIC
- RUN_ALL_TIMING_ANALYSES
- RUN_CLOCK_TAN
- RUN_COMPARISON_ON_EVERY_COMPILE
- RUN_DRC_DURING_COMPILATION
- RUN_FITTER_IN_SIGNALPROBE_MODE
- RUN_FULL_COMPILE_ON_DEVICE_CHANGE
- RUN_P2P_TAN
- RUN_TAN
- RUN_TIMING_ANALYSES
- RUN_TIMING_ANALYSES_ONLY_FOR_TIMING_ASSIGNMENTS
- RX_DET_OFF
- RX_DET_ON
- RX_DET_PCIE_OUT
- RX_DET_QPI_OUT
- RZQ_GROUP
- S0H9
- S1_MODE
- SAFE_STATE_MACHINE
- SAME_AS_MULTICYCLE
- SAMPLE_AND_SUSTAIN
- SAP_NAME
- SATA1_I
- SATA1_M
- SATA1_X
- SATA2_I
- SATA2_M
- SATA2_X
- SAVE_DISK_SPACE
- SAVE_INTERMEDIATE_FITTING_RESULTS
- SAVE_MIGRATION_INFO_DURING_COMPILATION
- SBI_FILE
- SCE_PIN
- SDC_ENTITY_FILE
- SDC_ENTITY_HELPER_FILE
- SDC_FILE
- SDC_STATEMENT
- SDC_UNIQUIFIED_STATEMENT
- SDF_OUTPUT_FILE
- SDI_1485_HD
- SDI_270_SD
- SDI_2970_3G
- SDLV_0
- SDLV_10
- SDLV_11
- SDLV_12
- SDLV_13
- SDLV_14
- SDLV_15
- SDLV_1
- SDLV_2
- SDLV_3
- SDLV_4
- SDLV_5
- SDLV_6
- SDLV_7
- SDLV_8
- SDLV_9
- SDM_DIRECT_TO_FACTORY_IMAGE
- SDM_PCIE_CALIB_START
- SDM_PINS
- SDO_PIN
- SDO_RESERVED
- SEARCH_PATH
- SECTION_COLUMN
- SECTION
- SECURITY_BIT
- SEED
- SELECTED_EDGE
- SEQUENTIAL
- SERIAL_BITSTREAM_FILE
- SERIAL_LITE_III_16400
- SERIAL_LITE_III_17400
- SERIAL_VECTOR_FILE
- SERIES_25_OHMS
- SERIES_25_OHMS_WITH_CALIBRATION
- SERIES_25_OHMS_WITHOUT_CALIBRATION
- SERIES_50_OHMS
- SERIES_50_OHMS_WITH_CALIBRATION
- SERIES_50_OHMS_WITHOUT_CALIBRATION
- SERIES
- SET_PULSE_WIDTH
- SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
- SETUP_HOLD_DETECTION
- SETUP_HOLD_TIME_VIOLATION_DETECTION
- SETUP_RELATIONSHIP
- SEU_FIT_REPORT
- SFCU
- SFI_S_6250
- SFIS
- SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL
- SHOW_ALL_TAN_PANELS
- SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT
- SHOW_REGISTRATION_MESSAGE
- SHOW_TIMING_MODEL_CHANGE_MESSAGE
- SIGNAL_INTEGRITY_ASSIGNMENT
- SIGNAL_INTEGRITY_WILDCARDS
- SIGNALPROBE_ALLOW_OVERUSE
- SIGNALPROBE_ASSIGNMENT
- SIGNALPROBE_CLOCK
- SIGNALPROBE_DURING_NORMAL_COMPILATION
- SIGNAL_PROBE_ENABLE
- SIGNALPROBE_ENABLE
- SIGNALPROBE
- SIGNALPROBE_NUM_REGISTERS
- SIGNAL_PROBE_SOURCE
- SIGNALPROBE_SOURCE
- SIGNALRACE_CAT
- SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN
- SIGNALRACE_RULE_CLK_PORT_RACE
- SIGNALRACE_RULE_RESET_RACE
- SIGNALRACE_RULE_SECOND_SIGNAL_RACE
- SIGNALRACE_RULE_TRISTATE
- SIGNALTAP_ASSIGNMENTS
- SIGNALTAP_FILE
- SIGNALTAP
- SIGNALTAP_LOGIC_ANALYZER_PROJECT_FILES
- SIGNALTAP_LOGIC_ANALYZER_SETTINGS
- SIM_AUTO_USE_GLITCH_FILTERING
- SIM_BEHAVIOR_SIMULATION
- SIM_BUS_CHANNEL_GROUPING
- SIM_CELL_DELAY_MODEL_TYPE
- SIM_COMPARE_SIGNAL
- SIM_COMPILE_HDL_FILES
- SIM_DEFAULT_VECTOR_COMPARE_TOLERANCE
- SIM_DELAY_MODEL_TYPE
- SIM_ENABLE_SIMULATION_NETLIST_VIEWER
- SIMGEN_ARBITRARY_BLACKBOX
- SIMGEN_BLACKBOX_FILE
- SIMGEN_PARAMETER
- SIM_HDL_TOP_MODULE_NAME
- SIM_INTERCONNECT_DELAY_MODEL_TYPE
- SIM_NO_DELAYS
- SIM_OUTPUT_POWERPLAY_VCD
- SIM_OUTPUT_POWERPLAY_VCD_NAME
- SIM_OUTPUT_SAF
- SIM_OUTPUT_SAF_NAME
- SIM_OVERWRITE_WAVEFORM_INPUTS
- SIMPLE_18_BIT_MULTIPLIERS
- SIMPLE_MULTIPLIERS
- SIMPLE_MULT
- SIMPLE_MULT_UPGRADE_WIDTH
- SIMPLIFIED_LOGIC
- SIM_POWERPLAY_VCD_END_TIME
- SIM_POWERPLAY_VCD_START_TIME
- SIM_PVT_TIMING_MODEL_TYPE
- SIM_SET_NO_DELAYS_VIRTUAL_IO
- SIM_SIGNAL_ACTIVITY_END_TIME
- SIM_SIGNAL_ACTIVITY_START_TIME
- SIM_SIGNAL_COMPARE_TOLERANCE
- SIM_SIGNAL_TRIGGER_VECTOR_COMPARE
- SIM_SIMULATION_DEBUGGER
- SIM_TAP_REGISTER_D_Q_PORTS
- SIMULATION_ASSIGNMENT
- SIMULATION_BUS_CHANNEL_GROUPING
- SIMULATION_CELL_DELAY_MODEL_TYPE
- SIMULATION_COMPARE_SIGNAL
- SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL
- SIMULATION_COVERAGE
- SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE
- SIMULATION_DELAY_MODEL_TYPE
- SIMULATION_INCREMENTAL_TIME_INPUT
- SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE
- SIMULATION
- SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL
- SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL
- SIMULATION_MODE
- SIMULATION_NETLIST_VIEWER
- SIMULATION_SIGNAL_COMPARE_TOLERANCE
- SIMULATION_TYPE
- SIMULATION_VDB_RESULT_FLUSH
- SIMULATION_VECTOR_COMPARE_BEGIN_TIME
- SIMULATION_VECTOR_COMPARE_END_TIME
- SIMULATION_VECTOR_COMPARE_RULE_FOR_0
- SIMULATION_VECTOR_COMPARE_RULE_FOR_1
- SIMULATION_VECTOR_COMPARE_RULE_FOR_DC
- SIMULATION_VECTOR_COMPARE_RULE_FOR_H
- SIMULATION_VECTOR_COMPARE_RULE_FOR_L
- SIMULATION_VECTOR_COMPARE_RULE_FOR_U
- SIMULATION_VECTOR_COMPARE_RULE_FOR_W
- SIMULATION_VECTOR_COMPARE_RULE_FOR_X
- SIMULATION_VECTOR_COMPARE_RULE_FOR_Z
- SIMULATION_WITH_AUTO_GLITCH_FILTERING
- SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW
- SIMULATION_WITH_GLITCH_FILTERING
- SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF
- SIMULATOR_ACTION_POINTS
- SIMULATOR_GENERATE_POWERPLAY_VCD_FILE
- SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE
- SIMULATOR_POWERPLAY_VCD_FILE_END_TIME
- SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION
- SIMULATOR_POWERPLAY_VCD_FILE_START_TIME
- SIMULATOR_PVT_TIMING_MODEL_TYPE
- SIMULATOR_SETTINGS
- SIMULATOR_SETTINGS_LIST
- SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME
- SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION
- SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME
- SIMULATOR_TCL_SCRIPT_FILE
- SIM_USE_FAST_TIMING_MODEL
- SIM_USE_GLITCH_FILTERING
- SIM_USE_GLITCH_FILTERING_WHEN_GENERATING_SAF
- SIM_USE_PDB_NETLIST
- SIM_VDB_RESULT_FLUSH
- SIM_VECTOR_COMPARE_BEGIN_TIME
- SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE
- SIM_VECTOR_COMPARED_CLOCK_OFFSET
- SIM_VECTOR_COMPARED_CLOCK_PERIOD
- SIM_VECTOR_COMPARE_END_TIME
- SIM_VECTOR_COMPARE_RULE_FOR_0
- SIM_VECTOR_COMPARE_RULE_FOR_1
- SIM_VECTOR_COMPARE_RULE_FOR_DC
- SIM_VECTOR_COMPARE_RULE_FOR_H
- SIM_VECTOR_COMPARE_RULE_FOR_L
- SIM_VECTOR_COMPARE_RULE_FOR_U
- SIM_VECTOR_COMPARE_RULE_FOR_W
- SIM_VECTOR_COMPARE_RULE_FOR_X
- SIM_VECTOR_COMPARE_RULE_FOR_Z
- SIM_VECTOR_COMPARE_TRIGGER_CLOCK
- SIM_VECTOR_COMPARE_TRIGGER_MODE
- SIM_VECTOR_COMPARE_TRIGGER_SIGNAL
- SIM_VECTOR_OUTPUT_FILE
- SIM_VECTOR_OUTPUT_FORMAT
- SINGLE_COMP_IMAGE
- SINGLE_COMP_IMAGE_WITH_ERAM
- SINGLE_IMAGE
- SINGLE_IMAGE_WITH_ERAM
- SINGLE_PIN
- SIP_FILE
- SIZE_OF_LATCH_REPORT
- SIZE_OF_PR_INITIAL_CONDITIONS_REPORT
- SKIP_ATOM_SWEEPER
- SKIP_CONFLICTING
- SKIP_CRC_CHECK_IN_HC
- SKIP_REGENERATING_IP_IF_HDL_MODIFIED
- SLD_BIDIR_PIN_CONNECT_FROM_PORT
- SLD_FABRIC_PARTITION
- SLD_FILE
- SLD_INCR_NODE_CREATOR_ID
- SLD_INCR_NODE_ENTITY_NAME
- SLD_INCR_NODE_PARAMETER_ASSIGNMENT
- SLD_INCR_NODE_SOURCE_FILE
- SLD_INFO
- SLD_NODE_CONNECT_FROM_PORT
- SLD_NODE_CONNECT_TO_PORT
- SLD_NODE_CREATOR_ID
- SLD_NODE_ENTITY_NAME
- SLD_NODE_PARAMETER_ASSIGNMENT
- SLD_NODE_SOURCE_FILE
- SLD_PARAMETER_ASSIGNMENT
- SLD_PARAMETER_COMPATIBILITY_STRING
- SLD_PIN_CONNECT_FROM_PORT
- SLD_PIN_CONNECT_TO_PORT
- SLD_PRE_SYN_COMPATIBILITY_STRING
- SLEW_R0
- SLEW_R1
- SLEW_R2
- SLEW_R3
- SLEW_R4
- SLEW_R5
- SLEW_R6
- SLEW_R7
- SLEW_RATE
- SLOW_POR_DELAY
- SLOW_SLEW_RATE
- SMALL
- SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES
- SMART_RECOMPILE
- SMF_FILE
- SMP_PROCESS_TYPE
- SOFT
- SOFTWARE_ACTION_POINTS
- SOFTWARE_LIBRARY_FILE
- SOFTWARE_SETTINGS
- SOFTWARE_SETTINGS_LIST
- SONET
- SONET_OC12_622
- SONET_OC192_9953
- SONET_OC3_155
- SONET_OC48_2488
- SOPC_BUILDER_SIGNATURE_ID
- SOPC_FILE
- SOPCINFO_FILE
- SOURCE_FILE
- SOURCE
- SOURCE_MULTICYCLE_HOLD
- SOURCE_MULTICYCLE
- SOURCES_PER_DESTINATION_INCLUDE_COUNT
- SOURCE_SYNCHRONOUS
- SOURCE_TCL_SCRIPT_FILE
- SOURCE_TCL_SCRIPT
- SPARSE_AUTO
- SPARSE
- SPAUI_6250
- SPD_FILE
- SPECTRAQ_PHYSICAL_SYNTHESIS
- SPEED_DISK_USAGE_TRADEOFF
- SPEED
- SRAM_OBJECT_FILE
- SRC_HOLD_MULTICYCLE
- SRC_MULTICYCLE
- SRECORDS_FILE
- SRIO_1250_LR
- SRIO_1250_SR
- SRIO_2500_LR
- SRIO_2500_SR
- SRIO_3125_LR
- SRIO_3125_SR
- SRIO_5000_LR
- SRIO_5000_MR
- SRIO_5000_SR
- SRIO_6250_LR
- SRIO_6250_MR
- SRIO_6250_SR
- SRIO
- STA_IGNORED_EMBEDDED_SDC_STATEMENT
- STA_MODE
- STANDARD_DELAY_FORMAT_OUTPUT_FILE
- STANDARD_FIT
- STANDARD
- STANDARD_PARTITION
- START_TIME
- START_UP_CLOCK
- STATE_MACHINE_PROCESSING
- STD_ONLY
- STG1_GAIN7
- STG2_GAIN7
- STG3_GAIN7
- STG4_GAIN7
- STOP
- STP_FILE
- STP_INCREMENTAL_SOURCE
- STP_SIGNAL_PROBE_SOURCE
- STP_SIGNALPROBE_SOURCE
- STP_VIRTUAL_PIN_CLK_SOURCE
- STP_VIRTUAL_PIN
- STRATIX_CARRY_CHAIN_LENGTH
- STRATIX_CONFIG_DEVICE_JTAG_USER_CODE
- STRATIX_CONFIGURATION_DEVICE
- STRATIX_CONFIGURATION_SCHEME
- STRATIX_CRC_ERROR_CHECKING
- STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- STRATIX_DEVICE_IO_STANDARD
- STRATIX_FAST_PLL_INCREASE_LOCK_WINDOW
- STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET
- STRATIXGX_ALLOW_DEDICATED_CLOCK_FANOUT_WITH_ANALOG_RESET
- STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE
- STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE
- STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
- STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B
- STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
- STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE
- STRATIXGX_ALLOW_POST8B10B_LOOPBACK
- STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK
- STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE
- STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS
- STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE
- STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
- STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
- STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT
- STRATIXGX_OCT_VALUE
- STRATIXGX_TERMINATION_VALUE
- STRATIXII_ALLOW_DUAL_PORT_DUAL_CLOCK_MRAM_USAGE
- STRATIXII_CARRY_CHAIN_LENGTH
- STRATIX_II_CONFIGURATION_DEVICE
- STRATIXII_CONFIGURATION_DEVICE
- STRATIX_II_CONFIGURATION_SCHEME
- STRATIXII_CONFIGURATION_SCHEME
- STRATIXII_EP2S60ES_ALLOW_MRAM_USAGE
- STRATIXIIGX_OCT_VALUE
- STRATIXIIGX_TERMINATION_VALUE
- STRATIXIII_CONFIGURATION_SCHEME
- STRATIXIII_LUTAB_SLOWDOWN
- STRATIXIII_MRAM_COMPATIBILITY
- STRATIXIII_OUTPUT_DUTY_CYCLE_DELAY
- STRATIXIII_UPDATE_MODE
- STRATIXII_MRAM_COMPATIBILITY
- STRATIXII_OPTIMIZATION_TECHNIQUE
- STRATIXII_OUTPUT_DUTY_CYCLE_CONTROL
- STRATIXII_SILICON_VERSION
- STRATIXII_TERMINATION
- STRATIXIV_CONFIGURATION_SCHEME
- STRATIX_JTAG_USER_CODE
- STRATIX_OPTIMIZATION_TECHNIQUE
- STRATIX_TECHNOLOGY_MAPPER
- STRATIX_UPDATE_MODE
- STRATIXV_CONFIGURATION_SCHEME
- STRICT_POST_FIT
- STRICT_RAM_RECOGNITION
- STRIPE_TO_PLD_BRIDGE_EPXA4_10
- STRIPE_TO_PLD_INTERRUPTS_EPXA4_10
- SUBCLIQUE_OF
- SUPERIOR_PERFORMANCE
- SUPERIOR_PERFORMANCE_WITH_MAXIMUM_PLACEMENT_EFFORT
- SUPPRESS_DA_RULE_INTERNAL
- SUPPRESS_REG_MINIMIZATION_MSG
- SVF_FILE
- SXL9
- SYMBOL_FILE
- SYM_FILE
- SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
- SYNCHRONIZER_IDENTIFICATION
- SYNCHRONIZER_TOGGLE_RATE
- SYNTH_CHECK_PORT_CONNECTIONS
- SYNTH_CLOCK_MUX_PROTECTION
- SYNTH_CRITICAL_CLOCK
- SYNTH_CRITICAL_CLOCK_TO_OUTPUT
- SYNTH_CRITICAL_ENABLE
- SYNTH_CRITICAL_INPUT_TO_CLOCK
- SYNTH_CRITICAL_PIN
- SYNTHESIS_EFFORT
- SYNTHESIS_FITTING_SETTINGS
- SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
- SYNTHESIS_ON_ATOMS
- SYNTHESIS_ONLY
- SYNTHESIS_ONLY_QIP
- SYNTHESIS_S10_MIGRATION_CHECKS
- SYNTHESIS_SEED
- SYNTHESIS_WILDCARDS
- SYNTHESIZE_LATCHES_AS_HIPIS
- SYNTH_GATED_CLOCK_CONVERSION
- SYNTH_MESSAGE_LEVEL
- SYNTH_PROTECT_SDC_CONSTRAINT
- SYNTH_REPORT_SOURCE_ASSIGNMENTS
- SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM
- SYNTH_RPT_SHOW_PARAMS_PER_ENTITY_INSTANCE
- SYNTH_TIMING_DRIVEN_BALANCED_MAPPING
- SYNTH_TIMING_DRIVEN_REGISTER_DUPLICATION
- SYNTH_TIMING_DRIVEN_SYNTHESIS
- SYSTEMVERILOG_2005
- SYSTEMVERILOG_2009
- SYSTEMVERILOG_FILE
- T10_DELAY
- T10_FINE_DELAY
- T10_OCT_DELAY
- T10_OE_DELAY
- T10_OE_FINE_DELAY
- T11_0_DELAY
- T11_1_DELAY
- T11_DELAY
- T11_FINE_DELAY
- T1_DELAY
- T1_FINE_DELAY
- T2_DELAY
- T3_DELAY
- T4_DELAY
- T7_DELAY
- T7_FINE_DELAY
- T8_DELAY0
- T8_DELAY1
- T9_DELAY
- T9_FINE_DELAY
- T9_OCT_DELAY
- T9_OE_DELAY
- TAN_SCRIPT_FILE
- TAO_FILE
- TAO_FILE_NAME
- TBFF_PULSE_WIDTH
- TCL_ENTITY_FILE
- TCL_FILE
- TCL_SCRIPT_FILE
- TCO_REQUIREMENT
- TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT
- TDC_CCPP_TRADEOFF_TOLERANCE
- TDO_DUMP_FILE
- TECH_MAPPER_APEX20K
- TECH_MAPPER_DALI
- TECH_MAPPER_FLEX10K
- TECH_MAPPER_FLEX6K
- TECH_MAPPER
- TECH_MAPPER_MAX7000
- TECH_MAPPER_YEAGER
- TECHNOLOGY_MAPPER_DALI
- TECHNOLOGY_MAPPER_FLEX6K
- TECHNOLOGY_MAPPER
- TEMPLATE_FILE
- TENG_1588
- TENG_BASER
- TENG_KR_10312
- TENG_SDI
- TERMINATION_CONTROL_BLOCK
- TERMINATION
- TEST_BENCH_MODE
- TESTING_BOOL
- TESTING_ENUM
- TESTING_FILE
- TESTING_INT_GLOBAL_DISALLOWED_IN_QIP
- TESTING_INT
- TESTING_SINGLE_ABSOLUTE_NODE_ENTITY_INT
- TESTING_SINGLE_BOOL
- TESTING_SINGLE_ENUM
- TESTING_SINGLE_INT
- TESTING_SINGLE_RELATIVE_BOOL
- TESTING_SINGLE_RELATIVE_ENTITY_INT
- TESTING_SINGLE_RELATIVE_NODE_ENTITY_BOOL
- TESTING_SINGLE_RELATIVE_NODE_ENTITY_INT
- TESTING_SINGLE_RELATIVE_NODE_INT
- TESTING_SINGLE_STRING
- TESTING_STRING
- TEXT_FILE
- TEXT_FORMAT_REPORT_FILE
- THIRD_PARTY_EDA_TOOLS
- THREE
- TH_REQUIREMENT
- THR_THREAD_MAIN_ID
- TIMEGROUP_EXCEPTION
- TIMEGROUP_MEMBER
- TIMEQUEST2
- TIMEQUEST_CCPP_TRADEOFF_TOLERANCE
- TIMEQUEST_DO_CCPP_REMOVAL
- TIMEQUEST_DO_REPORT_CDC_VIEWER
- TIMEQUEST_DO_REPORT_TIMING
- TIMEQUEST_MULTICORNER_ANALYSIS
- TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS
- TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
- TIMEQUEST_REPORT_SCRIPT
- TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS
- TIMEQUEST_SIMULTANEOUS_MULTICORNER_ANALYSIS
- TIMEQUEST_SPECTRA_Q
- TIMING_ANALYSIS_OUTPUT_FILE
- TIMING_ANALYZER_CCPP_TRADEOFF_TOLERANCE
- TIMING_ANALYZER_DO_CCPP_REMOVAL
- TIMING_ANALYZER_DO_REPORT_CDC_VIEWER
- TIMING_ANALYZER_DO_REPORT_TIMING
- TIMING_ANALYZER_MULTICORNER_ANALYSIS
- TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS
- TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
- TIMING_ANALYZER_REPORT_SCRIPT
- TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS
- TIMING_ANALYZER_SIMULTANEOUS_MULTICORNER_ANALYSIS
- TIMING_ASSIGNMENT
- TIMING_CAT
- TIMING_DERATING_FILE
- TIMING_DRIVEN_COMPILE
- TIMING
- TIMING_REQUIREMENTS
- TIMING_RULE_COIN_CLKEDGE
- TIMING_RULE_HIGH_FANOUTS
- TIMING_RULE_SHIFT_REG
- TIMING_USING_FAST_TIMING_MODEL
- TOGGLE_RATE
- TOOLSET
- TOP_LEVEL_ENTITY
- TOP_PARTITION_PIN
- TPD_REQUIREMENT
- TRANSPORT
- TREAT_BIDIR_AS_OUTPUT
- TRI_CONVERTED_FROM_DIRECTIONAL_BUFFER
- TRIGGER_EQUATION
- TRIGGER_VECTOR_COMPARE_ON_SIGNAL
- TRISTATE1
- TRISTATED1
- TRI_STATE
- TRISTATE
- TRISTATE_OFF
- TRISTATE_ON
- TRI_STATE_SPI_PINS
- TRUE
- TRUE_WYSIWYG_FLOW
- TSUNAMI_OPTIMIZATION_TECHNIQUE
- TSU_REQUIREMENT
- TURBO_BIT
- TXPMA_SLEW_RATE
- TYPICAL
- U0H9
- UC_DCD_CAL_OFF
- UC_DCD_CAL_ON
- UC_RO_CAL_OFF
- UC_RO_CAL_ON
- UC_RX_DFE_CAL_OFF
- UC_RX_DFE_CAL_ON
- UC_SKEW_CAL_OFF
- UC_SKEW_CAL_ON
- UC_TX_VOD_CAL_CONT_OFF
- UC_TX_VOD_CAL_CONT_ON
- UC_TX_VOD_CAL_OFF
- UC_TX_VOD_CAL_ON
- UI_DEFAULT_ASSEMBLER_SETTING
- UI_DEFAULT_COMP_PROCESS_SETTING
- UI_DEFAULT_EDA_NATIVELINK_SETTING
- UI_DEFAULT_EDA_SIMULATION_SETTING
- UI_DEFAULT_FITTER_SETTING
- UI_DEFAULT_HYPERFLEX_SETTING
- UI_DEFAULT_OPTIMIZATION_SETTING
- UI_DEFAULT_SIMULATOR_SETTING
- UI_DEFAULT_SYNTHESIS_SETTING
- UI_DEFAULT_TIMING_SETTING
- UNFORCE_MERGE_PLL
- UNFORCE_MERGE_PLL_OUTPUT_COUNTER
- UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE
- UNIPHY_TEMP_VER_CODE
- UNNAMED_POOL
- UNSECURED
- UNUSED_RXCLK_BTI_MITIGATION
- UNUSED_RXTXCLK_BTI_MITIGATION
- UNUSED_TSD_PINS_GND
- UPCORE_TRANSACTION_MODEL_FILE
- UPDATE_ASE_FEATURE_TIME_WHEN_CHANGED
- UPDATE_ASSIGNMENT_GROUP_FEATURE_TIME_WHEN_CHANGED
- UPDATE_CHIP_EDITOR_FEATURE_TIME_WHEN_CHANGED
- UPDATE_CONFLICTING
- UPDATE_ECMC_FEATURE_TIME_WHEN_CHANGED
- UPDATE_FLOORPLAN_EDITOR_FEATURE_TIME_WHEN_CHANGED
- UPDATE_MODE_INTERNAL_FLASH
- UPDATE_MODE_TITAN
- UPDATE_MODE_YEAGER
- UPDATE_PAT_FEATURE_TIME_WHEN_CHANGED
- UPDATE_PIN_PLANNER_FEATURE_TIME_WHEN_CHANGED
- UPDATE_SIM_FEATURE_TIME_WHEN_CHANGED
- UPDATE_SSN_FEATURE_TIME_WHEN_CHANGED
- UPDATE_TAN_FEATURE_TIME_WHEN_CHANGED
- UPGRADE_WIDTH
- USE_ADVANCED_DETAILED_LAB_LEGALITY
- USE_AS_3V_GPIO
- USE_AS_PROGRAMMING_PIN
- USE_AS_REGULAR_IO
- USE_CAP
- USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT
- USE_CHECKSUM_AS_USERCODE
- USE_CHECKSUM_AS_USERCODE_MAX7000
- USE_CLK_FOR_VIRTUAL_PIN
- USE_CLOCK
- USE_CLOCK_SETTINGS
- USE_COMPILER_SETTINGS
- USE_CONF_DONE
- USE_CONFIGURATION_DEVICE
- USE_CONFIGURATION_DEVICE_NAME_APEX20K
- USE_CONFIGURATION_DEVICE_NAME_ARMSTRONG
- USE_CONFIGURATION_DEVICE_NAME_CUDA
- USE_CONFIGURATION_DEVICE_NAME_CYCLONE
- USE_CONFIGURATION_DEVICE_NAME_DALI
- USE_CONFIGURATION_DEVICE_NAME_EXCALIBUR
- USE_CONFIGURATION_DEVICE_NAME_FLEX10K
- USE_CONFIGURATION_DEVICE_NAME_FLEX6K
- USE_CONFIGURATION_DEVICE_NAME
- USE_CONFIGURATION_DEVICE_NAME_YEAGER
- USE_CONFIGURATION_DEVICE_OPTIONS
- USE_C_PREPROCESSOR_FOR_GNU_ASM_FILES
- USE_CVP_CONFDONE
- USE_DATA_UNLOCK
- USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
- USE_DMF
- USE_GENERATED_PHYSICAL_CONSTRAINTS
- USE_GLOBAL_SETTINGS
- USE_HIGH_SPEED_ADDER
- USE_HPS_COLD_RESET
- USE_HPS_WARM_RESET
- USE_INIT_DONE
- USE_LOCAL_APEX20K
- USE_LOCAL_FLEX6K
- USE_LOCAL
- USE_LOGIC_ANALYZER_INTERFACE_FILE
- USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
- USE_LPM_FOR_AHDL_OPERATORS
- USE_MULTITAP_FILE
- USE_NEW_TEXT_REPORT_TABLE_FORMAT
- USE_PWRMGT_ALERT
- USE_PWRMGT_PWM0
- USE_PWRMGT_SCL
- USE_PWRMGT_SDA
- USER_CUSTOM
- USER_ENABLED
- USER_ENCODED
- USER_FILES_NEW_EXTRACTOR
- USER_JTAG_CODE_APEX20K
- USER_JTAG_CODE_DALI
- USER_JTAG_CODE_FLEX10K
- USER_JTAG_CODE_FLEX6K
- USER_JTAG_CODE
- USER_JTAG_CODE_MAX7000
- USER_JTAG_CODE_MAX7000S
- USER_JTAG_CODE_YEAGER
- USER_LIBRARIES
- USER_MESSAGE
- USER_START_UP_CLOCK
- USER_VALUE
- USE_SEU_ERROR
- USE_SIGNALTAP_FILE
- USE_TCL_PROC
- USE_TIMEQUEST_TIMING_ANALYZER
- USE_TIMING_DRIVEN_COMPILATION
- USE_UIB_CATTRIP
- USE_VPACK
- USE_VPR
- USE_VQM_INSTEAD_OF_SOURCE
- V0P00
- V0P58
- V0P64
- V0P67
- V0P70
- V0P75
- V0P81
- V0P86
- V0P87
- V0P93
- V0P96
- V1P00
- V1P04
- V1P13
- V1P22
- V1P30
- V1P39
- VALUE_IS_NODE
- VARIABLE_VALUE_CANNOT_BE_CHANGED
- VCCA_FPLL_USER_VOLTAGE
- VCCA_GTBR_USER_VOLTAGE
- VCCA_GTB_USER_VOLTAGE
- VCCA_GXBL_USER_VOLTAGE
- VCCA_GXBR_USER_VOLTAGE
- VCCA_GXB_USER_VOLTAGE
- VCCA_L_USER_VOLTAGE
- VCCA_PLL_USER_VOLTAGE
- VCCA_R_USER_VOLTAGE
- VCCA_USER_VOLTAGE
- VCCAUX_SHARED_USER_VOLTAGE
- VCCAUX_USER_VOLTAGE
- VCCBAT_USER_VOLTAGE
- VCCCB_USER_VOLTAGE
- VCCD_FPLL_USER_VOLTAGE
- VCCD_PLL_USER_VOLTAGE
- VCCD_USER_VOLTAGE
- VCCE_GXBL_USER_VOLTAGE
- VCCE_GXBR_USER_VOLTAGE
- VCCE_GXB_USER_VOLTAGE
- VCCEH_GXBL_USER_VOLTAGE
- VCCEH_GXBR_USER_VOLTAGE
- VCCEH_GXB_USER_VOLTAGE
- VCCELA_0P85V
- VCCELA_0P9V
- VCCELA_1P0V
- VCCELA_1P1V
- VCCERAM_USER_VOLTAGE
- VCCER
- VCCE_USER_VOLTAGE
- VCCH_GTBR_USER_VOLTAGE
- VCCH_GTB_USER_VOLTAGE
- VCCH_GXBL_USER_VOLTAGE
- VCCH_GXBR_USER_VOLTAGE
- VCCH_GXB_USER_VOLTAGE
- VCCHIP_L_USER_VOLTAGE
- VCCHIP_R_USER_VOLTAGE
- VCCHIP_USER_VOLTAGE
- VCCH_L_USER_VOLTAGE
- VCC_HPS_USER_VOLTAGE
- VCCH_R_USER_VOLTAGE
- VCCHSSI_L_USER_VOLTAGE
- VCCHSSI_R_USER_VOLTAGE
- VCCINT_USER_VOLTAGE
- VCCIO_45
- VCCIO_50
- VCCIO_55
- VCCIO_65
- VCCIO_70
- VCCIO_75
- VCCIO_CURRENT_1PT8V
- VCCIO_CURRENT_2PT5V
- VCCIO_CURRENT_GTL
- VCCIO_CURRENT_GTL_PLUS
- VCCIO_CURRENT_LVCMOS
- VCCIO_CURRENT_LVTTL
- VCCIO_CURRENT_PCI
- VCCIO_CURRENT_SSTL2_CLASS1
- VCCIO_CURRENT_SSTL2_CLASS2
- VCCIO_CURRENT_SSTL3_CLASS1
- VCCIO_CURRENT_SSTL3_CLASS2
- VCCIO_HPS_USER_VOLTAGE
- VCCIO_IOBANK1_MAX7000B
- VCCIO_IOBANK2_MAX7000B
- VCCIOREF_HPS_USER_VOLTAGE
- VCCIO_USER_VOLTAGE
- VCCL_GTBL_USER_VOLTAGE
- VCCL_GTBR_USER_VOLTAGE
- VCCL_GTB_USER_VOLTAGE
- VCCL_GXBL_USER_VOLTAGE
- VCCL_GXBR_USER_VOLTAGE
- VCCL_GXB_USER_VOLTAGE
- VCCL_HPS_USER_VOLTAGE
- VCCL_USER_VOLTAGE
- VCCPD_USER_VOLTAGE
- VCCPD_VOLTAGE
- VCCPGM_USER_VOLTAGE
- VCCPLL_HPS_USER_VOLTAGE
- VCCPT_USER_VOLTAGE
- VCCP_USER_VOLTAGE
- VCCR_GTBL_USER_VOLTAGE
- VCCR_GTBR_USER_VOLTAGE
- VCCR_GTB_USER_VOLTAGE
- VCCR_GXBL_USER_VOLTAGE
- VCCR_GXBR_USER_VOLTAGE
- VCCR_GXB_USER_VOLTAGE
- VCCR_L_USER_VOLTAGE
- VCCR_R_USER_VOLTAGE
- VCCRSTCLK_HPS_USER_VOLTAGE
- VCCR_USER_VOLTAGE
- VCC_SETTING0
- VCC_SETTING1
- VCC_SETTING2
- VCC_SETTING3
- VCCT_GTBL_USER_VOLTAGE
- VCCT_GTBR_USER_VOLTAGE
- VCCT_GTB_USER_VOLTAGE
- VCCT_GXBL_USER_VOLTAGE
- VCCT_GXBR_USER_VOLTAGE
- VCCT_GXB_USER_VOLTAGE
- VCCT_L_USER_VOLTAGE
- VCCT_R_USER_VOLTAGE
- VCCT_USER_VOLTAGE
- VCC_USER_VOLTAGE
- VCD_FILE
- VCM_CURRENT_1
- VCM_CURRENT_2
- VCM_CURRENT_3
- VCM_CURRENT_DEFAULT
- VCM_SETTING_00
- VCM_SETTING_01
- VCM_SETTING_02
- VCM_SETTING_03
- VCM_SETTING_04
- VCM_SETTING_05
- VCM_SETTING_06
- VCM_SETTING_07
- VCM_SETTING_08
- VCM_SETTING_09
- VCM_SETTING_10
- VCM_SETTING_11
- VCM_SETTING_12
- VCM_SETTING_13
- VCM_SETTING_14
- VCM_SETTING_15
- VECTOR_CHANNEL_FILE
- VECTOR_COMPARE_TRIGGER_MODE
- VECTOR_FILE
- VECTOR_INPUT_SOURCE
- VECTOR_OUTPUT_DESTINATION
- VECTOR_OUTPUT_FORMAT
- VECTOR_SOURCE_FILE
- VECTOR_TABLE_OUTPUT_FILE
- VECTOR_TEXT_FILE
- VECTOR_WAVEFORM_FILE
- VER_COMPATIBLE_DB_DIR
- VERILOG_1995
- VERILOG_2001
- VERILOG_CONSTANT_LOOP_LIMIT
- VERILOG_CU_MODE
- VERILOG_FILE
- VERILOG_GLOBAL_COMPILER_MACRO_FILE
- VERILOG_INCLUDE_FILE
- VERILOG_INPUT_VERSION
- VERILOG_LMF_FILE
- VERILOG_MACRO
- VERILOG_NON_CONSTANT_LOOP_LIMIT
- VERILOG_OUTPUT_FILE
- VERILOG_SHOW_LMF_MAPPING_MESSAGES
- VERILOG_SHOW_LMF_MAPPING_MSGS
- VERILOG_TEST_BENCH_FILE
- VERILOG_VH_FILE
- VHDL_1987
- VHDL_1993
- VHDL_2008
- VHDL87
- VHDL93
- VHDL_FILE
- VHDL_INPUT_LIBRARY
- VHDL_INPUT_VERSION
- VHDL_LMF_FILE
- VHDL_OUTPUT_FILE
- VHDL_SHOW_LMF_MAPPING_MESSAGES
- VHDL_SHOW_LMF_MAPPING_MSGS
- VHDL_TEST_BENCH_FILE
- VID_OPERATION_MODE
- VIRTUAL_CLOCK_REFERENCE
- VIRTUAL_EFUSES
- VIRTUAL_IO_DRIVES_CLOCK_PORT
- VIRTUAL_PIN
- VOLT_0MV
- VOLT_0P35V
- VOLT_0P50V
- VOLT_0P55V
- VOLT_0P60V
- VOLT_0P65V
- VOLT_0P70V
- VOLT_0P75V
- VOLT_0P80V
- VOLTS
- VPACK
- VPACK_ONLY
- VQM_FILE
- VREF_MODE
- VREF_VOLT_0
- VREF_VOLT_0P5
- VREF_VOLT_0P75
- VREF_VOLT_1P0
- VTT_0P35V
- VTT_0P50V
- VTT_0P55V
- VTT_0P60V
- VTT_0P65V
- VTT_0P70V
- VTT_0P75V
- VTT_0P80V
- VTT_PDN_STRONG
- VTT_PDN_WEAK
- VTT_PUP_STRONG
- VTT_PUP_WEAK
- VTT_VCMOFF0
- VTT_VCMOFF1
- VTT_VCMOFF2
- VTT_VCMOFF3
- VTT_VCMOFF4
- VTT_VCMOFF5
- VTT_VCMOFF6
- VTT_VCMOFF7
- WAIT_1_MS
- WAIT_2_MS
- WAIT_4_MS
- WAIT_50_MS
- WAIT_8_MS
- WEAK_PULL_UP
- WEAK_PULL_UP_RESISTOR
- WHEN_REQUESTED_BY_FPGA
- WHEN_TSU_AND_TPD_CONSTRAINTS_PERMIT
- WIDTH_0
- WIDTH_18_BIT_MULTIPLIERS
- WIDTH_1
- WIDTH_2
- WIDTH_3
- WIDTH
- WRITE
- X1_PLL_FREQUENCY
- XACTO_INCREMENTAL_COMPILE_ASSIGNMENT
- XACTO_INCREMENTAL_COMPILE_FILE
- XACTO_REGION
- XACTO_VQM_FILES
- XAUI_3125
- XAUI
- XCVR_A10_CDR_PLL_ANALOG_MODE
- XCVR_A10_CDR_PLL_POWER_MODE
- XCVR_A10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
- XCVR_A10_CDR_PLL_UC_RO_CAL
- XCVR_A10_CMU_FPLL_ANALOG_MODE
- XCVR_A10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
- XCVR_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
- XCVR_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
- XCVR_A10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
- XCVR_A10_CMU_FPLL_POWER_MODE
- XCVR_A10_LC_PLL_ANALOG_MODE
- XCVR_A10_LC_PLL_POWER_MODE
- XCVR_A10_PM_UC_CLKDIV_SEL
- XCVR_A10_PM_UC_CLKSEL_CORE
- XCVR_A10_PM_UC_CLKSEL_OSC
- XCVR_A10_REFCLK_TERM_TRISTATE
- XCVR_A10_RX_ADAPT_DFE_CONTROL_SEL
- XCVR_A10_RX_ADAPT_DFE_SEL
- XCVR_A10_RX_ADAPT_VGA_SEL
- XCVR_A10_RX_ADAPT_VREF_SEL
- XCVR_A10_RX_ADP_CTLE_ACGAIN_4S
- XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
- XCVR_A10_RX_ADP_DFE_FLTAP_POSITION
- XCVR_A10_RX_ADP_DFE_FXTAP10
- XCVR_A10_RX_ADP_DFE_FXTAP10_SGN
- XCVR_A10_RX_ADP_DFE_FXTAP11
- XCVR_A10_RX_ADP_DFE_FXTAP11_SGN
- XCVR_A10_RX_ADP_DFE_FXTAP1
- XCVR_A10_RX_ADP_DFE_FXTAP2
- XCVR_A10_RX_ADP_DFE_FXTAP2_SGN
- XCVR_A10_RX_ADP_DFE_FXTAP3
- XCVR_A10_RX_ADP_DFE_FXTAP3_SGN
- XCVR_A10_RX_ADP_DFE_FXTAP4
- XCVR_A10_RX_ADP_DFE_FXTAP4_SGN
- XCVR_A10_RX_ADP_DFE_FXTAP5
- XCVR_A10_RX_ADP_DFE_FXTAP5_SGN
- XCVR_A10_RX_ADP_DFE_FXTAP6
- XCVR_A10_RX_ADP_DFE_FXTAP6_SGN
- XCVR_A10_RX_ADP_DFE_FXTAP7
- XCVR_A10_RX_ADP_DFE_FXTAP7_SGN
- XCVR_A10_RX_ADP_DFE_FXTAP8
- XCVR_A10_RX_ADP_DFE_FXTAP8_SGN
- XCVR_A10_RX_ADP_DFE_FXTAP9
- XCVR_A10_RX_ADP_DFE_FXTAP9_SGN
- XCVR_A10_RX_ADP_LFEQ_FB_SEL
- XCVR_A10_RX_ADP_ONETIME_DFE
- XCVR_A10_RX_ADP_VGA_SEL
- XCVR_A10_RX_ADP_VREF_SEL
- XCVR_A10_RX_BYPASS_EQZ_STAGES_234
- XCVR_A10_RX_EQ_BW_SEL
- XCVR_A10_RX_EQ_DC_GAIN_TRIM
- XCVR_A10_RX_INPUT_VCM_SEL
- XCVR_A10_RX_LINK
- XCVR_A10_RX_OFFSET_CANCELLATION_CTRL
- XCVR_A10_RX_ONE_STAGE_ENABLE
- XCVR_A10_RX_POWER_MODE
- XCVR_A10_RX_QPI_ENABLE
- XCVR_A10_RX_RX_SEL_BIAS_SOURCE
- XCVR_A10_RX_SD_OUTPUT_OFF
- XCVR_A10_RX_SD_OUTPUT_ON
- XCVR_A10_RX_SD_THRESHOLD
- XCVR_A10_RX_TERM_SEL
- XCVR_A10_RX_TERM_TRI_ENABLE
- XCVR_A10_RX_UC_RX_DFE_CAL
- XCVR_A10_RX_VCCELA_SUPPLY_VOLTAGE
- XCVR_A10_RX_VCM_CURRENT_ADD
- XCVR_A10_RX_VCM_SEL
- XCVR_A10_RX_XRX_PATH_ANALOG_MODE
- XCVR_A10_TX_COMPENSATION_EN
- XCVR_A10_TX_DCD_DETECTION_EN
- XCVR_A10_TX_DPRIO_CGB_VREG_BOOST
- XCVR_A10_TX_LINK
- XCVR_A10_TX_LOW_POWER_EN
- XCVR_A10_TX_POWER_MODE
- XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
- XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
- XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
- XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
- XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
- XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
- XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
- XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
- XCVR_A10_TX_RES_CAL_LOCAL
- XCVR_A10_TX_RX_DET
- XCVR_A10_TX_RX_DET_OUTPUT_SEL
- XCVR_A10_TX_RX_DET_PDB
- XCVR_A10_TX_SLEW_RATE_CTRL
- XCVR_A10_TX_TERM_CODE
- XCVR_A10_TX_TERM_SEL
- XCVR_A10_TX_UC_DCD_CAL
- XCVR_A10_TX_UC_GEN3
- XCVR_A10_TX_UC_GEN4
- XCVR_A10_TX_UC_SKEW_CAL
- XCVR_A10_TX_UC_TXVOD_CAL_CONT
- XCVR_A10_TX_UC_TXVOD_CAL
- XCVR_A10_TX_UC_VCC_SETTING
- XCVR_A10_TX_USER_FIR_COEFF_CTRL_SEL
- XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
- XCVR_A10_TX_XTX_PATH_ANALOG_MODE
- XCVR_ANALOG_SETTINGS_PROTOCOL
- XCVR_C10_CDR_PLL_ANALOG_MODE
- XCVR_C10_CDR_PLL_POWER_MODE
- XCVR_C10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
- XCVR_C10_CDR_PLL_UC_RO_CAL
- XCVR_C10_CMU_FPLL_ANALOG_MODE
- XCVR_C10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
- XCVR_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
- XCVR_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
- XCVR_C10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
- XCVR_C10_CMU_FPLL_POWER_MODE
- XCVR_C10_LC_PLL_ANALOG_MODE
- XCVR_C10_LC_PLL_POWER_MODE
- XCVR_C10_PM_UC_CLKDIV_SEL
- XCVR_C10_PM_UC_CLKSEL_CORE
- XCVR_C10_PM_UC_CLKSEL_OSC
- XCVR_C10_REFCLK_TERM_TRISTATE
- XCVR_C10_RX_ADAPT_DFE_CONTROL_SEL
- XCVR_C10_RX_ADAPT_DFE_SEL
- XCVR_C10_RX_ADAPT_VGA_SEL
- XCVR_C10_RX_ADAPT_VREF_SEL
- XCVR_C10_RX_ADP_CTLE_ACGAIN_4S
- XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL
- XCVR_C10_RX_ADP_DFE_FLTAP_POSITION
- XCVR_C10_RX_ADP_DFE_FXTAP10
- XCVR_C10_RX_ADP_DFE_FXTAP10_SGN
- XCVR_C10_RX_ADP_DFE_FXTAP11
- XCVR_C10_RX_ADP_DFE_FXTAP11_SGN
- XCVR_C10_RX_ADP_DFE_FXTAP1
- XCVR_C10_RX_ADP_DFE_FXTAP2
- XCVR_C10_RX_ADP_DFE_FXTAP2_SGN
- XCVR_C10_RX_ADP_DFE_FXTAP3
- XCVR_C10_RX_ADP_DFE_FXTAP3_SGN
- XCVR_C10_RX_ADP_DFE_FXTAP4
- XCVR_C10_RX_ADP_DFE_FXTAP4_SGN
- XCVR_C10_RX_ADP_DFE_FXTAP5
- XCVR_C10_RX_ADP_DFE_FXTAP5_SGN
- XCVR_C10_RX_ADP_DFE_FXTAP6
- XCVR_C10_RX_ADP_DFE_FXTAP6_SGN
- XCVR_C10_RX_ADP_DFE_FXTAP7
- XCVR_C10_RX_ADP_DFE_FXTAP7_SGN
- XCVR_C10_RX_ADP_DFE_FXTAP8
- XCVR_C10_RX_ADP_DFE_FXTAP8_SGN
- XCVR_C10_RX_ADP_DFE_FXTAP9
- XCVR_C10_RX_ADP_DFE_FXTAP9_SGN
- XCVR_C10_RX_ADP_LFEQ_FB_SEL
- XCVR_C10_RX_ADP_ONETIME_DFE
- XCVR_C10_RX_ADP_VGA_SEL
- XCVR_C10_RX_ADP_VREF_SEL
- XCVR_C10_RX_BYPASS_EQZ_STAGES_234
- XCVR_C10_RX_EQ_BW_SEL
- XCVR_C10_RX_EQ_DC_GAIN_TRIM
- XCVR_C10_RX_INPUT_VCM_SEL
- XCVR_C10_RX_LINK
- XCVR_C10_RX_OFFSET_CANCELLATION_CTRL
- XCVR_C10_RX_ONE_STAGE_ENABLE
- XCVR_C10_RX_POWER_MODE
- XCVR_C10_RX_QPI_ENABLE
- XCVR_C10_RX_RX_SEL_BIAS_SOURCE
- XCVR_C10_RX_SD_OUTPUT_OFF
- XCVR_C10_RX_SD_OUTPUT_ON
- XCVR_C10_RX_SD_THRESHOLD
- XCVR_C10_RX_TERM_SEL
- XCVR_C10_RX_TERM_TRI_ENABLE
- XCVR_C10_RX_UC_RX_DFE_CAL
- XCVR_C10_RX_VCCELA_SUPPLY_VOLTAGE
- XCVR_C10_RX_VCM_CURRENT_ADD
- XCVR_C10_RX_VCM_SEL
- XCVR_C10_RX_XRX_PATH_ANALOG_MODE
- XCVR_C10_TX_COMPENSATION_EN
- XCVR_C10_TX_DCD_DETECTION_EN
- XCVR_C10_TX_DPRIO_CGB_VREG_BOOST
- XCVR_C10_TX_LINK
- XCVR_C10_TX_LOW_POWER_EN
- XCVR_C10_TX_POWER_MODE
- XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP
- XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP
- XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T
- XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T
- XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
- XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
- XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
- XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
- XCVR_C10_TX_RES_CAL_LOCAL
- XCVR_C10_TX_RX_DET
- XCVR_C10_TX_RX_DET_OUTPUT_SEL
- XCVR_C10_TX_RX_DET_PDB
- XCVR_C10_TX_SLEW_RATE_CTRL
- XCVR_C10_TX_TERM_CODE
- XCVR_C10_TX_TERM_SEL
- XCVR_C10_TX_UC_DCD_CAL
- XCVR_C10_TX_UC_GEN3
- XCVR_C10_TX_UC_GEN4
- XCVR_C10_TX_UC_SKEW_CAL
- XCVR_C10_TX_UC_TXVOD_CAL_CONT
- XCVR_C10_TX_UC_TXVOD_CAL
- XCVR_C10_TX_UC_VCC_SETTING
- XCVR_C10_TX_USER_FIR_COEFF_CTRL_SEL
- XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL
- XCVR_C10_TX_XTX_PATH_ANALOG_MODE
- XCVR_FAST_LOCK_MODE
- XCVR_GT_IO_PIN_TERMINATION
- XCVR_GT_RX_COMMON_MODE_VOLTAGE
- XCVR_GT_RX_CTLE
- XCVR_GT_RX_DC_GAIN
- XCVR_GT_RX_FORCE_VCO_CONST
- XCVR_GT_TX_COMMON_MODE_VOLTAGE
- XCVR_GT_TX_PRE_EMP_1ST_POST_TAP
- XCVR_GT_TX_PRE_EMP_INV_PRE_TAP
- XCVR_GT_TX_PRE_EMP_PRE_TAP
- XCVR_GT_TX_VOD_MAIN_TAP
- XCVR_IO_PIN_TERMINATION
- XCVR_RECONFIG_AVMM_GROUP
- XCVR_RECONFIG_GROUP
- XCVR_REFCLK_PIN_TERMINATION
- XCVR_RX_ACGAIN_A
- XCVR_RX_ACGAIN_V
- XCVR_RX_ADCE_HSF_HFBW
- XCVR_RX_ADCE_RGEN_BW
- XCVR_RX_ADCE_RGEN_MODE
- XCVR_RX_BYPASS_EQ_STAGES_234
- XCVR_RX_COMMON_MODE_VOLTAGE
- XCVR_RX_DC_GAIN
- XCVR_RX_DFE_PI_BW
- XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
- XCVR_RX_EQ_BW_SEL
- XCVR_RX_EYEQ_BANDWIDTH
- XCVR_RX_INPUT_VCM_SEL
- XCVR_RX_LINEAR_EQUALIZER_CONTROL
- XCVR_RX_PMOS_GAIN_PEAK
- XCVR_RX_QPI_ENABLE
- XCVR_RX_SD_ENABLE
- XCVR_RX_SD_OFF
- XCVR_RX_SD_ON
- XCVR_RX_SD_THRESHOLD
- XCVR_RX_SEL_BIAS_SOURCE
- XCVR_RX_SEL_HALF_BW
- XCVR_RX_VCM_DRIVE_STRENGTH
- XCVR_S10_REFCLK_TERM_TRISTATE
- XCVR_TX_COMMON_MODE_VOLTAGE
- XCVR_TX_DRIVER_RESOLUTION_CTRL
- XCVR_TX_LOCAL_IB_CTL
- XCVR_TX_PLL_RECONFIG_GROUP
- XCVR_TX_PRE_EMP_1ST_POST_TAP
- XCVR_TX_PRE_EMP_2ND_POST_TAP
- XCVR_TX_PRE_EMP_2ND_POST_TAP_USER
- XCVR_TX_PRE_EMP_INV_2ND_TAP
- XCVR_TX_PRE_EMP_INV_PRE_TAP
- XCVR_TX_PRE_EMP_PRE_TAP
- XCVR_TX_PRE_EMP_PRE_TAP_USER
- XCVR_TX_QPI_EN
- XCVR_TX_RX_DET_ENABLE
- XCVR_TX_RX_DET_MODE
- XCVR_TX_RX_DET_OUTPUT_SEL
- XCVR_TX_SLEW_RATE_CTRL
- XCVR_TX_SWING_BOOST
- XCVR_TX_VCM_CTRL_SRC
- XCVR_TX_VCM_DRIVE_STRENGTH
- XCVR_TX_VOD_BOOST
- XCVR_TX_VOD
- XCVR_TX_VOD_PRE_EMP_CTRL_SRC
- XCVR_USE_HQ_REFCLK
- XCVR_USE_SKEW_BALANCED
- XCVR_VCCA_VOLTAGE
- XCVR_VCCR_VCCT_VOLTAGE
- X_ON_VIOLATION_OPTION
- XOR_SYNTHESIS
- XR_AUTO_SIZE
- XR_CORE_ONLY
- XR_EXCLUDE
- XR_HEIGHT
- XR_MEMBER_OF
- XR_MEMBER_OPTION
- XR_MEMBER_RESOURCE_EXCLUDE
- XR_MEMBER_STATE
- XR_NODE_LOCATION
- XR_ORIGIN
- XR_PARENT
- XR_PATH_EXCLUDE
- XR_PATH_INCLUDE
- XR_PRIORITY
- XR_RESERVE
- XR_ROOT_REGION
- XR_ROUGH
- XR_SOFT
- XR_STATE
- XR_WIDTH
- XSTL_INPUT_ALLOW_SE_BUFFER
- YEAGER_CONFIGURATION_DEVICE
- YEAGER_CRC_ERROR_CHECKING
- YEAGER_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- YEAGER_DEVICE_IO_STANDARD
- YEAGER_OCT_AND_IMPEDANCE_MATCHING
- YEAGER_OPTIMIZATION_TECHNIQUE
- YEAGER_TECHNOLOGY_MAPPER
- YEAGER_UPDATE_MODE
- ZBT_OE_FALLING_EDGE_DELAY
- ZERO_DELAY_BUFFER
- ZERO
- ZIP_VECTOR_CHANNEL_FILE
- ZIP_VECTOR_WAVEFORM_FILE
