UNISIM and command-line simulation with the Xilinx simulator

I simulate models outside of the Xilinx’ IDE (known as ISE), since the simulation is textual anyhow. Besides, running regression tests without being sure the simulation settings are repeated exactly is a good way to waste time every time the mouse clicks without our full awareness.

Anyhow, my problem was that I instantiated a Xilinx synthesis primitive within one of my modules (a block RAM to be precise) and for some reason, the tools didn’t like it. Here’s my little war story. Spoiler: I won.

This is the original makefile:

SIMNAME=simulation
PLDIRECTORY=../src/PLverilog/

PLSOURCES=bits2alpha trajectory modulator transmitter dualrom67
SOURCES=glbl test_tx $(addprefix $(PLDIRECTORY), $(PLSOURCES))

TOPLEVEL=test_tx 

VERILOGS=$(addsuffix .v, $(SOURCES))
#LIBS=$(addsuffix _lib, $(SOURCES))
#LIBINARG=$(foreach source, $(SOURCES), -lib $(source)_lib)

all:	clean
	vlogcomp $(VERILOGS)
	fuse -top $(TOPLEVEL) -top glbl -o $(SIMNAME).exe
	$(SIMNAME).exe -tclbatch simcommands.tcl

clean:
	rm -f `find . -name "*~"`
	rm -rf isim isim.tmp_save isimwavedata.xwv
	rm -f isim.log $(SIMNAME).exe simulate_dofile.lo*
	rm -f out.*

Running a compilation, all Verilog compilations run properly, but when it’s time for fuse (linker?) I got:

fuse -top test_tx  -top glbl -o simulation.exe
Release 9.2.03i - ISE Simulator Fuse J.39

Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

ERROR:HDLParsers:3482 - Could not resolve instantiated unit RAMB16_S18_S18 in
   Verilog module work/dualrom67 in any library

ERROR:Simulator:198 - Failed when handling dependencies for module test_tx
make: *** [all] Error 2

And yes, I did instantiate a block RAM in one of the modules.  RAMB16_S18_S18 explicitly. Somehow I got the idea that I need to use the unisim library, so I added the “-lib unisim” option to fuse, and got this instead:

fuse -lib unisim -top test_tx  -top glbl -o simulation.exe
Release 9.2.03i - ISE Simulator Fuse J.39

Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

ERROR:Simulator:170 - unisim/VPKG is not compiled properly. Please recompile
   unisim/VPKG in file "" without -incremental option.

ERROR:Simulator:198 - Failed when handling dependencies for module test_tx
make: *** [all] Error 2

What now? There is a VPKG module installed ( {ISE install directory}/vhdl/src/unisims/unisim_VPKG.vhd, namely) but it’s in VHDL. I could compile that one. But I found it much cooler to copy {ISE install directory}/verilog/src/unisims/RAMB16_S18_S18.v into my home directory, and add RAMB16_S18_S18 to the SOURCES in the makefile above (and remove the -lib unisim, of course).

And that did the job.

Lesson learned: Don’t listen to recommendations on error messages (as if that was new). Just copy the model you need.