DCM loses lock on Virtex-4: It’s all about auto calibration

This post was written by eli on October 24, 2009
Posted Under: FPGA,Microsoft,miscellaneous,oddities,Software

The whole story began when I decided to be kind enough to tell the Xilinx tools (ISE 9.2 in my case) that the Virtex-4 I’m targeting is a grown-up. Stepping 2, to be precise. I added

CONFIG STEPPING = "2";

to the UCF file. It must have been one of those moments where I believed that the tools do what is best for me.

It wasn’t long before the mapper told me it’s rewarding me with some autocalibration logic for the DCM. Sounded pretty OK. Some logic that will get the DCM back on its feet if the clock stops and returns. Not that I have any such plans. As a matter of fact, I’ve made sure that the DCM will get a reset after any possible messing with the DCM’s clock input.

Both the mapping warning and the docs mention that it’s possible to disable the autocalibration feature in order to save some logic. They never mentioned that the logic can kill the DCM.

And then one of the DCMs started losing lock. I had changed several other things at the same time, so it wasn’t easy to track down why. But it looked so weird: The DCM’s lock flag would go high, and then go down again. The timescale was tens of milliseconds, which is way beyond the response times  for a DCM.

My first thought was that it must have something to do with the clock’s signal quality. Maybe some crosstalk. The clock was around 200 MHz. But then I decided to look a bit closer on what this autocalibration was about.

That led me to Answer Record #21435, which was pretty explicit about the reset:

When the input clock returns, the user must manually assert the DCM reset for at least 200 ms to resume proper DCM functionality.

200 ms? So there is was. I did mess with the input clock, but then I sent a brief reset signal to the DCM to get it back to normal. It worked in the past. Not with the extra logic. So all I needed to do, was to add

defparam   thedcm.DCM_AUTOCALIBRATION = “FALSE”;

(in the Verilog definition of the DCM) and the problem (which shouldn’t have occured in the first place) was solved.

To make things slightly more annoying, I also had to upgrade the old “DCM” primitives to “DCM_BASE”, because when the “DCM” primitives are upgraded automatically to DCM_ADV’s (by XST),  the DCM_AUTOCALIBRATION parameter set to the default, which is “TRUE”. The same parameter simply doesn’t exist for the backward-compatible “DCM” primitive.

Note to self: Remember to disable the autocalibration on all DCMs from now on.

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