FPGA Editor video tutorial

This post was written by eli on January 1, 2009
Posted Under: FPGA

Having made several FPGA projects for my clients, I’ve learned that most of them are reluctant to use the Xilinx FPGA Editor. While most seem to realize that’s it’s a valuable tool, few really grasp the enormous advantage it offers, in particular when debugging FPGA designs: The possibilities to view the FPGA down to the level of the basic logic elements, as well as making small, yet arbitrary changes, without needing to go through place and route again. This opens for several techniques, which make a huge difference in the frustration of debugging, not to mention time.

Maybe because the documentation is currently somewhat laconic (anyone seen a good user’s reference manual?) most people skip this tool.

The video tutorial presented below should make you friends with the tool. It doesn’t cover nearly all functionality, but focuses on the things you need to get started, and also do a few useful things. It’s a private initiative, so Xilinx are of course not responsible for anything said in it. It was shot in December 2007, showing the tools of ISE 9.2.

Published on Youtube, the tutorial is given in three parts:

Part 1: Introduction

(For a fullscreen view, watch this video directly from Youtube)

Topics covered:

  • Running the FPGA Editor
  • Place and Route, Bitgen, iMPACT and where FPGA Editor fits in
  • Backing up the NCD file
  • The Array window, List window, World window and text window
  • The toolbars
  • The List window: “All Components and All Nets”. Searching
  • The Default Layout of windows
  • The “Editmode” button: Changing to read/write mode
  • The “Attrib” button and “Info” button

Part 2: Using the FPGA Editor

(For a fullscreen view, watch this video directly from Youtube)

This part is a demonstration of how internals can be viewed, and how to make changes in a placed and routed design.

Topics covered:

  • Inside a DCM, parameters, checkboxes and making changes
  • Inside an IOB: Seeing the flip-flop in the IOB, changing drive current strength, slew rate etc.
  • Inside a slice (SLICEL): The LUT’s logic functions, changing the internal routing
  • Briefly: Creating a new net or component
  • Saving the modified design to NCD
  • Creating a bitfile with bitgen

Part 3: Routing any net to a physical pin

(For a fullscreen view, watch this video directly from Youtube)

How to watch any signal within your FPGA design with a regular oscilloscope, almost as easy as in the pre-FPGA times, when all signals were physically exposed on the board.

Topics covered:

  • Opening a second List window
  • Finding the output pin to sacrifice for debugging
  • Disconnecting the output pin from its previous connection
  • Connecting the new net with the “Route” button
  • Routing the net to the IOB with the “Autoroute” button
  • A few words about skews
  • Briefly: About the “Probes” utility
  • Virtex-4 (and newer devices): A possible routing problem

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