Getting the right names in the UCF file: Using netgen

The problem: NGDBUILD tells you it can’t find a net or instance given in the UCF file. It’s likely that the synthesizer changed the names, sometimes slightly and sometimes beyond recognition. You need these names to define a timing group, for example, but how do you know them? Normally, I would get the net and [...]

The PCF file: Xilinx timing constraints as the tools understood them

One of the problems with setting up timing constraints in the UCF file, is to be sure that you got the right elements in, and kept the unnecessary ones out. Suppose I wrote something like NET “the_clock” TNM_NET = “tnm_ctrl_clk”; TIMESPEC “TS_ctrl_clk” = PERIOD “tnm_ctrl_clk” 40 ns HIGH 50 %; What logic element does it [...]

Using Perl to map FPGA pins from a board design to UCF pin constraints

One of the things I try to avoid as an FPGA engineer, is to manually configure the pin constraints (in the UCF file) in order to tell the tools which FPGA pin is connected to what. Not only is this extremely boring, but I also think that getting it done right (at the first go) [...]