Linux Device Tree: What those status = “okay” are about

There are a lot of “okay” assignments in the kernel’s device tree. For example, arch/arm/boot/dts/zynq-zed.dts starts with /dts-v1/; #include “zynq-7000.dtsi” and later on there’s, among others, &sdhci0 { status = “okay”; }; &uart1 { status = “okay”; }; &usb0 { status = “okay”; dr_mode = “host”; usb-phy = <&usb_phy0>; }; Let’s look on the last [...]

Simple GPIO on Zybo using command-line on Linux

Running Xillinux on the Zybo board, this is how I toggled a GPIO pin from a plain one-liner bash script in Linux. The same technique can be used for other Zynq-7000 boards (Zedboard in particular) to easily control GPIO pins. First, I looked up which GPIO pin it is. The pin assignments can be found [...]

Booting Vivado / EDK mixed FSBL on Zynq-7000

Background This is yet another war story about making the FSBL boot on a Zynq processor. I had prepared an FSBL for a certain target using SDK 14.6, and then someone needed it in a Vivado package, using the SDK attached to Vivado 2014.1. In a perfect world, I would have exported the system’s configuration [...]

“Unsupported machine ID” after upgrading Linux kernel or U-boot

Unlike how I usually treat software tools I work with, my attitude towards U-boot is “if it works, never mind how and why”. Trying to understand the gory details of U-boot has never been very rewarding. Things work or break more or less randomly, depending on which git revision is checked out. Someone sent a [...]

Setting up a cross compiler: Buildroot notes

Just a quick summary on how to compile my own cross-compiler in 20 minutes. Download from Buildroot’s home page Run “make xconfig”. The configuration is stored in .config Possibly set BR2_JLEVEL=8 for parallel compilation(even though 0 should just do it right according to the number of processors present) Pick little Endian ARM Cortex-9 for Xillinux [...]

Xilinx “map” tool trimming just a little too much

Sometimes, in particular when working on a relatively new Xilinx device family, the “map” tool fails on several errors like ERROR:MapLib:979 – LUT5 symbol “project/project_core/module/module_empty_user_w_smb_wren_d_O R_201_o_inv1″ (output signal=project/project_core/module/module_empty_user_w_smb_wr en_d_OR_201_o_inv) has input signal “project/project_core/module/module_almostfull_d” which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven [...]

High resolution images of the Zedboard

At times, it’s useful to have a high-resolution picture of the board in front of you. For example, finding the correct place to touch with a probe is easier when the point is first found on the computer screen. These are two very detailed images of the Zedboard by Digilent (and Avnet), which is one [...]

Zynq-7000 EPP: Does it connect with AXI3 or AXI4?

The short answer The P7 ARM processor’s buses run AXI3 It’s not as important as it seems at first The supposed conflict Xilinx have been transferring most of its CoreGen IP cores from all kinds of interfaces to AXI4 over the last few years. With the transaction of Microblaze-related IP cores together with the anticipation [...]

Interrupt definitions in DTS (device tree) files for Xilinx Zynq-7000 / ARM

Having some trouble to figure out what I should write in my own hand-written DTS entry for my logic, I ended up reading the sources of the Linux kernel (version 3.3, which is the currently used for Zynq). The purpose is to hook up a device defined in the PL of a Zynq-7000 (FPGA-style logic [...]

Automatic generation of DTS file for Zedboard/ZC702 (Zynq-7000)

Background Creating a DTS file is a crucial step in integrating a custom peripheral with the Linux kernel. Unfortunately, this subject is rather hazy at the present time, and it’s in particular difficult to obtain that initial DTS to boot the system up with for the first time. It’s important to take the DTS (and [...]