PCIe: Xilinx’ pipe_clock module and its timing constraints

Introduction In several versions of Xilinx’ wrapper for the integrated PCIe block, it’s the user application logic’s duty to instantiate the module which generates the “pipe clock”. It typically looks something like this: pcie_myblock_pipe_clock # ( .PCIE_ASYNC_EN ( “FALSE” ), // PCIe async enable .PCIE_TXBUF_EN ( “FALSE” ), // PCIe TX buffer enable for Gen1/Gen2 [...]

Vivado: Finding the “maximal frequency” after synthesis

Motivation Somewhere at the bottom of ISE’s xst synthesizer’s report, it says what the maximal frequency is, along with an outline the slowest path. This is a rather nice feature, in particular when attempting to optimize a specific module. There is no such figure given after a regular Vivado synthesis, possibly because the guys at [...]

Vivado HLS and the “no function body” error: Using a C++ function in plain C code

It’s quite well-known, that in order to call a function in C, which has been compiled in a C++ source file, there’s need for an extern “C” statement. So if this appears on a C++ source file: void my_puts(const char *str) { … } and there’s an attempt to call my_puts() in a plain C [...]

Vivado’s component.xml: IP-XACT dissection jots

These are a few jots I wrote down as I wrote some code that generates component.xml files automatically. The XML convention of this file IP-XACT format, a specification by the SPIRIT Consortium which can be downloaded free from IEEE. The “spirit:” prefixes all over the XML file indicates that the keywords are defined in the [...]

Under the hood of Vivado runs: Some scripting essentials

Introduction My motivation for looking inside Vivado runs was that I wanted to implement a Vivado project from within XEmacs, using the Compile button, and all that within a rather tangled Makefile-based build system. But I also wanted to leave the possibility to open the project using Vivado’s GUI, if something went wrong or needed [...]

Vivado 2014.1 eliminating instantiations of IP (black boxes)

I discovered this problem in a project that instantiated a 512-bit wide FIFO consisting many (>16) times in different modules. For some unknown reason (it’s called a bug, I suppose) Vivado treated the instantiation as if it wasn’t there, and optimized all surrounding logic as if the black box’ output ports were all zero. For [...]

Vivado 2014.1 / Linux Ubuntu 14.04 license activation notes

Introduction After installing Vivado 2014.1 on my laptop running Ubuntu 14.04 (64 bits), I went for license activation. All I wanted was a plain node-locked license. Not a server, and not a floating one. Baseline. Xilinx abandoned the good old certificate licensing in favor of activation licensing. That is causing some headaches lately… Going through [...]

Vivado: Random notes about the XDC constraints file

These are a few jots about constraining in Vivado. With no particular common topic, and in no particular order. Note that I have another post on similar topics. Setting the default IOSTANDARD for all ports In a design where all ports have the same IOSTANDARD, it’s daunting to set them for all. So if there’s [...]

Manually installing launcher icons for Xilinx tools on a Gnome desktop

So I installed Vivado on my Centos 6.5 64-bit Linux machine, and even though it promised to install icons on my desktop, it didn’t. This is how I installed them manually. There is surely a simpler way, as the special launch bash scripts I created must be somewhere. But I didn’t bother looking. So it [...]

Booting Vivado / EDK mixed FSBL on Zynq-7000

Background This is yet another war story about making the FSBL boot on a Zynq processor. I had prepared an FSBL for a certain target using SDK 14.6, and then someone needed it in a Vivado package, using the SDK attached to Vivado 2014.1. In a perfect world, I would have exported the system’s configuration [...]