PCIe: Xilinx’ pipe_clock module and its timing constraints

Introduction In several versions of Xilinx’ wrapper for the integrated PCIe block, it’s the user application logic’s duty to instantiate the module which generates the “pipe clock”. It typically looks something like this: pcie_myblock_pipe_clock # ( .PCIE_ASYNC_EN ( “FALSE” ), // PCIe async enable .PCIE_TXBUF_EN ( “FALSE” ), // PCIe TX buffer enable for Gen1/Gen2 [...]

PCIe over fiber optics notes (using SFP+)

General As part of a larger project, I was required to set up a PCIe link between a host and some FPGAs through a fiber link, in order to ensure medical-grade electrical isolation of a high-bandwidth video data link + allow for control over the same link. These are a few jots on carrying a [...]

Gigabit tranceivers on FPGA: Selected topics

Introduction This is a summary of a few topics that should to be kept in mind when a Multi-Gigabit Tranceiver (MGT) is employed in an FPGA design. It’s not a substitute for reading the relevant user guide, nor a tutorial. Rather, it’s here to point at issues that may not be obvious at first glance. [...]

Using Linux’ setpci to program an EEPROM attached to an PLX / Avago PCIe switch

Introduction These are my notes as I programmed an Atmel AT25128 EEPROM, attached to a PEX 8606 PCIe switch, using PCIe configuration-space writes only (that is, no I2C / SMBus cable). This is frankly quite redundant, as Avago supplies software tools for doing this. In fact, in order to get their tools, register at Avago’s [...]

Linux kernel hack for calming down a flood of PCIe AER messages

While working on a project involving a custom PCIe interface, Linux’ message log became flooded with messages like pcieport 0000:00:1c.6: device [8086:a116] error status/mask=00001081/00002000 pcieport 0000:00:1c.6: [ 0] Receiver Error pcieport 0000:00:1c.6: [ 7] Bad DLLP pcieport 0000:00:1c.6: [12] Replay Timer Timeout pcieport 0000:00:1c.6: Error of this Agent(00e6) is reported first pcieport 0000:02:00.0: PCIe Bus [...]

Getting the PCIe of Avnet S6LX150T Development Kit detected

About a year ago, I had a client failing to get the PCIe working on an Avnet LX150T development board. Despite countless joint efforts, we failed to get the card detected as a PCIe device by the computer. A recent comment from another client supplied the clue: The user guide (which I downloaded recently from [...]

Altera’s IP compiler for PCI express, and how to survive it

This is the good news: Xillybus is now supporting Altera FPGAs having the hard IP transceiver for PCI Express (and other Gigabit interfaces). If you’re into PCI Express, and into a fairly recent project, odds are that your device is on the list. There is, of course, the possibility to handle the Avalon-ST interface by [...]

List of FPGA boards and IP cores with PCIe/USB and their vendors

I collected some links for my own use (limiting myself to Virtex-5 and later Xilinx FPGAs). Maybe this can help someone else too. This is by no means a complete list, but additions and corrections are welcome in the comment section below (I may delete your comment and update the list, don’t take it personally). [...]

An FPGA-based PCI Express peripheral for Windows: It’s easy

To make a long story short… There is really no need to work hard to make your FPGA talk with a PC.  Xillybus gives you the end-to-end connection interfacing FPGAs with both Linux and Windows computers. The challenge At times, FPGA engineers are faced with the need to transfer data to or from a regular [...]

Virtex-5 PCIe endpoint block plus: Stay away from v1.15

While porting Xillybus to Virtex-5, I ran into nasty trouble. In the beginning, it looked like the MSI interrupt delivery mechanism was wrong, and then it turned out that the core gets locked up completely after a few packets, and refuses to send any TLPs after a few sent. I also noticed that the PCIe [...]