Altera ECPQ flash access with a Nios II processor + programming bitfiles

Introduction This post outlines some technical details on accessing an Altera ECPQ flash from a Nios II processor for read, write and erase. A non-OS settings (“bare metal”) setting is assumed. And as a bonus (at the bottom of this post), how to program the flash based upon a SOF file. Hardware setup In the [...]

XEmacs / VHDL: Stop that annoying “assistance” while typing

Emacs’ (and hence XEmacs’) VHDL mode has an annoying thing about hopping in and “help me” with composing code. Type “if” and it tells me I need to add an expression. Thanks. I wouldn’t have figured it out myself. So here’s how to disable this annoyance: Add in~/.xemacs/custom.el, to the custom-set-variables clause ‘(vhdl-electric-mode nil) ‘(vhdl-stutter-mode [...]

Quartus’ timing analysis on set_input_delay and set_output_delay constraints

OK, what’s this? This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints. TimeQuest (Quartus’ timing analyzer) performs a four-corner check (max/min temperature, max/min voltage) and picks the worst slack. In the examples below, the worst case of these four corners is shown. It’s [...]

Vivado’s timing analysis on set_input_delay and set_output_delay constraints

OK, what’s this? This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints. As mentioned on the other post, the relevant timing constraints were: create_clock -name theclk -period 20 [get_ports test_clk] set_output_delay -clock theclk -max 8 [get_ports test_out] set_output_delay -clock theclk -min -3 [get_ports [...]

Meaning of set_input_delay and set_output_delay in SDC timing constraints

Introduction Synopsys Design Constraints (SDC) has been adopted by Xilinx (in Vivado, as .xdc files) as well as Altera (in Quartus, as .sdc files) and other FPGA vendors as well. Despite the wide use of this format, there seems to be some confusion regarding the constraints for defining I/O timing. This post is defines what [...]

Quartus: Packing registers into I/O cells

Often I prefer to handle I/O timing simply by ensuring that all registers are pushed into the I/O cells. Where timing matters, that is. It seems like I/O register packing isn’t the default in Quartus. Anyhow, here’s the lazy man’s recipe for this scenario. First, disable timing checking on all I/Os. This will silence the [...]

PCIe: Xilinx’ pipe_clock module and its timing constraints

Introduction In several versions of Xilinx’ wrapper for the integrated PCIe block, it’s the user application logic’s duty to instantiate the module which generates the “pipe clock”. It typically looks something like this: pcie_myblock_pipe_clock # ( .PCIE_ASYNC_EN ( “FALSE” ), // PCIe async enable .PCIE_TXBUF_EN ( “FALSE” ), // PCIe TX buffer enable for Gen1/Gen2 [...]

Vivado: Finding the “maximal frequency” after synthesis

Motivation Somewhere at the bottom of ISE’s xst synthesizer’s report, it says what the maximal frequency is, along with an outline the slowest path. This is a rather nice feature, in particular when attempting to optimize a specific module. There is no such figure given after a regular Vivado synthesis, possibly because the guys at [...]

Vivado HLS and the “no function body” error: Using a C++ function in plain C code

It’s quite well-known, that in order to call a function in C, which has been compiled in a C++ source file, there’s need for an extern “C” statement. So if this appears on a C++ source file: void my_puts(const char *str) { … } and there’s an attempt to call my_puts() in a plain C [...]

PCIe over fiber optics notes (using SFP+)

General As part of a larger project, I was required to set up a PCIe link between a host and some FPGAs through a fiber link, in order to ensure medical-grade electrical isolation of a high-bandwidth video data link + allow for control over the same link. These are a few jots on carrying a [...]