Test point placement constraints for KC705

The said board, which is Xilinx’ official development kit for Kintex-7, has an LCD which can be taken off. Its pins can then be used as plain testpoints for logic. These are the placement constraint for this use (Vivado XDC style): set_property PACKAGE_PIN Y10 [get_ports tp[0]]; # LCD_DB7, pin 1 set_property PACKAGE_PIN AA11 [get_ports tp[1]]; [...]

Ultrascale GTH transceivers: Advanced doesn’t necessarily mean better

Introduction I tend to naturally assume that newer FPGAs will perform better in basically everything, and that the heavier hammers are always better. Specifically, I expect the GTX / GTH / GT-whatever to perform better with the newer FPGAs (not just higher rates, but simply work better) and that their equalizers will be able to [...]

Setting up Si5324/Si5328 on Xilinx development boards

General These are my notes as I set up the jitter attenuator devices (Silicon Labs’ Si5324 and Si5328) on Xilinx development boards as clean clock sources for use with MGTs. As such, this post isn’t all that organized. I suppose that the reason Xilinx put a jitter attenuator to drive the SFP+ related reference clock, [...]

Xilinx Ultrascale / Ultrascale+ GTH/GTY CPLL calibration

… or why does my GTH/GTY not come out of reset? Why are those reset_rx_done / reset_tx_done never asserted after a reset_all or a reset involving the CPLLs? What’s this CPLL calibration thing about? It turns out that some GTH/GTY’s on Ultrascale and Ultrascale+ FPGAs have problems with getting the CPLL to work reliably. I’ll [...]

Installing Vivado 2020.1 on Linux Mint 19

… or any other “unsupported” Linux distribution. … or: How to trick the installer into thinking you’re running one of the supported OSes. So I wanted to install Vivado 2020.1 on my Linux Mint 19 (Tara) machine. I downloaded the full package, and ran xsetup. A splash window appeared, and soon after it another window [...]

Intel FPGA’s Stratix 10: My impressions and notes

Introduction These are a few random things I wrote down as I worked with the Stratix 10 Development Kit, with focus on its PCIe interface. Quite obviously, it’s mostly about things I found noteworthy about this specific FPGA and its board, compared with previous hardware I’ve encountered. Generally speaking, Stratix 10 is not for the [...]

Intel Stratix 10 PCIe IP: Building it only appears to be stuck

These are a few notes when implementing an FPGA design for Stratix 10 with a Makefile flow (i.e. command-line utilities) with Quartus 19.2. So I wanted was to implement a design including the PCIe 16x block for Stratix 10. I added a line going set_global_assignment -name IP_FILE pcie_s10_16x.ip in the relevant QSF file. And by [...]

Intel / Altera: Proper access of the Configuration Space Registers (tl_cfg_ctl)

Introduction The PCIe blocks on Intel (formerly Altera) FPGAs have a somewhat peculiar, yet useful interface for exposing some of the interface’s configuration information, called “Transaction Layer Configuration”. For the purposes of this post, it consists of two output signals, tl_cfg_add[3:0] and tl_cfg_ctl[31:0]. Both are driven by the PCIe block, and clocked by the same [...]

USB 3.0 device compliance test notes

Introduction While implementing Xillybus‘ USB 3.0 general purpose IP core for FPGAs, I found the USB Implementers Forum’s compliance tool handy, yet somewhat quirky, for verifying I got things right. It was USB3CV version, running on Windows 10 @32 bit. The 64 bit version works the same (I’ve tested it as well). A GPLed [...]

Solved: Kintex-7 / KC705: MiG DDR3 fails to calibrate

As I implemented a MiG controller for KC705′s on-board SODIMM, the controller failed to calibrate at first. Despite that I’ve copied the instantiation and port connections from the example design. As for the pin placement, this was taken care of by the core itself, by virtue of memctl/memctl/user_design/constraints/memctl.xdc within MiG’s dedicated directory (which I called [...]