PCIe on Cyclone 10 GX: Data loss on DMA writes by FPGA

TL;DR DMA writes from a Cyclone 10 GX PCIe interface may be lost, probably due to a path that isn’t timed properly by the fitter. This has been observed with Quartus Prime Version 17.1.0 Build 240 SJ Pro Edition, and the official Cyclone 10 GX development board. A wider impact is likely, possibly on Arria [...]

Quartus / Linux: Programming the FPGA with command-line

Command-line? Yes, it much more convenient than the GUI programmer. Programming an FPGA is a repeated task, always the same file to the same FPGA on the same board connected to the computer. And somehow the GUI programming tools turn it into a daunting ceremony (and sometimes even a quiz, when it can’t tell exactly [...]

Quartus / sdc: Constraining I/O ports clocked by an internal clock

Introduction This post is an expansion for another post of mine, which deals with register I/O packing. It’s recommended reading that one first. Timing constraining of I/O ports is typically intended to ensure timing relations between an external clock and the timing of signals that are clocked by this clock (or derived from this clock, [...]

Synplify Pro on Linux Mint 18.1: The cheat sheet

Introduction I needed to run Synplify Pro for a short trial period on my Fedora 12 machine (yup, it’s 2018, and still). And I have a full Mint 18.1 as a chroot jail on that machine for installing contemporary software. So these are my notes on the go. Consider everything below as run om Mint [...]

Cyclone V and some transceiver CDR/PLL parameters

Introduction Connecting an Intel FPGA (Altera) Cyclone V’s Native Transceiver IP to a USB 3.0 channel (which involves a -5000 ppm Spread Spectrum modulation), I got a significant bit error rate and what appeared to be occasional losses of lock. Suspecting that the CDR didn’t catch up with the frequency modulation, I wanted to try [...]

Quartus, timing closure: Obtaining a concise multi-corner timing path report

Introduction The natural thing to do when an FPGA design fails timing is to take a detailed look at the critical paths, based upon a timing report showing the logic elements and their delays of this path. If you’re not a heavy user of Intel’s FPGAs (a.k.a. Altera), it may not be so trivial to [...]

Making any IP in the IP Catalog availabe in QSys

Introduction I needed the Cyclone V Transceiver Native PHY IP Core inside QSys. Why? Actually, part of a failed attempt to find solve a compilation error. The IP is available in Quartus 15.1′s IP Catalog, but inside the same toolkit’s QSys it doesn’t appear in the list of IPs. As discussed in this forum thread, [...]

Combining PCIe and Gigabit Transceiver on Cyclone V

Overview The goal: Using one of the PCIe transceivers for something else on a Cyclone V GT FPGA Development Kit Board, while keeping the PCIe link (narrowing it down from 4x to 2x). This allows allocating some other logic to the transceiver that goes to the PCIe finger, and do the bifurcation with a PCIe [...]

QDB vs. QXP, Quartus Pro vs. Standard: Post-synthesis packaging of an IP core

Introduction It’s often desired to package an piece of FPGA logic in a post-synthesis (netlist) format for later use in another project. IP core vendors often deliver their products as netlists, partly to protect themselves from unauthorized copying and use, and partly to ensure that possible bugs in the end-user’s synthesizer don’t influence the product [...]

Using Verilog “initial” blocks for FPGA synthesis: Legit? Portable?

Introduction Ask an VLSI engineer if the Verilog “initial” keyword is legit for synthesis, and flames of fury will go your way. However in the FPGA world, it’s a portable way to assign registers and array with the initial (and possibly constant) values immediately after configuration. The main argument against this practice is that a [...]