USB 3.0 device compliance test notes

Introduction While implementing Xillybus‘ USB 3.0 general purpose IP core for FPGAs, I found the USB Implementers Forum’s compliance tool handy, yet somewhat quirky, for verifying I got things right. It was USB3CV version 2.1.12.1, running on Windows 10 @32 bit. The 64 bit version works the same (I’ve tested it as well). A GPLed [...]

Solved: Kintex-7 / KC705: MiG DDR3 fails to calibrate

As I implemented a MiG controller for KC705′s on-board SODIMM, the controller failed to calibrate at first. Despite that I’ve copied the instantiation and port connections from the example design. As for the pin placement, this was taken care of by the core itself, by virtue of memctl/memctl/user_design/constraints/memctl.xdc within MiG’s dedicated directory (which I called [...]

Linux: When Vivado’s GUI doesn’t start with an error on locale

Trying to running Vivado 2017.3 with GUI and all on a remote host with X forwarding, i.e. $ ssh -X mycomputer setting the environment with $ . /path/to/Vivado/2017.3/settings64.sh it failed with $ vivado & terminate called after throwing an instance of ‘std::runtime_error’ what(): locale::facet::_S_create_c_locale name not valid Now here’s the odd thing: The error message [...]

Xilinx’ Zynq Z007s: Is it really single core?

Introduction Xilinx’ documentation says that XC7Z007S, among other “S” devices, is a single-core device, as opposed to, for example, its older brother XC7Z010, which is dual-core. So I compared several aspects of the PS part of a Z007S vs. Z010, and to my astonishment, I found that Z007S is exactly the same: Two CPUs are [...]

Quartus: The importance of derive_pll_clocks in the SDC file

Introduction Whenever a PLL is used in a design to generate one clock from another, it’s quite common to expect the timing tools to figure out the frequencies and timing relations between the different clocks. With Intel’s Quartus tools, this isn’t the case by default. A derive_pll_clocks command is required in the SDC constraints file [...]

PCIe on Cyclone 10 GX: Data loss on DMA writes by FPGA

TL;DR DMA writes from a Cyclone 10 GX PCIe interface may be lost, probably due to a path that isn’t timed properly by the fitter. This has been observed with Quartus Prime Version 17.1.0 Build 240 SJ Pro Edition, and the official Cyclone 10 GX development board. A wider impact is likely, possibly on Arria [...]

Quartus / Linux: Programming the FPGA with command-line

Command-line? Yes, it much more convenient than the GUI programmer. Programming an FPGA is a repeated task, always the same file to the same FPGA on the same board connected to the computer. And somehow the GUI programming tools turn it into a daunting ceremony (and sometimes even a quiz, when it can’t tell exactly [...]

Quartus / sdc: Constraining I/O ports clocked by an internal clock

Introduction This post is an expansion for another post of mine, which deals with register I/O packing. It’s recommended reading that one first. Timing constraining of I/O ports is typically intended to ensure timing relations between an external clock and the timing of signals that are clocked by this clock (or derived from this clock, [...]

Synplify Pro on Linux Mint 18.1: The cheat sheet

Introduction I needed to run Synplify Pro for a short trial period on my Fedora 12 machine (yup, it’s 2018, and still). And I have a full Mint 18.1 as a chroot jail on that machine for installing contemporary software. So these are my notes on the go. Consider everything below as run om Mint [...]

Cyclone V and some transceiver CDR/PLL parameters

Introduction Connecting an Intel FPGA (Altera) Cyclone V’s Native Transceiver IP to a USB 3.0 channel (which involves a -5000 ppm Spread Spectrum modulation), I got a significant bit error rate and what appeared to be occasional losses of lock. Suspecting that the CDR didn’t catch up with the frequency modulation, I wanted to try [...]