Quartus Pro 19.2: List of QSF parameter names

Due to rather peculiar reasons described in this post, I found myself looking for all QSF parameter names that Quartus recognizes. I ended up searching a binary file in Quartus’ installation directory. So this is by no means an authoritative list, but since I made it, I thought I should post it. Just in case [...]

Quartus 17.1 (non-pro): List of QSF parameter names

Due to rather peculiar reasons described in this post, I found myself looking for all QSF parameter names that Quartus recognizes. I ended up searching a binary file in Quartus’ installation directory. So this is by no means an authoritative list, but since I made it, I thought I should post it. Just in case [...]

Reverse engineering Cyclone 10 transceiver’s attributes

Introduction This post summarizes some scattered findings I made while trying to make a Cyclone 10′s signal detect feature work properly for detecting a SuperSpeed USB LFPS signal. As it turned out, Cyclone 10′s transceiver isn’t capable of this, as explained below. But since the documentation on this issue was lacking, I resorted to reverse [...]

Critical Warnings after upgrading a PCIe block for Ultrascale+ on Vivado 2020.1

Introduction Checking Xillybus’ bundle for Kintex Ultrascale+ on Vivado 2020.1, I got several critical warnings related to the PCIe block. As the bundle is intended to show how Xillybus’ IP core is used for simplifying communication with the host, these warnings aren’t directly related, and yet they’re unacceptable. This bundle is designed to work with [...]

Running Xilinx Impact on Linux Mint 19

Introduction This is my short war story as I made Xilinx’ Impact, part of ISE 14.7, work on a Linux Mint 19 machine with a v4.15 Linux kernel. I should mention that I already use Vivado on the same machine, so the whole JTAG programming thing was already sorted out, including loading firmware into the [...]

FPGA + USB 3.0: Cypress EZ-USB FX3 or XillyUSB?

Introduction As the title implies, this post compares two solutions for connecting an FPGA to a host via USB 3.0: Cypress’ FX3 chipset, which has been around since around 2010, and the XillyUSB IP core, which was released in November 2020. Cypress has been acquired by Infineon, but I’ll stick with Cypress. It’s not clear [...]

Test point placement constraints for KC705

The said board, which is Xilinx’ official development kit for Kintex-7, has an LCD which can be taken off. Its pins can then be used as plain testpoints for logic. These are the placement constraint for this use (Vivado XDC style): set_property PACKAGE_PIN Y10 [get_ports tp[0]]; # LCD_DB7, pin 1 set_property PACKAGE_PIN AA11 [get_ports tp[1]]; [...]

Ultrascale GTH transceivers: Advanced doesn’t necessarily mean better

Introduction I tend to naturally assume that newer FPGAs will perform better in basically everything, and that the heavier hammers are always better. Specifically, I expect the GTX / GTH / GT-whatever to perform better with the newer FPGAs (not just higher rates, but simply work better) and that their equalizers will be able to [...]

Setting up Si5324/Si5328 on Xilinx development boards

General These are my notes as I set up the jitter attenuator devices (Silicon Labs’ Si5324 and Si5328) on Xilinx development boards as clean clock sources for use with MGTs. As such, this post isn’t all that organized. I suppose that the reason Xilinx put a jitter attenuator to drive the SFP+ related reference clock, [...]

Xilinx Ultrascale / Ultrascale+ GTH/GTY CPLL calibration

… or why does my GTH/GTY not come out of reset? Why are those reset_rx_done / reset_tx_done never asserted after a reset_all or a reset involving the CPLLs? What’s this CPLL calibration thing about? It turns out that some GTH/GTY’s on Ultrascale and Ultrascale+ FPGAs have problems with getting the CPLL to work reliably. I’ll [...]