Gtkwave notes

General Gtkwave is a simple and convenient viewer of electronic waveforms. It’s a free software tool at its best: A bit rough to start working with, but after a while it becomes clear that the decisions have been made by someone who uses the tool himself. Really recommended. So here are my jumpstart notes for [...]

Notes on USB 1.1 low-level protocol for FPGA implementation

Introduction These are the consideration and design decisions I took when designing a transparent hub for low- and full-speed USB (that is, all covered by USB 1.1, and not high-speed as required by USB 2.0). A transparent 1:1 hub is a device with one male USB plug, and one female plug. It basically substitutes an [...]

Altera NIOS II jots

About this post These are things I wrote down at different stages of introducing myself to Nios II and its environment. Nothing really consistent nor necessarily the right way to do things. Jots Open Qsys. Follow this post. Went for Nios II classic, used Nios/e (no Hardware multiplication, as the target device doesn’t have it. [...]

Remote Update from ECPQ flash on Altera Cyclone IV

Introduction This post relates to Altera (or should I say Intel FPGA?) Cyclone IV FPGAs loaded from an ECPQ flash in Active Serial x 1 (AS x 1) mode. Things written below are probably relevant to other Altera FPGAs as well, but keep in mind that Cyclone IV FPGAs have several peculiarities you won’t find [...]

Quartus/Linux: Setting PATH and environment for command-line

The classic way: $ export QUARTUS_ROOTDIR=/path/to/altera/15.1/quartus $ . $QUARTUS_ROOTDIR/adm/qenv.sh Or open a shell (will set path, but not a full environment): $ /path/to/altera/15.1/nios2eds/nios2_command_shell.sh This is good for compiling for NIOS etc.

Altera ECPQ flash access with a Nios II processor + programming bitfiles

Introduction This post outlines some technical details on accessing an Altera ECPQ flash from a Nios II processor for read, write and erase. A non-OS settings (“bare metal”) setting is assumed. And as a bonus (at the bottom of this post), how to program the flash based upon a SOF file, both with JTAG and [...]

XEmacs / VHDL: Stop that annoying “assistance” while typing

Emacs’ (and hence XEmacs’) VHDL mode has an annoying thing about hopping in and “help me” with composing code. Type “if” and it tells me I need to add an expression. Thanks. I wouldn’t have figured it out myself. So here’s how to disable this annoyance: Add in~/.xemacs/custom.el, to the custom-set-variables clause ‘(vhdl-electric-mode nil) ‘(vhdl-stutter-mode [...]

Quartus’ timing analysis on set_input_delay and set_output_delay constraints

OK, what’s this? This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints. TimeQuest (Quartus’ timing analyzer) performs a four-corner check (max/min temperature, max/min voltage) and picks the worst slack. In the examples below, the worst case of these four corners is shown. It’s [...]

Vivado’s timing analysis on set_input_delay and set_output_delay constraints

OK, what’s this? This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints. As mentioned on the other post, the relevant timing constraints were: create_clock -name theclk -period 20 [get_ports test_clk] set_output_delay -clock theclk -max 8 [get_ports test_out] set_output_delay -clock theclk -min -3 [get_ports [...]

Meaning of set_input_delay and set_output_delay in SDC timing constraints

Introduction Synopsys Design Constraints (SDC) has been adopted by Xilinx (in Vivado, as .xdc files) as well as Altera (in Quartus, as .sdc files) and other FPGA vendors as well. Despite the wide use of this format, there seems to be some confusion regarding the constraints for defining I/O timing. This post is defines what [...]