“Unsupported machine ID” after upgrading Linux kernel or U-boot

Unlike how I usually treat software tools I work with, my attitude towards U-boot is “if it works, never mind how and why”. Trying to understand the gory details of U-boot has never been very rewarding. Things work or break more or less randomly, depending on which git revision is checked out. Someone sent a [...]

Linux kernel platform device food chain example

Since the device tree is the new way to set up hardware devices on embedded platforms, I hoped that I could avoid the “platform” API for picking which driver is going to take control over what. But it looks like the /arch/arm disaster is here to stay for a while, so I need to at [...]

Cache coherency on i.MX25 running Linux

What this blob is all about Running some home-cooked SDMA scripts on Freescale’s Linux 2.6.28 kernel on an i.MX25 processor, I’m puzzled by the fact, that cache flushing with dma_map_single(…, DMA_TO_DEVICE) doesn’t hurt, but nothing happens if the calls are removed. On the other hand, attempting to remove cache invalidation calls, as in dma_map_single(…, DMA_FROM_DEVICE) [...]

stmmaceth: NetworkManager fails to bring up a wired Ethernet NIC

The problem In short: Running linux 3.8.0 on Altera’s Cyclone V SoC, NetworkManager doesn’t bring up the Ethernet port. It also makes false accusations such as Jan 1 00:00:17 localhost NetworkManager[1206]: <info> (eth0): driver ‘stmmaceth’ does not support carrier detection. and later on also says Jan 1 00:00:17 localhost NetworkManager[1206]: <warn> (eth0): couldn’t get carrier [...]

Cyclone V SoC: Two masters on a bus errs on ID signal width

While working on Xillinux‘ port to Altera (the SocKit board, actually), I needed to connect two AXI masters: One for the VGA adapter, and one for the Xillybus IP core. Unlike Zynq, Altera’s HPS offers only one AXI slave port, so it’s up to Qsys to generate arbitration logic, implemented in the logic fabric, to [...]

Setting up a cross compiler: Buildroot notes

Just a quick summary on how to compile my own cross-compiler in 20 minutes. Download from Buildroot’s home page Run “make xconfig”. The configuration is stored in .config Possibly set BR2_JLEVEL=8 for parallel compilation(even though 0 should just do it right according to the number of processors present) Pick little Endian ARM Cortex-9 for Xillinux [...]

DHCP changing the IP address suddenly on embedded systems

The problem It first seemed extremely odd: The IP address of my embedded Linux machine changed suddenly after a few hours, breaking the ssh connection I had up, and messing up the NFS mount. The problem turned out to be the lack of a hardware clock (RTC) on the board + clock being updated with [...]

Zynq-7000 EPP: Does it connect with AXI3 or AXI4?

The short answer The P7 ARM processor’s buses run AXI3 It’s not as important as it seems at first The supposed conflict Xilinx have been transferring most of its CoreGen IP cores from all kinds of interfaces to AXI4 over the last few years. With the transaction of Microblaze-related IP cores together with the anticipation [...]

Interrupt definitions in DTS (device tree) files for Xilinx Zynq-7000 / ARM

Having some trouble to figure out what I should write in my own hand-written DTS entry for my logic, I ended up reading the sources of the Linux kernel (version 3.3, which is the currently used for Zynq). The purpose is to hook up a device defined in the PL of a Zynq-7000 (FPGA-style logic [...]

Automatic generation of DTS file for Zedboard/ZC702 (Zynq-7000)

Background Creating a DTS file is a crucial step in integrating a custom peripheral with the Linux kernel. Unfortunately, this subject is rather hazy at the present time, and it’s in particular difficult to obtain that initial DTS to boot the system up with for the first time. It’s important to take the DTS (and [...]