Cyclone V and some transceiver CDR/PLL parameters

Introduction Connecting an Intel FPGA (Altera) Cyclone V’s Native Transceiver IP to a USB 3.0 channel (which involves a -5000 ppm Spread Spectrum modulation), I got a significant bit error rate and what appeared to be occasional losses of lock. Suspecting that the CDR didn’t catch up with the frequency modulation, I wanted to try [...]

Quartus, timing closure: Obtaining a concise multi-corner timing path report

Introduction The natural thing to do when an FPGA design fails timing is to take a detailed look at the critical paths, based upon a timing report showing the logic elements and their delays of this path. If you’re not a heavy user of Intel’s FPGAs (a.k.a. Altera), it may not be so trivial to [...]

Making any IP in the IP Catalog availabe in QSys

Introduction I needed the Cyclone V Transceiver Native PHY IP Core inside QSys. Why? Actually, part of a failed attempt to find solve a compilation error. The IP is available in Quartus 15.1′s IP Catalog, but inside the same toolkit’s QSys it doesn’t appear in the list of IPs. As discussed in this forum thread, [...]

Combining PCIe and Gigabit Transceiver on Cyclone V

Overview The goal: Using one of the PCIe transceivers for something else on a Cyclone V GT FPGA Development Kit Board, while keeping the PCIe link (narrowing it down from 4x to 2x). This allows allocating some other logic to the transceiver that goes to the PCIe finger, and do the bifurcation with a PCIe [...]

QDB vs. QXP, Quartus Pro vs. Standard: Post-synthesis packaging of an IP core

Introduction It’s often desired to package an piece of FPGA logic in a post-synthesis (netlist) format for later use in another project. IP core vendors often deliver their products as netlists, partly to protect themselves from unauthorized copying and use, and partly to ensure that possible bugs in the end-user’s synthesizer don’t influence the product [...]

Altera NIOS II jots

About this post These are things I wrote down at different stages of introducing myself to Nios II and its environment. Nothing really consistent nor necessarily the right way to do things. Jots Open Qsys. Follow this post. Went for Nios II classic, used Nios/e (no Hardware multiplication, as the target device doesn’t have it. [...]

Remote Update from ECPQ flash on Altera Cyclone IV

Introduction This post relates to Altera (or should I say Intel FPGA?) Cyclone IV FPGAs loaded from an ECPQ flash in Active Serial x 1 (AS x 1) mode. Things written below are probably relevant to other Altera FPGAs as well, but keep in mind that Cyclone IV FPGAs have several peculiarities you won’t find [...]

Quartus/Linux: Setting PATH and environment for command-line

The classic way: $ export QUARTUS_ROOTDIR=/path/to/altera/15.1/quartus $ . $QUARTUS_ROOTDIR/adm/ Or open a shell (will set path, but not a full environment): $ /path/to/altera/15.1/nios2eds/ This is good for compiling for NIOS etc.

Altera ECPQ flash access with a Nios II processor + programming bitfiles

Introduction This post outlines some technical details on accessing an Altera ECPQ flash from a Nios II processor for read, write and erase. A non-OS settings (“bare metal”) setting is assumed. And as a bonus (at the bottom of this post), how to program the flash based upon a SOF file, both with JTAG and [...]

Quartus’ timing analysis on set_input_delay and set_output_delay constraints

OK, what’s this? This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints. TimeQuest (Quartus’ timing analyzer) performs a four-corner check (max/min temperature, max/min voltage) and picks the worst slack. In the examples below, the worst case of these four corners is shown. It’s [...]