Quartus Pro 19.2: List of QSF parameter names

Due to rather peculiar reasons described in this post, I found myself looking for all QSF parameter names that Quartus recognizes. I ended up searching a binary file in Quartus’ installation directory. So this is by no means an authoritative list, but since I made it, I thought I should post it. Just in case [...]

Quartus 17.1 (non-pro): List of QSF parameter names

Due to rather peculiar reasons described in this post, I found myself looking for all QSF parameter names that Quartus recognizes. I ended up searching a binary file in Quartus’ installation directory. So this is by no means an authoritative list, but since I made it, I thought I should post it. Just in case [...]

Reverse engineering Cyclone 10 transceiver’s attributes

Introduction This post summarizes some scattered findings I made while trying to make a Cyclone 10′s signal detect feature work properly for detecting a SuperSpeed USB LFPS signal. As it turned out, Cyclone 10′s transceiver isn’t capable of this, as explained below. But since the documentation on this issue was lacking, I resorted to reverse [...]

Intel FPGA’s Stratix 10: My impressions and notes

Introduction These are a few random things I wrote down as I worked with the Stratix 10 Development Kit, with focus on its PCIe interface. Quite obviously, it’s mostly about things I found noteworthy about this specific FPGA and its board, compared with previous hardware I’ve encountered. Generally speaking, Stratix 10 is not for the [...]

Intel Stratix 10 PCIe IP: Building it only appears to be stuck

These are a few notes when implementing an FPGA design for Stratix 10 with a Makefile flow (i.e. command-line utilities) with Quartus 19.2. So I wanted was to implement a design including the PCIe 16x block for Stratix 10. I added a line going set_global_assignment -name IP_FILE pcie_s10_16x.ip in the relevant QSF file. And by [...]

Intel / Altera: Proper access of the Configuration Space Registers (tl_cfg_ctl)

Introduction The PCIe blocks on Intel (formerly Altera) FPGAs have a somewhat peculiar, yet useful interface for exposing some of the interface’s configuration information, called “Transaction Layer Configuration”. For the purposes of this post, it consists of two output signals, tl_cfg_add[3:0] and tl_cfg_ctl[31:0]. Both are driven by the PCIe block, and clocked by the same [...]

Quartus: The importance of derive_pll_clocks in the SDC file

Introduction Whenever a PLL is used in a design to generate one clock from another, it’s quite common to expect the timing tools to figure out the frequencies and timing relations between the different clocks. With Intel’s Quartus tools, this isn’t the case by default. A derive_pll_clocks command is required in the SDC constraints file [...]

PCIe on Cyclone 10 GX: Data loss on DMA writes by FPGA

TL;DR DMA writes from a Cyclone 10 GX PCIe interface may be lost, probably due to a path that isn’t timed properly by the fitter. This has been observed with Quartus Prime Version 17.1.0 Build 240 SJ Pro Edition, and the official Cyclone 10 GX development board. A wider impact is likely, possibly on Arria [...]

Quartus / Linux: Programming the FPGA with command-line

Command-line? Yes, it much more convenient than the GUI programmer. Programming an FPGA is a repeated task, always the same file to the same FPGA on the same board connected to the computer. And somehow the GUI programming tools turn it into a daunting ceremony (and sometimes even a quiz, when it can’t tell exactly [...]

Quartus / sdc: Constraining I/O ports clocked by an internal clock

Introduction This post is an expansion for another post of mine, which deals with register I/O packing. It’s recommended reading that one first. Timing constraining of I/O ports is typically intended to ensure timing relations between an external clock and the timing of signals that are clocked by this clock (or derived from this clock, [...]