Altera NIOS II jots

About this post These are things I wrote down at different stages of introducing myself to Nios II and its environment. Nothing really consistent nor necessarily the right way to do things. Jots Open Qsys. Follow this post. Went for Nios II classic, used Nios/e (no Hardware multiplication, as the target device doesn’t have it. [...]

Remote Update from ECPQ flash on Altera Cyclone IV

Introduction This post relates to Altera (or should I say Intel FPGA?) Cyclone IV FPGAs loaded from an ECPQ flash in Active Serial x 1 (AS x 1) mode. Things written below are probably relevant to other Altera FPGAs as well, but keep in mind that Cyclone IV FPGAs have several peculiarities you won’t find [...]

Quartus/Linux: Setting PATH and environment for command-line

The classic way: $ export QUARTUS_ROOTDIR=/path/to/altera/15.1/quartus $ . $QUARTUS_ROOTDIR/adm/ Or open a shell (will set path, but not a full environment): $ /path/to/altera/15.1/nios2eds/ This is good for compiling for NIOS etc.

Altera ECPQ flash access with a Nios II processor + programming bitfiles

Introduction This post outlines some technical details on accessing an Altera ECPQ flash from a Nios II processor for read, write and erase. A non-OS settings (“bare metal”) setting is assumed. And as a bonus (at the bottom of this post), how to program the flash based upon a SOF file, both with JTAG and [...]

Quartus’ timing analysis on set_input_delay and set_output_delay constraints

OK, what’s this? This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints. TimeQuest (Quartus’ timing analyzer) performs a four-corner check (max/min temperature, max/min voltage) and picks the worst slack. In the examples below, the worst case of these four corners is shown. It’s [...]

Meaning of set_input_delay and set_output_delay in SDC timing constraints

Introduction Synopsys Design Constraints (SDC) has been adopted by Xilinx (in Vivado, as .xdc files) as well as Altera (in Quartus, as .sdc files) and other FPGA vendors as well. Despite the wide use of this format, there seems to be some confusion regarding the constraints for defining I/O timing. This post is defines what [...]

Quartus: Packing registers into I/O cells

Often I prefer to handle I/O timing simply by ensuring that all registers are pushed into the I/O cells. Where timing matters, that is. It seems like I/O register packing isn’t the default in Quartus. Anyhow, here’s the lazy man’s recipe for this scenario. First, disable timing checking on all I/Os. This will silence the [...]

Using cgroups to force RAM swapping for implementing an Arria 10 design

The problem I needed to implement an FPGA design for an Arria 10 chip with Quartus 15 on a Linux machine. According to Altera’s requirement page, (“Memory recommendations” tab), the computer should have 28-48 GB of RAM. Or, as it says on that page, one can fake it with virtual memory. It turns out the [...]

stmmaceth: NetworkManager fails to bring up a wired Ethernet NIC

The problem In short: Running linux 3.8.0 on Altera’s Cyclone V SoC, NetworkManager doesn’t bring up the Ethernet port. It also makes false accusations such as Jan 1 00:00:17 localhost NetworkManager[1206]: <info> (eth0): driver ‘stmmaceth’ does not support carrier detection. and later on also says Jan 1 00:00:17 localhost NetworkManager[1206]: <warn> (eth0): couldn’t get carrier [...]

High resolution images of the Sockit board

At times, it’s useful to have a high-resolution picture of the board in front of you. For example, finding the correct place to touch with a probe is easier when the point is first found on the computer screen. These are two very detailed images of the Sockit board by Terasic and Arrow Electronics (and [...]