Controlling GPIO on the Z-Turn Lite board with Xillinux

Introduction This post shows how to access some GPIO functionalities from Xillinux running on a Z-Turn Lite board (with an Z-turn Lite IO Cape board attached), directly from the command line. Watchdog When the “WD” jumper at J26 on the board is placed, it’s possible to utilize the board’s watchdog chip, which resets the processor [...]

Linux: When Vivado’s GUI doesn’t start with an error on locale

Trying to running Vivado 2017.3 with GUI and all on a remote host with X forwarding, i.e. $ ssh -X mycomputer setting the environment with $ . /path/to/Vivado/2017.3/ it failed with $ vivado & terminate called after throwing an instance of ‘std::runtime_error’ what(): locale::facet::_S_create_c_locale name not valid Now here’s the odd thing: The error message [...]

Xilinx’ Zynq Z007s: Is it really single core?

Introduction Xilinx’ documentation says that XC7Z007S, among other “S” devices, is a single-core device, as opposed to, for example, its older brother XC7Z010, which is dual-core. So I compared several aspects of the PS part of a Z007S vs. Z010, and to my astonishment, I found that Z007S is exactly the same: Two CPUs are [...]

Soft Linux kernel hacking for dumping ULPI commands to USB PHY

Ever wanted to see how the a Linux USB host talks with its PHY with ULPI commands? Probably not. But if you do, here’s how I did it on a Zynq device, connected to an USB3320 USB 2.0 PHY chip. Note that: The relevant sources must be compiled into the kernel. Modules are loaded too [...]

Quartus: The importance of derive_pll_clocks in the SDC file

Introduction Whenever a PLL is used in a design to generate one clock from another, it’s quite common to expect the timing tools to figure out the frequencies and timing relations between the different clocks. With Intel’s Quartus tools, this isn’t the case by default. A derive_pll_clocks command is required in the SDC constraints file [...]