Cyclone V SoC: Two masters on a bus errs on ID signal width

While working on Xillinux‘ port to Altera (the SocKit board, actually), I needed to connect two AXI masters: One for the VGA adapter, and one for the Xillybus IP core. Unlike Zynq, Altera’s HPS offers only one AXI slave port, so it’s up to Qsys to generate arbitration logic, implemented in the logic fabric, to connect these two masters to the HPS module.

But the interconnect’s details shouldn’t have bothered me, the user of Qsys. It was supposed to be a matter of connecting both masters to the same slave in Qsys’ graphical representation, and leaving the rest to the tools (Quartus 13.1 and 13.0sp1 in my case).

Only it went a little wrong. Besides, if you intend to use the WSTRB signals at all, you may want to avoid Altera’s master interconnect altogether. See below.

The generation failed as follows:

2013.12.14.17:22:33 Error: hps_0.f2h_axi_slave: width of ID signals (8) must be at least 9
2013.12.14.17:22:33 Info: merlin_domain_transform: After transform: 14 modules, 87 connections
2013.12.14.17:22:33 Info: merlin_router_transform: After transform: 28 modules, 129 connections
... snip ...
2013.12.14.17:22:34 Info: merlin_interrupt_mapper_transform: After transform: 62 modules, 201 connections
2013.12.14.17:22:38 Error: Generation stopped, 51 or more modules remaining
2013.12.14.17:22:38 Info: soc_system: Done soc_system" with 23 modules, 1 files, 298125 byte

Say what? The ID signals of masters on the AXI bus, which are connected to hps_0.f2h_axi_slave, should be 8 bits wide. Besides, where did the figure “9″ come from?

Also, note that Qsys is complaining about the width of a signal it generated itself (the port to the module that instantiates the HPS).

A word about ID widths

The IDs on the AXI bus are intended to identify the master that initiated the transaction, for several purposes (e.g. to allow loose reordering of packets from different masters). The full ID on the internal AXI bus is 12 bits wide.

Consequently, the ID widths presented by an FPGA slave on the AXI bus (attached to the regular or lightweight bridge, it doesn’t matter) should be 12 bits.

When the FPGA is master, the ID width is 8 bits. Rationale: The ID is 12 bits in the main interconnect, but bit 11 is always zero and bits [2:0] are 3′b100 for all packets from the FPGA bridge, so only 8 bits are left for setting by FPGA. See table 6-6 in the Cyclone V Device Handbook vol.3.

The solution

The answer is that the “9″ came from the width of the two master’s ID signals, which was 8, like they should be. It seems like the arbitration logic, which was automatically inserted by Qsys, added another bit in the ID field to distinguish between the two masters connected to it. So there are 9 bits. But the HPS can only offer 8 bits. Bummer.

Understanding the problem, the solution is simple: Reduce the masters’ ID signals’ width to, say, 4. Qsys then requires 5 bits from the HPS module, which is covered by its 8.

WSTRB lost by interconnect

After solving the problem described above, I combined two 64-bit masters into HPS’ slave, 64 bits as well, and experienced data corruptions. Some investigation revealed that the WSTRB signal wasn’t obeyed. Specifically, if WSTRB[7:0] was 0xf0 on a single-beat burst, all 64 bits ended up written into SDRAM, instead of leaving bits [31:0] intact. It’s not clear whether this happened occasionally or all the time, and if this is the only issue. I worked around this by connecting the write related AXI signals directly to the HPS (the arbitration was needed only for read signals), which solved the problem. Hence my conclusion that the interconnect was faulty.