Getting the PCIe of Avnet S6LX150T Development Kit detected

This post was written by eli on March 26, 2013
Posted Under: FPGA,PCI express

About a year ago, I had a client failing to get the PCIe working on an Avnet LX150T development board. Despite countless joint efforts, we failed to get the card detected as a PCIe device by the computer.

A recent comment from another client supplied the clue: The user guide (which I downloaded recently from Avnet) is simply wrong about the DIP switch setting of the board. Table 5 (page 11) says that SW8 should be set OFF-ON-OFF to have a reference clock of 125 MHz to the FPGA.

On the other hand, Avnet’s AXI PCIe Endpoint Design guide for the same board (also downloaded recently from Avnet) says on page 30, that the setting for the same frequency should be ON-ON-ON.

Hmmm… So which one is correct?

Well, those signals go to an IDT ICS874003-05 PCI Express jitter attenuator, which consists of a frequency synthesizer. It multiplies the board’s 100 MHz reference clock by 5 on its internal VCO, and then divides that clock by an integer. The DIP switch setting determines the integers used for both outputs.

Ah, yes, there are generally two different divisors for the two outputs, depending on the DIP switch settings. In other words, PCIe-REFCLK0 and PCIe-REFCLK2 run at different frequencies (except for two settings, for which they happen to be the same). It’s worth to download the chip’s datasheet and have a look. It’s on the first page of the datasheet.

The bottom line is that the correct setting for a 125 MHz clock is ON-ON-ON, for which the correct clock is generated on both clock outputs. By the way, if it’s OFF-OFF-OFF, a 250 MHz clock appears on both outputs.

All other combinations generate two different clocks. Refer to the datasheet if you need a 100 MHz clock.


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