“FPGA-printf”: When Chipscope isn’t fast or deep enough

This post was written by eli on July 19, 2011
Posted Under: FPGA

The concept of having a debugging agent within the FPGA design to probe the logic is by no means new. Xilinx’ Chipscope has presented a neat solution as an internal logic analyzer for several years.

Since Chipscope uses the JTAG channel for its data transfer, it’s sampling depth is effectively limited by the block RAMs allocated for its use. Real-time continuous sampling is out of the question.

When printf-style debugging is more in place, Xillybus can come handy. Based upon the FPGA’s PCI Express hardware core, it allows for up to 200 MByte/s sustained data transfer. The Xillybus IP core interfaces with user application logic through a standard FIFO: Whatever is written to the FIFO appears at the host side as a data stream represented as a file. In this sense, the debugging method resembles printf-debugging: The designer chooses what data and when to write it to the FIFO. It can be a notification of certain events or a bulk stream of metadata. Either way, Xillybus offers an immediate way to transfer debug information to the host.

On the host side, a simple shell script command (such as “cat”) can store the received data on the disk, or it may be analyzed by a plain application or script for detecting events of interest.

Data can be sent in the other direction as well, typically up to 100 MByte/s. This feature can be used for behavioral testing of logic in hardware. When exhaustive verification (or validation)  of core logic is desired, massive data needs to be sent to the logic for input, and its output is then sent back for comparison with the expected results. The overall data transfer reaches gigabytes easily, so not only is a high-bandwidth channel necessary, but a convenient interface for simple user-space applications: Many times the reasonable solution is to generate the test data on the fly as well as comparing the logic’s results against the software application.

Xillybus offers both: With the logic under test connected to FIFOs in the FPGA, the application software on host merely opens one file for input and another one for output. The entire testing process then consists of writing the test data to the output file, read returning data from the input file, and compare the latter with the expected input.

And if this sounds too good to be true, a complete evaluation kit is available for download with no strings attached. The evaluation hardware can be purchased directly from Xilinx at around $500.

Reader Comments

A somewhat similar tool that takes advantage of FPGA high-speed transceivers is THUNDER by Byte Paradigm: http://www.byteparadigm.com/thunder-series-113.html

Written By Evgeni on September 10th, 2011 @ 13:45

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