Verilog: Declaring each port (or argument) once

This post was written by eli on July 25, 2009
Posted Under: FPGA,Software

(…or why the Verilog-emacs AUTOARG is redundant)

In Verilog, I never understood why port declarations appear both in the module declaration, and then immediately afterwards, along with the wires and registers. I mean, if the ports in the module declaration are always deducible from what follows immediately, why is the language forcing me to write it twice?

The short answer is: It doesn’t.

Let’s have a look on this simple module:

module example(clk, outdata, inbit, outbit);
   parameter width = 16;

   input clk;
   input inbit;
   output outbit;
   output [(width-1):0] outdata;

   reg [(width-1):0]		outdata;

   assign 	outbit = !inbit;

   always @(posedge clk)
     outdata <= outdata + 1;


There is nothing new here, even for the Verilog beginner: It demonstrates a simple combinatoric input-output relation. We also have an output, which happens to be a register as well (I didn’t even bother to reset it).

And as usual, every port is mentioned twice. Yuck.

Instead, we can go:

module example #(parameter width = 16)
   input clk,
   input inbit,
   output outbit,
   output reg [(width-1):0] outdata

   assign 	outbit = !inbit;

   always @(posedge clk)
     outdata <= outdata + 1;


At this point, I’d like to point out, that this is no dirty trick; This type of module declaration is explicitly defined in the Verilog 2001 standard (or by its official name, IEEE Std 1364-2001). This goes both for defining the ports and the parameters  (thanks to Evgeni for pointing out the possibility to set parameters as shown above).

According to the BNF definition in Annex A (A.1.3, to be precise), a module definition must take one of the two formats shown above, but mixing them is not allowed.

So here are few things to note when using the latter format:

  • Each port declaration ends with a comma, not a semicolon. Same goes for parameter declarations.
  • It’s not allowed to declare anything about the port again in the module’s body. Repeating the port’s name as a wire or reg is not allowed.
  • Use “output reg” (which is legal in either format)  instead of declaring the register in the module’s body (which is not allowed in this setting)
  • Syntax highlighters and indenters may not work well

The question is now: How could I not know about this?

Reader Comments

I agree this format is much more concise and easier to read. I wonder what the reasoning was in Verilog 95 for requiring the dual input/output declaration?

Written By Andy on April 6th, 2010 @ 21:39

I suppose there was some inside sabotage by VHDL guys.

Written By eli on April 6th, 2010 @ 21:45

This is priceless! Having switched from VHDL to Verilog, I was always annoyed with these double port declarations. This easily cuts out a hundred lines of useless code.

Written By Tim on April 12th, 2013 @ 16:21

One use of duplicated port declaration I’ve seen was in netlisting tool that converted transistor-level schematics into Verilog netlist. This was part of a fully custom chip design flow.

The tool was generating code like this:

module example( my_signal1[0], my_signal2[1:0],
{my_signal1[1], my_signal2[2]} );
input [1:0] my_signal1;
input [2:0] my_signal2;

Don’t know the reason why it did it that way. But it took advantage of the fact that Verilog allows flexible grouping of the module IO signals.


Written By Evgeni on August 9th, 2013 @ 19:57

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