Getting the right names in the UCF file: Using netgen

This post was written by eli on July 24, 2009
Posted Under: FPGA

The problem: NGDBUILD tells you it can’t find a net or instance given in the UCF file. It’s likely that the synthesizer changed the names, sometimes slightly and sometimes beyond recognition. You need these names to define a timing group, for example, but how do you know them?

Normally, I would get the net and instance names from FPGA Editor, or possibly from the Timing analyzer. But without any successful place-and-route, how can I know what names the synthesizer gave them, if I can’t even get through NGDBUILD?

Solution: Create a simulation model in Verilog (it also possible in VHDL, but I’ll show Verilog):

If my synthesis gave mydesign.ngc, simply write at command prompt (to most of you it’s a DOS window):

netgen -ofmt verilog mydesign.ngc delme.v

And delme.v will contain the simulation model. It’s a fairly readable file, in which the design is broken down to small primitives, which makes it pretty heavy. But the names used for nets and logic are those that go to NGDBUILD, and with some searching in the text file, one can get around.

Note that if mydesign.ncd is used rather than mydesign.ngc, you’ll get the simulation model for the post-PAR result (which can be useful too at times).

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