Introduction I’m using Xilinx’ MiG 1.7.3 for running DDR2 memories on a Virtex-4 FPGA. It didn’t take me long to realize that the controller never finishes initialization. The problem is that I had no idea of why, and as far as I know, no documentation to refer to in my attempts to understand where the [...]
One of the problems with setting up timing constraints in the UCF file, is to be sure that you got the right elements in, and kept the unnecessary ones out. Suppose I wrote something like NET “the_clock” TNM_NET = “tnm_ctrl_clk”; TIMESPEC “TS_ctrl_clk” = PERIOD “tnm_ctrl_clk” 40 ns HIGH 50 %; What logic element does it [...]
One of the things I try to avoid as an FPGA engineer, is to manually configure the pin constraints (in the UCF file) in order to tell the tools which FPGA pin is connected to what. Not only is this extremely boring, but I also think that getting it done right (at the first go) [...]
Take a close look on the Verilog code below. This is a plainly-written synchronous ROM. Do you see anything wrong with it? (Spoiler: There is nothing wrong with it. Not that I know of) module coeffs ( clk, en, addr, data ); input clk, en; input [9:0] addr; [...]
