Sometimes, in particular when working on a relatively new Xilinx device family, the “map” tool fails on several errors like ERROR:MapLib:979 – LUT5 symbol “project/project_core/module/module_empty_user_w_smb_wren_d_O R_201_o_inv1″ (output signal=project/project_core/module/module_empty_user_w_smb_wr en_d_OR_201_o_inv) has input signal “project/project_core/module/module_almostfull_d” which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven [...]
At times, it’s useful to have a high-resolution picture of the board in front of you. For example, finding the correct place to touch with a probe is easier when the point is first found on the computer screen. These are two very detailed images of the Zedboard by Digilent (and Avnet), which is one [...]
The short answer The P7 ARM processor’s buses run AXI3 It’s not as important as it seems at first The supposed conflict Xilinx have been transferring most of its CoreGen IP cores from all kinds of interfaces to AXI4 over the last few years. With the transaction of Microblaze-related IP cores together with the anticipation [...]
Having some trouble to figure out what I should write in my own hand-written DTS entry for my logic, I ended up reading the sources of the Linux kernel (version 3.3, which is the currently used for Zynq). The purpose is to hook up a device defined in the PL of a Zynq-7000 (FPGA-style logic [...]
Background Creating a DTS file is a crucial step in integrating a custom peripheral with the Linux kernel. Unfortunately, this subject is rather hazy at the present time, and it’s in particular difficult to obtain that initial DTS to boot the system up with for the first time. It’s important to take the DTS (and [...]
