Every now and then Vivado whines with [Common 17-356] Failed to install all user apps. And every time I’m looking up how to to solve this, and then I find that the command that fixes this is tclapp::reset_tclstore in the Tcl command window. And then quit Vivado, and start it again. Why? I’ll never know. [...]
Introduction Checking Xillybus’ bundle for Kintex Ultrascale+ on Vivado 2020.1, I got several critical warnings related to the PCIe block. As the bundle is intended to show how Xillybus’ IP core is used for simplifying communication with the host, these warnings aren’t directly related, and yet they’re unacceptable. This bundle is designed to work with [...]
The said board, which is Xilinx’ official development kit for Kintex-7, has an LCD which can be taken off. Its pins can then be used as plain testpoints for logic. These are the placement constraint for this use (Vivado XDC style): set_property PACKAGE_PIN Y10 [get_ports tp[0]]; # LCD_DB7, pin 1 set_property PACKAGE_PIN AA11 [get_ports tp[1]]; [...]
… or why does my GTH/GTY not come out of reset? Why are those reset_rx_done / reset_tx_done never asserted after a reset_all or a reset involving the CPLLs? What’s this CPLL calibration thing about? It turns out that some GTH/GTY’s on Ultrascale and Ultrascale+ FPGAs have problems with getting the CPLL to work reliably. I’ll [...]
… or any other “unsupported” Linux distribution. … or: How to trick the installer into thinking you’re running one of the supported OSes. So I wanted to install Vivado 2020.1 on my Linux Mint 19 (Tara) machine. I downloaded the full package, and ran xsetup. A splash window appeared, and soon after it another window [...]
As I implemented a MiG controller for KC705′s on-board SODIMM, the controller failed to calibrate at first. Despite that I’ve copied the instantiation and port connections from the example design. As for the pin placement, this was taken care of by the core itself, by virtue of memctl/memctl/user_design/constraints/memctl.xdc within MiG’s dedicated directory (which I called [...]
Trying to running Vivado 2017.3 with GUI and all on a remote host with X forwarding, i.e. $ ssh -X mycomputer setting the environment with $ . /path/to/Vivado/2017.3/settings64.sh it failed with $ vivado & terminate called after throwing an instance of ‘std::runtime_error’ what(): locale::facet::_S_create_c_locale name not valid Now here’s the odd thing: The error message [...]
OK, what’s this? This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints. As mentioned on the other post, the relevant timing constraints were: create_clock -name theclk -period 20 [get_ports test_clk] set_output_delay -clock theclk -max 8 [get_ports test_out] set_output_delay -clock theclk -min -3 [get_ports [...]
Introduction Synopsys Design Constraints (SDC) has been adopted by Xilinx (in Vivado, as .xdc files) as well as Altera (in Quartus, as .sdc files) and other FPGA vendors as well. Despite the wide use of this format, there seems to be some confusion regarding the constraints for defining I/O timing. This post is defines what [...]
Introduction In several versions of Xilinx’ wrapper for the integrated PCIe block, it’s the user application logic’s duty to instantiate the module which generates the “pipe clock”. It typically looks something like this: pcie_myblock_pipe_clock # ( .PCIE_ASYNC_EN ( “FALSE” ), // PCIe async enable .PCIE_TXBUF_EN ( “FALSE” ), // PCIe TX buffer enable for Gen1/Gen2 [...]
