To make a long story short… There is really no need to work hard to make your FPGA talk with a PC. Xillybus gives you the end-to-end connection interfacing FPGAs with both Linux and Windows computers. The challenge At times, FPGA engineers are faced with the need to transfer data to or from a regular [...]
While porting Xillybus to Virtex-5, I ran into nasty trouble. In the beginning, it looked like the MSI interrupt delivery mechanism was wrong, and then it turned out that the core gets locked up completely after a few packets, and refuses to send any TLPs after a few sent. I also noticed that the PCIe [...]
Introduction The PCI Express standard requires an error detection and retransmit mechanism, which ensures that the TLP packets indeed arrive correctly. The need for reliable communication on a system bus is obvious, but this mechanism also sweeps problems under the carpet: If data packets arrive faulty or are lost in the lower layers, nobody will [...]
The fatal error Let’s break the bad news: Spartan-6′s PCIe core may drop TLP packets sporadically when ASPM (Active State Power Management) is enabled. That means that any TLP given to the core for transmission can silently disappear, as if it was never submitted. I also suspect that the problem exists in the opposite direction. [...]
This is just a raw dump of PCIe communication. I wrote a small sniffer on an FPGA and ran some data in a loop to and from the peripheral. The sniffer’s own data was stored while sniffing, so it doesn’t appear in the stream. The whole thing ran on a Linux machine. I thought that [...]
While the PCI Express standard is impressive in that it actually makes sense (well, most of the time) there is a pretty annoying thing about read requests reordering. By the way, I talk about TLP packet formation in general in another post. In section 2.4.1 of the PCIe spec 1.1, it says that read requests [...]
Finding the maximal payload manually The truth is, there is no need to do this manually. lspci does the work for us. But looking into the configuration table once and for all helps demystifying the issue. So here we go. According to the PCIe spec (section 7.8), the max_payload_size the card can take is give [...]
Update: The project is up and running, available for a large range of FPGAs. Click here to visit its home page. Over the years in which I’ve worked on FPGA projects, I’ve always been frustrated by the difficulty of communicating with a PC. Or an embedded processor running a decent operating system, for that matter. [...]
