Introduction Checking Xillybus’ bundle for Kintex Ultrascale+ on Vivado 2020.1, I got several critical warnings related to the PCIe block. As the bundle is intended to show how Xillybus’ IP core is used for simplifying communication with the host, these warnings aren’t directly related, and yet they’re unacceptable. This bundle is designed to work with [...]
Introduction These are a few random things I wrote down as I worked with the Stratix 10 Development Kit, with focus on its PCIe interface. Quite obviously, it’s mostly about things I found noteworthy about this specific FPGA and its board, compared with previous hardware I’ve encountered. Generally speaking, Stratix 10 is not for the [...]
Why is it at 2.5 GT/s??? With all said about Nvidia’s refusal to release their drivers as open source, their Linux support is great. I don’t think I’ve ever had such a flawless graphics card experience with Linux. After replacing the nouveau driver with Nvidia’s, of course. Ideology is nice, but a computer that works [...]
TL;DR DMA writes from a Cyclone 10 GX PCIe interface may be lost, probably due to a path that isn’t timed properly by the fitter. This has been observed with Quartus Prime Version 17.1.0 Build 240 SJ Pro Edition, and the official Cyclone 10 GX development board. A wider impact is likely, possibly on Arria [...]
Introduction In several versions of Xilinx’ wrapper for the integrated PCIe block, it’s the user application logic’s duty to instantiate the module which generates the “pipe clock”. It typically looks something like this: pcie_myblock_pipe_clock # ( .PCIE_ASYNC_EN ( “FALSE” ), // PCIe async enable .PCIE_TXBUF_EN ( “FALSE” ), // PCIe TX buffer enable for Gen1/Gen2 [...]
General As part of a larger project, I was required to set up a PCIe link between a host and some FPGAs through a fiber link, in order to ensure medical-grade electrical isolation of a high-bandwidth video data link + allow for control over the same link. These are a few jots on carrying a [...]
Introduction This is a summary of a few topics that should to be kept in mind when a Multi-Gigabit Tranceiver (MGT) is employed in an FPGA design. It’s not a substitute for reading the relevant user guide, nor a tutorial. Rather, it’s here to point at issues that may not be obvious at first glance. [...]
Introduction These are my notes as I programmed an Atmel AT25128 EEPROM, attached to a PEX 8606 PCIe switch, using PCIe configuration-space writes only (that is, no I2C / SMBus cable). This is frankly quite redundant, as Avago supplies software tools for doing this. In fact, in order to get their tools, register at Avago’s [...]
While working on a project involving a custom PCIe interface, Linux’ message log became flooded with messages like pcieport 0000:00:1c.6: device [8086:a116] error status/mask=00001081/00002000 pcieport 0000:00:1c.6: [ 0] Receiver Error pcieport 0000:00:1c.6: [ 7] Bad DLLP pcieport 0000:00:1c.6: [12] Replay Timer Timeout pcieport 0000:00:1c.6: Error of this Agent(00e6) is reported first pcieport 0000:02:00.0: PCIe Bus [...]
About a year ago, I had a client failing to get the PCIe working on an Avnet LX150T development board. Despite countless joint efforts, we failed to get the card detected as a PCIe device by the computer. A recent comment from another client supplied the clue: The user guide (which I downloaded recently from [...]
