About a year ago, I had a client failing to get the PCIe working on an Avnet LX150T development board. Despite countless joint efforts, we failed to get the card detected as a PCIe device by the computer. A recent comment from another client supplied the clue: The user guide (which I downloaded recently from [...]
Sometimes, in particular when working on a relatively new Xilinx device family, the “map” tool fails on several errors like ERROR:MapLib:979 – LUT5 symbol “project/project_core/module/module_empty_user_w_smb_wren_d_O R_201_o_inv1″ (output signal=project/project_core/module/module_empty_user_w_smb_wr en_d_OR_201_o_inv) has input signal “project/project_core/module/module_almostfull_d” which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven [...]
The golden rule is: All operands must be signed. Verilog, it seems, is strongly inclined towards unsigned numbers. Any of the following yield an unsigned value: Any operation on two operands, unless both operands are signed. Based numbers (e.g. 12′d10), unless the explicit “s” modifier is used) Bit-select results Part-select results Concatenations So the bottom [...]
At times, it’s useful to have a high-resolution picture of the board in front of you. For example, finding the correct place to touch with a probe is easier when the point is first found on the computer screen. These are two very detailed images of the Zedboard by Digilent (and Avnet), which is one [...]
The short answer The P7 ARM processor’s buses run AXI3 It’s not as important as it seems at first The supposed conflict Xilinx have been transferring most of its CoreGen IP cores from all kinds of interfaces to AXI4 over the last few years. With the transaction of Microblaze-related IP cores together with the anticipation [...]
Background Creating a DTS file is a crucial step in integrating a custom peripheral with the Linux kernel. Unfortunately, this subject is rather hazy at the present time, and it’s in particular difficult to obtain that initial DTS to boot the system up with for the first time. It’s important to take the DTS (and [...]
To make a long story short… There is really no need to work hard to make your FPGA talk with a PC. Xillybus gives you the end-to-end connection interfacing FPGAs with both Linux and Windows computers. The challenge At times, FPGA engineers are faced with the need to transfer data to or from a regular [...]
While porting Xillybus to Virtex-5, I ran into nasty trouble. In the beginning, it looked like the MSI interrupt delivery mechanism was wrong, and then it turned out that the core gets locked up completely after a few packets, and refuses to send any TLPs after a few sent. I also noticed that the PCIe [...]
In Verilog there’s a bit shifter operator, which isn’t used a lot, since FPGA designers prefer to state exact bit vectors. But sometimes bit shifting makes the code significantly more readable. Too bad that Xilinx’ XST synthesizer doesn’t get it right in a specific case. Namely, the following statement is perfectly legal: always @(posedge clk) [...]
Just lucky? I’ve been approached a few times with requests to design the FPGA part of an FPGA-to-PC link over Ethernet. The purpose of the link is typically transporting a large amount of data to the PC. The application varies from continuous data acquisition to frame grabbing or transport of a raw video image stream. [...]
