I discovered this problem in a project that instantiated a 512-bit wide FIFO consisting many (>16) times in different modules. For some unknown reason (it’s called a bug, I suppose) Vivado treated the instantiation as if it wasn’t there, and optimized all surrounding logic as if the black box’ output ports were all zero. For [...]
Introduction After installing Vivado 2014.1 on my laptop running Ubuntu 14.04 (64 bits), I went for license activation. All I wanted was a plain node-locked license. Not a server, and not a floating one. Baseline. Xilinx abandoned the good old certificate licensing in favor of activation licensing. That is causing some headaches lately… Going through [...]
Introduction Xilinx’ Series-7 FPGAs (Virtex-7, Kintex-7, Atrix-7 and Zynq-7000) offer a rather flexible frequency synthesizer, (MMCE2) allowing steps of 0.125 for setting the VCO’s multiplier and one of its dividers. The MMCE can be reprogrammed through its DRP interface, so it can be used as a source of a variable clock frequency. These are a [...]
These are a few jots about constraining in Vivado. With no particular common topic, and in no particular order. Note that I have another post on similar topics. Setting the default IOSTANDARD for all ports In a design where all ports have the same IOSTANDARD, it’s daunting to set them for all. So if there’s [...]
Running Xillinux on the Zybo board, this is how I toggled a GPIO pin from a plain one-liner bash script in Linux. The same technique can be used for other Zynq-7000 boards (Zedboard in particular) to easily control GPIO pins. First, I looked up which GPIO pin it is. The pin assignments can be found [...]
So I installed Vivado on my Centos 6.5 64-bit Linux machine, and even though it promised to install icons on my desktop, it didn’t. This is how I installed them manually. There is surely a simpler way, as the special launch bash scripts I created must be somewhere. But I didn’t bother looking. So it [...]
Background This is yet another war story about making the FSBL boot on a Zynq processor. I had prepared an FSBL for a certain target using SDK 14.6, and then someone needed it in a Vivado package, using the SDK attached to Vivado 2014.1. In a perfect world, I would have exported the system’s configuration [...]
Just a few things I wrote down for myself, as I got acquainted with Vivado 2014.1 (having worked with ISE until now). Kicking off in Linux $ cd trashcan-directory $ . /path/to/Vivado_2014.1/Vivado/2014.1/settings64.sh $ vivado & or running Vivado with a certain Tcl script $ vivado -mode batch -source /path/to/project.tcl or implementing a project without GUI: [...]
At times, it’s useful to have a high-resolution picture of the board in front of you. For example, finding the correct place to touch with a probe is easier when the point is first found on the computer screen. These are two very detailed images of the Sockit board by Terasic and Arrow Electronics (and [...]
Wildcards There is a certain confusion regarding how wildcards are matched in the SDC file (in fact, by the Tcl commands), which is why full paths are often used. This causes overloaded SDC files that don’t survive changes in the hierarchy. For example, regarding get_pins, the SDC and TimeQuest API Reference Manual page 2-15 states [...]
