This is a small reverse-engineering of the ELF file, as generated by Xilinx’ SDK for a simple standalone application targeted for the SP605 board. ELF headers Looking into the ELF file, we have something like this: > mb-objdump –headers sdk/peripheral_tests_1/Debug/peripheral_tests_1.elf sdk/peripheral_tests_1/Debug/peripheral_tests_1.elf: file format elf32-microblazele Sections: Idx Name Size VMA LMA File off Algn 0 .vectors.reset [...]
This is a small guide to loading a standalone application + bitstream to an FPGA using the CompactFlash card. Or put otherwise, how to make the System ACE chip happy. For loading a Linux kernel in the same way, I suggest referring to a special post in that subject. Formatting the flash Rule #1: Don’t [...]
A mix of issues not deserving a post of their own. COM port issues (with Windows XP) The SDK has its own terminal, which can be set to run with a serial port. It works fine. As for Hyperterminal, by all means configure a connection with a specified Hyperterminal configuration file. Just setting the properties [...]
Why embedded PC Embedded PC computers are commonly used instead of simple microcontrollers when more than a basic interface with the outer world is needed, e.g. Disk storage (ATA, SATA or ATAPI) USB connection with disk-on-key storage or other peripherals Ethernet connection (TCP/IP in particular) VGA/DVI for display of GUI, possibly based upon a high-level [...]
The concept of having a debugging agent within the FPGA design to probe the logic is by no means new. Xilinx’ Chipscope has presented a neat solution as an internal logic analyzer for several years. Since Chipscope uses the JTAG channel for its data transfer, it’s sampling depth is effectively limited by the block RAMs [...]
The headache… Data acquisition is one of those tasks, which always seem so easy until they get real. In the block diagram, capturing data is just an arrow to the computer. In reality, getting the data from the FPGA to something that feels like the real world can turn out to be the hardest part [...]
The fatal error Let’s break the bad news: Spartan-6′s PCIe core may drop TLP packets sporadically when ASPM (Active State Power Management) is enabled. That means that any TLP given to the core for transmission can silently disappear, as if it was never submitted. I also suspect that the problem exists in the opposite direction. [...]
Surprisingly enough, I haven’t found a plain and simple cookbook on how to generate a presynthesized IP core for delivery. So I tried it out, and wrote my findings here. Since it’s a result of trial and error, I may have missed some crucial points. Please comment below if you know about such. Synthesis In [...]
It looks like inferring RAMs and ROMs is the weak spot of XST. This is the second bug I find using this synthesizer, this time on XST M.63c, coming with ISE Release 12.2. The previous bug was ROM creation from a case statement. But hey, that was two years ago. This time I the code [...]
Update: The project is up and running, available for a large range of FPGAs. Click here to visit its home page. Over the years in which I’ve worked on FPGA projects, I’ve always been frustrated by the difficulty of communicating with a PC. Or an embedded processor running a decent operating system, for that matter. [...]
