A few posts on FPGA on my other site

I’ve been a bit silent on this blog for a while, but that’s only because I’ve been busy writing on my spin-off site lately.

So here are a few posts over there which are pretty much related to what I do on this blog. These pages are also translated to Chinese, Japanese and Korean, so this is what those links in parentheses are about.

About FIFOs:

• Introduction to FPGA FIFOs (zh ja ko)
• FPGA FIFOs: Different features and variants (zh ja ko)
• Implementation of single clock FIFOs in Verilog (zh ja ko)
• Improving timing on FIFOs by adding registers (zh ja ko)

About clock domains:

• Clock domains, related clocks and unrelated clocks (zh ja ko)
• Metastability and the basics of clock domain crossing (zh ja ko)
• Clock domain crossing with data (zh ja ko)