Displayport’s M and its Mvid fields: Timestamp or divider?

Introduction The Displayport standard requires the transmission of fields named Mvid in different places of the main link stream, however the relevant parts in the standard are somewhat unclear. This is an attempt to understand the rationale behind the standard’s requirements, in the hope to clarify them. This post is intended for someone who has [...]

Posted Under: Displayport
This post was written by eli on June 18, 2015 Comments (2)

Xilinx FPGA GTX: The exact meaning of TXCHARDISPVAL

Displayport’s standard requires that the TPS2 and TPS3 training sequences have a known running disparity on the transmitted characters. It uses a plus-minus notation (e.g. K28.5-) to indicate the disparity, and also clarifies the meaning of this notation by writing out the bit sequences of K28.5- and K28.5+. Xilinx, on the other hand, is slightly [...]

Posted Under: Displayport,FPGA
This post was written by eli on June 17, 2015 Comments (2)