DDR memory bit errors with SocKit (Cyclone V SoC device)

The problem There seems to be a minor DDR memory reliability issue with the SocKit, having the 5CSXFC6D6F31C8NES device marked “F AAAAU1319A”. This can be detected by copying pseudorandom data from one buffer to another repeatedly, and then comparing the data between the buffers. The buffers must be large, to make sure the cache is [...]

Posted Under: Intel FPGA (Altera)
This post was written by eli on November 12, 2013 Comments (4)

Experimenting with SDC/Tcl wildcards: Quartus TimingQuest Timing Analyzer

Wildcards There is a certain confusion regarding how wildcards are matched in the SDC file (in fact, by the Tcl commands), which is why full paths are often used. This causes overloaded SDC files that don’t survive changes in the hierarchy. For example, regarding get_pins, the SDC and TimeQuest API Reference Manual page 2-15 states [...]

Posted Under: FPGA,Intel FPGA (Altera),Tcl
This post was written by eli on November 9, 2013 Comments (0)