Zynq-7000 EPP: Does it connect with AXI3 or AXI4?

The short answer The P7 ARM processor’s buses run AXI3 It’s not as important as it seems at first The supposed conflict Xilinx have been transferring most of its CoreGen IP cores from all kinds of interfaces to AXI4 over the last few years. With the transaction of Microblaze-related IP cores together with the anticipation [...]

Posted Under: ARM,FPGA,Zynq
This post was written by eli on August 8, 2012 Comments (1)

Interrupt definitions in DTS (device tree) files for Xilinx Zynq-7000 / ARM

Having some trouble to figure out what I should write in my own hand-written DTS entry for my logic, I ended up reading the sources of the Linux kernel (version 3.3, which is the currently used for Zynq). The purpose is to hook up a device defined in the PL of a Zynq-7000 (FPGA-style logic [...]

Posted Under: ARM,Linux kernel,Zynq
This post was written by eli on August 4, 2012 Comments (15)