While porting Xillybus to Virtex-5, I ran into nasty trouble. In the beginning, it looked like the MSI interrupt delivery mechanism was wrong, and then it turned out that the core gets locked up completely after a few packets, and refuses to send any TLPs after a few sent. I also noticed that the PCIe [...]
In Verilog there’s a bit shifter operator, which isn’t used a lot, since FPGA designers prefer to state exact bit vectors. But sometimes bit shifting makes the code significantly more readable. Too bad that Xilinx’ XST synthesizer doesn’t get it right in a specific case. Namely, the following statement is perfectly legal: always @(posedge clk) [...]
There are several ways to stop these pingbacks, 95% of which are spam. My method may not be optimal, but has the elegance of simplicity. Simply edit the part in the end of wp-trackback.php (at WordPress’ root directory) going if ( !empty($tb_url) && !empty($title) ) { header(‘Content-Type: text/xml; charset=’ . get_option(‘blog_charset’) ); if ( !pings_open($tb_id) [...]