Data acquisition with FPGA: Not a headache necessarily.

The headache…

Data acquisition is one of those tasks, which always seem so easy until they get real. In the block diagram, capturing data is just an arrow to the computer. In reality, getting the data from the FPGA to something that feels like the real world can turn out to be the hardest part in the entire project.

And the striking question is: If getting data on and off an FPGA is such a commonly needed task, how come there isn’t a generic package, which does the job for you? How come getting the data to a computer just has to involve learning how a PCI or PCI express bus works, DMA, bus master issues, TLP, RCB, you name it. Or if the channel is through USB, the engineer needs to become friends with USB endpoints, understand bulk transfer, and how to configure a device to hotplug nicely.

… and its painkiller

And here comes the answer. This is exactly what Xillybus is: A generic solution for transporting data from and to an FPGA with a Windows or Linux computer at the other end.

In order to make things as simple as possible, the interfaces are the most easily understood: The FPGA designer works with plain FIFOs and possibly dual-port RAMs, and the programmer with plain userspace (device) files. No drivers to write, no complicated API to follow. As a matter or fact, the host software can be written even as scripts.

And the board design consists of getting 7 wires correctly. That’s all.

Several Xilinx FPGAs with T suffix are supported as well as Altera devices. Their hardware PCIe core is an invitation to connect with a computer, even if it’s just for testing logic components on hardware. Or getting debug information. Or getting a large chunk of samples from analog-to-digital converters (ADC) to check against simulation.

The barrier is gone. There is no need to consider the data transport a project of its own. A FIFO on one side, a file on the other, and the rest is a black box.