Introduction The Xilinx Platform Studio (EDK) has this “update bitstream” function, which I wasn’t so clear about, despite its documentation page. Its icon says “BRAM INIT” which turns out to be more accurate than expected. So what happens during this process? When is it necessary? If you’re into running a Linux kernel, you’re most likely [...]
This is a small reverse-engineering of the ELF file, as generated by Xilinx’ SDK for a simple standalone application targeted for the SP605 board. ELF headers Looking into the ELF file, we have something like this: > mb-objdump –headers sdk/peripheral_tests_1/Debug/peripheral_tests_1.elf sdk/peripheral_tests_1/Debug/peripheral_tests_1.elf: file format elf32-microblazele Sections: Idx Name Size VMA LMA File off Algn 0 .vectors.reset [...]
This is a small guide to loading a standalone application + bitstream to an FPGA using the CompactFlash card. Or put otherwise, how to make the System ACE chip happy. For loading a Linux kernel in the same way, I suggest referring to a special post in that subject. Formatting the flash Rule #1: Don’t [...]
A mix of issues not deserving a post of their own. COM port issues (with Windows XP) The SDK has its own terminal, which can be set to run with a serial port. It works fine. As for Hyperterminal, by all means configure a connection with a specified Hyperterminal configuration file. Just setting the properties [...]
Introduction The PCI Express standard requires an error detection and retransmit mechanism, which ensures that the TLP packets indeed arrive correctly. The need for reliable communication on a system bus is obvious, but this mechanism also sweeps problems under the carpet: If data packets arrive faulty or are lost in the lower layers, nobody will [...]
Why embedded PC Embedded PC computers are commonly used instead of simple microcontrollers when more than a basic interface with the outer world is needed, e.g. Disk storage (ATA, SATA or ATAPI) USB connection with disk-on-key storage or other peripherals Ethernet connection (TCP/IP in particular) VGA/DVI for display of GUI, possibly based upon a high-level [...]
The concept of having a debugging agent within the FPGA design to probe the logic is by no means new. Xilinx’ Chipscope has presented a neat solution as an internal logic analyzer for several years. Since Chipscope uses the JTAG channel for its data transfer, it’s sampling depth is effectively limited by the block RAMs [...]
The headache… Data acquisition is one of those tasks, which always seem so easy until they get real. In the block diagram, capturing data is just an arrow to the computer. In reality, getting the data from the FPGA to something that feels like the real world can turn out to be the hardest part [...]
Views and SQL Using Drupal views basically is trying to figure out how to trick the machine into making the SQL query I would have written in five minutes. As a matter of fact, I don’t think I had a chance of getting this right, hadn’t I known SQL pretty well. Or, as one of [...]