The PCF file: Xilinx timing constraints as the tools understood them
One of the problems with setting up timing constraints in the UCF file, is to be sure that you got the right elements in, and kept the unnecessary ones out.
Suppose I wrote something like
NET "the_clock" TNM_NET = "tnm_ctrl_clk"; TIMESPEC "TS_ctrl_clk" = PERIOD "tnm_ctrl_clk" 40 ns HIGH 50 %;
What logic element does it apply to? Did it work like I expected?
The information can be obtained by creating a timegroup report in the Timing Analyzer, but it’s actually available in a much easier way: The PCF file, which is created by the MAP tool. This file has the same syntax as the UCF file, but it reflects the constraints as understood by the tools.
You will find the as-made pin placements there (not shown here), and the timing groups as TIMEGRP statements. It goes something like:
TIMEGRP tnm_ctrl_clk = BEL "controller/bus_oe_16" BEL
"controller/ctrl_dout_15" BEL "controller/bus_oe_15" BEL
"controller/ctrl_dout_14" BEL "controller/bus_oe_14" BEL
"controller/ctrl_dout_13" BEL "controller/bus_oe_13" BEL
"controller/ctrl_dout_12" BEL "controller/bus_oe_12" BEL
"controller/ctrl_dout_11" BEL "controller/bus_oe_11" BEL
"controller/ctrl_dout_10" BEL "controller/bus_oe_10" BEL
"controller/ctrl_dout_9" BEL "controller/bus_oe_9" BEL
"controller/ctrl_dout_8" BEL "controller/bus_oe_8" BEL
"controller/ctrl_dout_7" BEL "controller/bus_oe_7" BEL
"controller/ctrl_dout_6" BEL "controller/bus_oe_6" BEL
"controller/ctrl_dout_5" BEL "controller/bus_oe_5" BEL
"controller/ctrl_dout_4" BEL "controller/bus_oe_4" BEL
"controller/ctrl_dout_3" BEL "controller/bus_oe_3" BEL
"controller/ctrl_dout_2" BEL "controller/bus_oe_2" BEL
"controller/ctrl_dout_1" BEL "controller/bus_oe_1" BEL
"controller/ctrl_dout_0";
There you have it, in plain text. The relevant constraint is just a few rows away:
TS_ctrl_clk = PERIOD TIMEGRP "tnm_ctrl_clk" 40 ns HIGH 50%;
As simple as that.
Reader Comments
Hi Eli,
Aditya, Electronics Graduate from India here.
My question:
The bitgen command creates a bit and if -g option is given also a bin file.
An optional input file that the bitgen command accommodates is the pcf file (created as you stated during map command)
Now when the pcf file is created and there is a manually created ucf file in the directory will the pcf file created during map have all the constraints present in the ucf file when it is created with map command?
Xilinx don’t expect anyone to play around with the pcf files directly. So all constraints in the UCF file are in effect for all tools. How exactly the tools get this info, I can’t say for sure, but I would put my money on the pcf file for the mapper, PAR, and Bitgen.
Xilinx support should give you a more decisive answer.
i m using xilinx ise 10.1. i need to know how to estimate dynamic power and how to generate the .xml , .ncd, .pcf files in xilinx