Xilinx’ XST synthesizer bug: ROM generation using case

Take a close look on the Verilog code below. This is a plainly-written synchronous ROM. Do you see anything wrong with it? (Spoiler: There is nothing wrong with it. Not that I know of) module coeffs   (    clk, en,    addr, data    );    input clk, en;    input [9:0] addr;    [...]