Meaning of set_input_delay and set_output_delay in SDC timing constraints

Introduction Synopsys Design Constraints (SDC) has been adopted by Xilinx (in Vivado, as .xdc files) as well as Altera (in Quartus, as .sdc files) and other FPGA vendors as well. Despite the wide use of this format, there seems to be some confusion regarding the constraints for defining I/O timing. This post is defines what [...]

Quartus: Packing registers into I/O cells

Often I prefer to handle I/O timing simply by ensuring that all registers are pushed into the I/O cells. Where timing matters, that is. It seems like I/O register packing isn’t the default in Quartus. Anyhow, here’s the lazy man’s recipe for this scenario. First, disable timing checking on all I/Os. This will silence the [...]

Using cgroups to force RAM swapping for implementing an Arria 10 design

The problem I needed to implement an FPGA design for an Arria 10 chip with Quartus 15 on a Linux machine. According to Altera’s requirement page, (“Memory recommendations” tab), the computer should have 28-48 GB of RAM. Or, as it says on that page, one can fake it with virtual memory. It turns out the [...]

stmmaceth: NetworkManager fails to bring up a wired Ethernet NIC

The problem In short: Running linux 3.8.0 on Altera’s Cyclone V SoC, NetworkManager doesn’t bring up the Ethernet port. It also makes false accusations such as Jan 1 00:00:17 localhost NetworkManager[1206]: <info> (eth0): driver ‘stmmaceth’ does not support carrier detection. and later on also says Jan 1 00:00:17 localhost NetworkManager[1206]: <warn> (eth0): couldn’t get carrier [...]

High resolution images of the Sockit board

At times, it’s useful to have a high-resolution picture of the board in front of you. For example, finding the correct place to touch with a probe is easier when the point is first found on the computer screen. These are two very detailed images of the Sockit board by Terasic and Arrow Electronics (and [...]

Tcl scripting: Which version of Quartus am I running?

The short answer is $quartus(version). Those familiar with Tcl immediately tell that there’s a named array (hash), $quartus, containing a key “version” which returns the full revision name. So, entering an interactive session, $ quartus_sh -s Info: ******************************************************************* Info: Running Quartus II 32-bit Shell Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web [...]

Cyclone V SoC: Two masters on a bus errs on ID signal width

While working on Xillinux‘ port to Altera (the SocKit board, actually), I needed to connect two AXI masters: One for the VGA adapter, and one for the Xillybus IP core. Unlike Zynq, Altera’s HPS offers only one AXI slave port, so it’s up to Qsys to generate arbitration logic, implemented in the logic fabric, to [...]

DDR memory bit errors with SocKit (Cyclone V SoC device)

The problem There seems to be a minor DDR memory reliability issue with the SocKit, having the 5CSXFC6D6F31C8NES device marked “F AAAAU1319A”. This can be detected by copying pseudorandom data from one buffer to another repeatedly, and then comparing the data between the buffers. The buffers must be large, to make sure the cache is [...]

Experimenting with SDC/Tcl wildcards: Quartus TimingQuest Timing Analyzer

Wildcards There is a certain confusion regarding how wildcards are matched in the SDC file (in fact, by the Tcl commands), which is why full paths are often used. This causes overloaded SDC files that don’t survive changes in the hierarchy. For example, regarding get_pins, the SDC and TimeQuest API Reference Manual page 2-15 states [...]

A list of Altera SoC FPGA development boards

I’m trying to find Altera boards that have an embedded ARM (Cortex A9) on them. This is my list so far. If you know about another board, please comment below. I’ll remove the comment and add the board to the list. Cyclone V Altera’s official Cyclone SoC Development kit with a 5CSXFC6D6F31C8NES. The Sockit by [...]