Quartus’ timing analysis on set_input_delay and set_output_delay constraints

This post was written by eli on April 6, 2017
Posted Under: Altera,FPGA

OK, what’s this?

This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints.

TimeQuest (Quartus’ timing analyzer) performs a four-corner check (max/min temperature, max/min voltage) and picks the worst slack. In the examples below, the worst case of these four corners is shown. It’s not exactly clear why a certain delay model becomes the worst case all the times.

As mentioned on the other post, the relevant timing constraints were:

create_clock -name theclk -period 20 [get_ports test_clk]
set_output_delay -clock theclk -max 8 [get_ports test_out]
set_output_delay -clock theclk -min -3 [get_ports test_out]
set_input_delay -clock theclk -max 4 [get_ports test_in]
set_input_delay -clock theclk -min 2 [get_ports test_in]

set_input_delay -max timing analysis (setup)

Delay Model:
    Slow 1100mV 0C Model

+------------------------------------------------------------------------------------------------------+
; Summary of Paths                                                                                     ;
+--------+-----------+-----------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node ; To Node   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-----------+--------------+-------------+--------------+------------+------------+
; 12.341 ; test_in   ; test_samp ; theclk       ; theclk      ; 20.000       ; 3.940      ; 7.499      ;
+--------+-----------+-----------+--------------+-------------+--------------+------------+------------+

Path #1: Setup slack is 12.341
===============================================================================
+--------------------------------+
; Path Summary                   ;
+--------------------+-----------+
; Property           ; Value     ;
+--------------------+-----------+
; From Node          ; test_in   ;
; To Node            ; test_samp ;
; Launch Clock       ; theclk    ;
; Latch Clock        ; theclk    ;
; Data Arrival Time  ; 11.499    ;
; Data Required Time ; 23.840    ;
; Slack              ; 12.341    ;
+--------------------+-----------+

+---------------------------------------------------------------------------------------+
; Statistics                                                                            ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Property                  ; Value  ; Count ; Total Delay ; % of Total ; Min   ; Max   ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Setup Relationship        ; 20.000 ;       ;             ;            ;       ;       ;
; Clock Skew                ; 3.940  ;       ;             ;            ;       ;       ;
; Data Delay                ; 7.499  ;       ;             ;            ;       ;       ;
; Number of Logic Levels    ;        ; 1     ;             ;            ;       ;       ;
; Physical Delays           ;        ;       ;             ;            ;       ;       ;
;  Arrival Path             ;        ;       ;             ;            ;       ;       ;
;   Clock                   ;        ;       ;             ;            ;       ;       ;
;    Clock Network (Lumped) ;        ; 1     ; 0.000       ;            ; 0.000 ; 0.000 ;
;   Data                    ;        ;       ;             ;            ;       ;       ;
;    IC                     ;        ; 2     ; 2.447       ; 33         ; 0.000 ; 2.447 ;
;    Cell                   ;        ; 2     ; 5.052       ; 67         ; 0.652 ; 4.400 ;
;  Required Path            ;        ;       ;             ;            ;       ;       ;
;   Clock                   ;        ;       ;             ;            ;       ;       ;
;    Clock Network (Lumped) ;        ; 1     ; 3.940       ; 100        ; 3.940 ; 3.940 ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
Note: Negative delays are omitted from totals when calculating percentages

+-----------------------------------------------------------------------------------+
; Data Arrival Path                                                                 ;
+----------+---------+----+------+--------+-------------------+---------------------+
; Total    ; Incr    ; RF ; Type ; Fanout ; Location          ; Element             ;
+----------+---------+----+------+--------+-------------------+---------------------+
; 0.000    ; 0.000   ;    ;      ;        ;                   ; launch edge time    ;
; 0.000    ; 0.000   ;    ;      ;        ;                   ; clock path          ;
;   0.000  ;   0.000 ; R  ;      ;        ;                   ; clock network delay ;
; 4.000    ; 4.000   ; F  ; iExt ; 1      ; PIN_AP17          ; test_in             ;
; 11.499   ; 7.499   ;    ;      ;        ;                   ; data path           ;
;   4.000  ;   0.000 ; FF ; IC   ; 1      ; IOIBUF_X48_Y0_N58 ; test_in~input|i     ;
;   8.400  ;   4.400 ; FF ; CELL ; 1      ; IOIBUF_X48_Y0_N58 ; test_in~input|o     ;
;   10.847 ;   2.447 ; FF ; IC   ; 1      ; FF_X48_Y2_N40     ; test_samp|asdata    ;
;   11.499 ;   0.652 ; FF ; CELL ; 1      ; FF_X48_Y2_N40     ; test_samp           ;
+----------+---------+----+------+--------+-------------------+---------------------+

+-------------------------------------------------------------------------------+
; Data Required Path                                                            ;
+----------+---------+----+------+--------+---------------+---------------------+
; Total    ; Incr    ; RF ; Type ; Fanout ; Location      ; Element             ;
+----------+---------+----+------+--------+---------------+---------------------+
; 20.000   ; 20.000  ;    ;      ;        ;               ; latch edge time     ;
; 23.940   ; 3.940   ;    ;      ;        ;               ; clock path          ;
;   23.940 ;   3.940 ; R  ;      ;        ;               ; clock network delay ;
; 23.840   ; -0.100  ;    ;      ;        ;               ; clock uncertainty   ;
; 23.840   ; 0.000   ;    ; uTsu ; 1      ; FF_X48_Y2_N40 ; test_samp           ;
+----------+---------+----+------+--------+---------------+---------------------+

This analysis starts in “Data Arrival Path” with setting the input port (test_in) at 4 ns as specified in the max input delay constraint, and continues that data path. Together with the FPGA’s own data path delay (7.499 ns), the total data path delay stands at 11.499 ns.

The clock path is the calculated in “Data Required Path”, starting from the following clock at 20 ns. The clock travels from the input pin to the flip-flop (with no clock network delay compensation, since no PLL is involved), taking into account the calculated jitter. All in all, the clock path ends at 23.840 ns, which is 12.341 ns after the data arrived to the flip-flop, which is this constraint’s slack.

It’s simple to see from this analysis that the max input delay is the clock-to-output ( + board delay), as it’s the starting time of the data path.

set_input_delay -min timing analysis (hold)

Delay Model:
    Slow 1100mV 85C Model

+-----------------------------------------------------------------------------------------------------+
; Summary of Paths                                                                                    ;
+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
; 0.770 ; test_in   ; test_samp ; theclk       ; theclk      ; 0.000        ; 4.287      ; 3.057      ;
+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+

Path #1: Hold slack is 0.770
===============================================================================
+--------------------------------+
; Path Summary                   ;
+--------------------+-----------+
; Property           ; Value     ;
+--------------------+-----------+
; From Node          ; test_in   ;
; To Node            ; test_samp ;
; Launch Clock       ; theclk    ;
; Latch Clock        ; theclk    ;
; Data Arrival Time  ; 5.057     ;
; Data Required Time ; 4.287     ;
; Slack              ; 0.770     ;
+--------------------+-----------+

+--------------------------------------------------------------------------------------+
; Statistics                                                                           ;
+---------------------------+-------+-------+-------------+------------+-------+-------+
; Property                  ; Value ; Count ; Total Delay ; % of Total ; Min   ; Max   ;
+---------------------------+-------+-------+-------------+------------+-------+-------+
; Hold Relationship         ; 0.000 ;       ;             ;            ;       ;       ;
; Clock Skew                ; 4.287 ;       ;             ;            ;       ;       ;
; Data Delay                ; 3.057 ;       ;             ;            ;       ;       ;
; Number of Logic Levels    ;       ; 1     ;             ;            ;       ;       ;
; Physical Delays           ;       ;       ;             ;            ;       ;       ;
;  Arrival Path             ;       ;       ;             ;            ;       ;       ;
;   Clock                   ;       ;       ;             ;            ;       ;       ;
;    Clock Network (Lumped) ;       ; 1     ; 0.000       ;            ; 0.000 ; 0.000 ;
;   Data                    ;       ;       ;             ;            ;       ;       ;
;    IC                     ;       ; 2     ; 2.028       ; 66         ; 0.000 ; 2.028 ;
;    Cell                   ;       ; 2     ; 1.029       ; 34         ; 0.290 ; 0.739 ;
;  Required Path            ;       ;       ;             ;            ;       ;       ;
;   Clock                   ;       ;       ;             ;            ;       ;       ;
;    Clock Network (Lumped) ;       ; 1     ; 4.287       ; 100        ; 4.287 ; 4.287 ;
+---------------------------+-------+-------+-------------+------------+-------+-------+
Note: Negative delays are omitted from totals when calculating percentages

+----------------------------------------------------------------------------------+
; Data Arrival Path                                                                ;
+---------+---------+----+------+--------+-------------------+---------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location          ; Element             ;
+---------+---------+----+------+--------+-------------------+---------------------+
; 0.000   ; 0.000   ;    ;      ;        ;                   ; launch edge time    ;
; 0.000   ; 0.000   ;    ;      ;        ;                   ; clock path          ;
;   0.000 ;   0.000 ; R  ;      ;        ;                   ; clock network delay ;
; 2.000   ; 2.000   ; R  ; iExt ; 1      ; PIN_AP17          ; test_in             ;
; 5.057   ; 3.057   ;    ;      ;        ;                   ; data path           ;
;   2.000 ;   0.000 ; RR ; IC   ; 1      ; IOIBUF_X48_Y0_N58 ; test_in~input|i     ;
;   2.739 ;   0.739 ; RR ; CELL ; 1      ; IOIBUF_X48_Y0_N58 ; test_in~input|o     ;
;   4.767 ;   2.028 ; RR ; IC   ; 1      ; FF_X48_Y2_N40     ; test_samp|asdata    ;
;   5.057 ;   0.290 ; RR ; CELL ; 1      ; FF_X48_Y2_N40     ; test_samp           ;
+---------+---------+----+------+--------+-------------------+---------------------+

+------------------------------------------------------------------------------+
; Data Required Path                                                           ;
+---------+---------+----+------+--------+---------------+---------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location      ; Element             ;
+---------+---------+----+------+--------+---------------+---------------------+
; 0.000   ; 0.000   ;    ;      ;        ;               ; latch edge time     ;
; 4.287   ; 4.287   ;    ;      ;        ;               ; clock path          ;
;   4.287 ;   4.287 ; R  ;      ;        ;               ; clock network delay ;
; 4.287   ; 0.000   ;    ;      ;        ;               ; clock uncertainty   ;
; 4.287   ; 0.000   ;    ; uTh  ; 1      ; FF_X48_Y2_N40 ; test_samp           ;
+---------+---------+----+------+--------+---------------+---------------------+

This analysis starts in “Data Arrival Path” with setting the input port (test_in) at 2 ns as specified in the min input delay constraint, and continues that data path. Together with the FPGA’s own data path delay (3.057 ns), the total data path delay stands at 5.057 ns.

The clock path is the calculated in “Data Required Path”, starting from the same clock edge at 0 ns. After all, this is a hold calculation, so the question is whether the mat wasn’t swept under the feet of the sampling flip-flop before it managed to sample it.

The clock travels from the input pin to the flip-flop (with no clock network delay compensation, since no PLL is involved), taking into account the calculated jitter. All in all, the clock path ends at 4.287 ns, which is 0.770 ns earlier than the data switching, which is also the slack.

It’s simple to see from this analysis that the min input delay is the minimal clock-to-output, as it’s the starting time of the data path.

set_output_delay -max timing analysis (setup)

Delay Model:
    Slow 1100mV 85C Model

+--------------------------------------------------------------------------------------------------------+
; Summary of Paths                                                                                       ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node     ; To Node  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+
; 2.651 ; test_out~reg0 ; test_out ; theclk       ; theclk      ; 20.000       ; -5.320     ; 3.929      ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+

Path #1: Setup slack is 2.651
===============================================================================
+------------------------------------+
; Path Summary                       ;
+--------------------+---------------+
; Property           ; Value         ;
+--------------------+---------------+
; From Node          ; test_out~reg0 ;
; To Node            ; test_out      ;
; Launch Clock       ; theclk        ;
; Latch Clock        ; theclk        ;
; Data Arrival Time  ; 9.249         ;
; Data Required Time ; 11.900        ;
; Slack              ; 2.651         ;
+--------------------+---------------+

+---------------------------------------------------------------------------------------+
; Statistics                                                                            ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Property                  ; Value  ; Count ; Total Delay ; % of Total ; Min   ; Max   ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Setup Relationship        ; 20.000 ;       ;             ;            ;       ;       ;
; Clock Skew                ; -5.320 ;       ;             ;            ;       ;       ;
; Data Delay                ; 3.929  ;       ;             ;            ;       ;       ;
; Number of Logic Levels    ;        ; 0     ;             ;            ;       ;       ;
; Physical Delays           ;        ;       ;             ;            ;       ;       ;
;  Arrival Path             ;        ;       ;             ;            ;       ;       ;
;   Clock                   ;        ;       ;             ;            ;       ;       ;
;    Clock Network (Lumped) ;        ; 1     ; 5.320       ; 100        ; 5.320 ; 5.320 ;
;   Data                    ;        ;       ;             ;            ;       ;       ;
;    IC                     ;        ; 1     ; 0.000       ; 0          ; 0.000 ; 0.000 ;
;    Cell                   ;        ; 3     ; 3.929       ; 100        ; 0.000 ; 2.150 ;
;    uTco                   ;        ; 1     ; 0.000       ; 0          ; 0.000 ; 0.000 ;
;  Required Path            ;        ;       ;             ;            ;       ;       ;
;   Clock                   ;        ;       ;             ;            ;       ;       ;
;    Clock Network (Lumped) ;        ; 1     ; 0.000       ;            ; 0.000 ; 0.000 ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
Note: Negative delays are omitted from totals when calculating percentages

+---------------------------------------------------------------------------------------+
; Data Arrival Path                                                                     ;
+---------+---------+----+------+--------+------------------------+---------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location               ; Element             ;
+---------+---------+----+------+--------+------------------------+---------------------+
; 0.000   ; 0.000   ;    ;      ;        ;                        ; launch edge time    ;
; 5.320   ; 5.320   ;    ;      ;        ;                        ; clock path          ;
;   5.320 ;   5.320 ; R  ;      ;        ;                        ; clock network delay ;
; 9.249   ; 3.929   ;    ;      ;        ;                        ; data path           ;
;   5.320 ;   0.000 ;    ; uTco ; 1      ; DDIOOUTCELL_X48_Y0_N50 ; test_out~reg0       ;
;   7.099 ;   1.779 ; FF ; CELL ; 1      ; DDIOOUTCELL_X48_Y0_N50 ; test_out~reg0|q     ;
;   7.099 ;   0.000 ; FF ; IC   ; 1      ; IOOBUF_X48_Y0_N42      ; test_out~output|i   ;
;   9.249 ;   2.150 ; FF ; CELL ; 1      ; IOOBUF_X48_Y0_N42      ; test_out~output|o   ;
;   9.249 ;   0.000 ; FF ; CELL ; 0      ; PIN_AN17               ; test_out            ;
+---------+---------+----+------+--------+------------------------+---------------------+

+--------------------------------------------------------------------------+
; Data Required Path                                                       ;
+----------+---------+----+------+--------+----------+---------------------+
; Total    ; Incr    ; RF ; Type ; Fanout ; Location ; Element             ;
+----------+---------+----+------+--------+----------+---------------------+
; 20.000   ; 20.000  ;    ;      ;        ;          ; latch edge time     ;
; 20.000   ; 0.000   ;    ;      ;        ;          ; clock path          ;
;   20.000 ;   0.000 ; R  ;      ;        ;          ; clock network delay ;
; 19.900   ; -0.100  ;    ;      ;        ;          ; clock uncertainty   ;
; 11.900   ; -8.000  ; F  ; oExt ; 0      ; PIN_AN17 ; test_out            ;
+----------+---------+----+------+--------+----------+---------------------+

Since the purpose of this analysis is to measure the output delay, it starts off in “Data Arrival Path” with the clock edge, adds the clock network delay to the flip-flop, and then goes along the data path until the physical output is stable, calculated at 9.249 ns.

This is compared with the time of the following clock at 20 ns, minus the output delay. Minus the possible jitter (0.1 ns in the case above). Data arrived at 9.249 ns, the moment that counts is at 11.9 ns, so there’s a 2.651 ns slack.

This demonstrates why set_output_delay -max is the setup time of the receiver: The output delay is reduced from the following clock’s time position, and that’s the goal to meet. That’s exactly the definition of setup time: How long before the following clock the data must be stable.

set_output_delay -min timing analysis (hold)

Delay Model:
    Fast 1100mV 0C Model

+--------------------------------------------------------------------------------------------------------+
; Summary of Paths                                                                                       ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node     ; To Node  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+
; 1.275 ; test_out~reg0 ; test_out ; theclk       ; theclk      ; 0.000        ; -2.255     ; 2.020      ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+

Path #1: Hold slack is 1.275
===============================================================================
+------------------------------------+
; Path Summary                       ;
+--------------------+---------------+
; Property           ; Value         ;
+--------------------+---------------+
; From Node          ; test_out~reg0 ;
; To Node            ; test_out      ;
; Launch Clock       ; theclk        ;
; Latch Clock        ; theclk        ;
; Data Arrival Time  ; 4.275         ;
; Data Required Time ; 3.000         ;
; Slack              ; 1.275         ;
+--------------------+---------------+

+---------------------------------------------------------------------------------------+
; Statistics                                                                            ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Property                  ; Value  ; Count ; Total Delay ; % of Total ; Min   ; Max   ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Hold Relationship         ; 0.000  ;       ;             ;            ;       ;       ;
; Clock Skew                ; -2.255 ;       ;             ;            ;       ;       ;
; Data Delay                ; 2.020  ;       ;             ;            ;       ;       ;
; Number of Logic Levels    ;        ; 0     ;             ;            ;       ;       ;
; Physical Delays           ;        ;       ;             ;            ;       ;       ;
;  Arrival Path             ;        ;       ;             ;            ;       ;       ;
;   Clock                   ;        ;       ;             ;            ;       ;       ;
;    Clock Network (Lumped) ;        ; 1     ; 2.255       ; 100        ; 2.255 ; 2.255 ;
;   Data                    ;        ;       ;             ;            ;       ;       ;
;    IC                     ;        ; 1     ; 0.000       ; 0          ; 0.000 ; 0.000 ;
;    Cell                   ;        ; 3     ; 2.020       ; 100        ; 0.000 ; 1.296 ;
;    uTco                   ;        ; 1     ; 0.000       ; 0          ; 0.000 ; 0.000 ;
;  Required Path            ;        ;       ;             ;            ;       ;       ;
;   Clock                   ;        ;       ;             ;            ;       ;       ;
;    Clock Network (Lumped) ;        ; 1     ; 0.000       ;            ; 0.000 ; 0.000 ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
Note: Negative delays are omitted from totals when calculating percentages

+---------------------------------------------------------------------------------------+
; Data Arrival Path                                                                     ;
+---------+---------+----+------+--------+------------------------+---------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location               ; Element             ;
+---------+---------+----+------+--------+------------------------+---------------------+
; 0.000   ; 0.000   ;    ;      ;        ;                        ; launch edge time    ;
; 2.255   ; 2.255   ;    ;      ;        ;                        ; clock path          ;
;   2.255 ;   2.255 ; R  ;      ;        ;                        ; clock network delay ;
; 4.275   ; 2.020   ;    ;      ;        ;                        ; data path           ;
;   2.255 ;   0.000 ;    ; uTco ; 1      ; DDIOOUTCELL_X48_Y0_N50 ; test_out~reg0       ;
;   2.979 ;   0.724 ; RR ; CELL ; 1      ; DDIOOUTCELL_X48_Y0_N50 ; test_out~reg0|q     ;
;   2.979 ;   0.000 ; RR ; IC   ; 1      ; IOOBUF_X48_Y0_N42      ; test_out~output|i   ;
;   4.275 ;   1.296 ; RR ; CELL ; 1      ; IOOBUF_X48_Y0_N42      ; test_out~output|o   ;
;   4.275 ;   0.000 ; RR ; CELL ; 0      ; PIN_AN17               ; test_out            ;
+---------+---------+----+------+--------+------------------------+---------------------+

+-------------------------------------------------------------------------+
; Data Required Path                                                      ;
+---------+---------+----+------+--------+----------+---------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location ; Element             ;
+---------+---------+----+------+--------+----------+---------------------+
; 0.000   ; 0.000   ;    ;      ;        ;          ; latch edge time     ;
; 0.000   ; 0.000   ;    ;      ;        ;          ; clock path          ;
;   0.000 ;   0.000 ; R  ;      ;        ;          ; clock network delay ;
; 0.000   ; 0.000   ;    ;      ;        ;          ; clock uncertainty   ;
; 3.000   ; 3.000   ; R  ; oExt ; 0      ; PIN_AN17 ; test_out            ;
+---------+---------+----+------+--------+----------+---------------------+

This analysis is similar to the max output delay, only it’s calculated against the same clock edge (and not the following one).

As before, the data path continues the clock path until the physical output is stable, calculated at 4.275 ns.

This is compared with the time of the same clock at 0 ns, minus the output delay. Recall that the min output delay was negative (-3 ns), which is why it appears as a positive number in the calculation.

Conclusion: Data was stable until 4.275 ns, and needs to be stable until 3 ns. That’s fine, with a 1.275 ns slack.

This demonstrates why set_output_delay -min is minus the hold time of the receiver: The given output delay with reversed sign is used as the time which the data path delay must exceed. In other words, the data must be stable for that long after the clock. This is the definition of hold time.

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