Comments on: Signed arithmetics in Verilog: The only rule one needs to know http://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/ Anything I found worthy to write down. Sun, 29 Nov 2020 17:07:56 +0000 hourly 1 http://wordpress.org/?v=3.1.2 By: Dave http://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/comment-page-1/#comment-1526 Dave Sun, 15 Nov 2020 19:26:23 +0000 http://billauer.co.il/blog/?p=3289#comment-1526 I avoid declaring signed type altogether. Much easier to just manage 2s complement sign explicitly. I have seen inconsistency in how signed type is handled between different simulators and compilers. I avoid declaring signed type altogether. Much easier to just manage 2s complement sign explicitly. I have seen inconsistency in how signed type is handled between different simulators and compilers.

]]> By: Tim http://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/comment-page-1/#comment-1436 Tim Tue, 23 Jul 2019 11:58:30 +0000 http://billauer.co.il/blog/?p=3289#comment-1436 Hey Eli, thanks for your great blog, it helped me a lot so far! :) Just recently I realized another issue with Verilog signed operations in Cadence: I declared two 16-bit operands, one signed & one unsigned. Then I executed the following operation: prod = $signed(op_a_signed * op_b_unsigned); and it turned out that the result returned by the typecast $signed() was also a 16-bit value (LSBs) unlike the result reg (prod) which was declared as a 32-bit value. So apparently the typecasts $signed() or $unsigned() return a value with bitness of the operands, not the bitness of the value the result is returned to. Maybe this helps someone! Hey Eli,

thanks for your great blog, it helped me a lot so far! :)

Just recently I realized another issue with Verilog signed operations in Cadence:
I declared two 16-bit operands, one signed & one unsigned. Then I executed the following operation:

prod = $signed(op_a_signed * op_b_unsigned);

and it turned out that the result returned by the typecast $signed() was also a 16-bit value (LSBs) unlike the result reg (prod) which was declared as a 32-bit value.

So apparently the typecasts $signed() or $unsigned() return a value with bitness of the operands, not the bitness of the value the result is returned to.

Maybe this helps someone!

]]> By: Yan http://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/comment-page-1/#comment-1318 Yan Wed, 07 Mar 2018 01:27:21 +0000 http://billauer.co.il/blog/?p=3289#comment-1318 Good point! Good point!

]]> By: Pedro http://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/comment-page-1/#comment-1214 Pedro Thu, 27 Oct 2016 18:06:08 +0000 http://billauer.co.il/blog/?p=3289#comment-1214 I also find that arrays of signed numbers do not work as expected. Verilog signed math is fraught with hazards. I also find that arrays of signed numbers do not work as expected. Verilog signed math is fraught with hazards.

]]> By: SHUBHAM http://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/comment-page-1/#comment-1180 SHUBHAM Thu, 21 Apr 2016 18:35:33 +0000 http://billauer.co.il/blog/?p=3289#comment-1180 thanks to you bro thanks to you bro

]]> By: Anonymous http://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/comment-page-1/#comment-1075 Anonymous Tue, 31 Mar 2015 16:52:39 +0000 http://billauer.co.il/blog/?p=3289#comment-1075 Thanks Thanks

]]> By: Oggy http://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/comment-page-1/#comment-946 Oggy Mon, 19 May 2014 13:35:43 +0000 http://billauer.co.il/blog/?p=3289#comment-946 Thank you, man. I thought I was crazy. Thank you, man. I thought I was crazy.

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